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ESP8266 Memory Map
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== <span id="map_iram">Mappable Instruction RAM (0x40108000 - 0x4010FFFF)</span> == Instruction RAM/FLASH cache ram. OTA bootloader uses it. Apparently mapped as two separate 16 KB blocks (0x4000): * 0x40108000 - 0x4010BFFF: Mapped if bit 4 (bit mask 0x10) is clear in the dport0 register 0x3ff00024 * 0x4010C000 - 0x4010FFFF: Mapped if bit 3 (bit mask 0x8) is clear in the dport0 register 0x3ff00024 {{question|How is this related to the SPI Flash cache? Why is it possible to unmap it?}} {{hypothesis|This may be the same physical RAM as is used for the SPI Flash cache, and these bits just switch it between being used for cache vs. for general-purpose IRAM. If so, this implies it may be possible to pick between using 16 KB vs 32 KB cache size (and use the rest for IRAM)}} {{question|Assuming the above, does this have anything to do with the mysterious third parameter to [[Cache_Read_Enable]]?}}
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