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=== API === Interrupts() and noInterrupts(): (本质都是直接设置 primask 这个寄存器) <source lang=cpp> /* * Enables IRQ interrupts by clearing the I-bit in the CPSR. * Can only be executed in Privileged modes. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } /* * Disables IRQ interrupts by setting the I-bit in the CPSR. * Can only be executed in Privileged modes. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } </source> Suggest to use: (@ emlib/src/em_core.c or inc/em_core.h) <source lang=cpp> CORE_DECLARE_IRQ_STATE; CORE_ENTER_CRITICAL(); your_code CORE_EXIT_CRITICAL() ; or: CORE_DECLARE_IRQ_STATE; CORE_ENTER_ATOMIC(); your_code CORE_EXIT_ATOMIC(); </source> <b>CRITICAL</b> section: Inside a critical sections all interrupts are disabled (except for fault handlers). The PRIMASK register is always used for interrupt disable/enable. <b>ATOMIC</b> section: This type of section is configurable and the default method is to use PRIMASK. With BASEPRI configuration, interrupts with priority equal to or lower than a given configurable level are disabled. The interrupt disable priority level is defined at compile time. The BASEPRI register is not available for all architectures. <b>NVIC mask</b> section: Disable NVIC (external interrupts) on an individual manner. '''获取 primask 寄存器的值并保存之:''' <source lang=cpp> /* * Returns the current state of the priority mask bit from the Priority Mask Register. * Priority Mask value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } </source> The exception mask register PRIMASK, that is used for priority boosting. PRIMASK is a special-purpose mask register. <br>
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