查看ESP32 RTC Sleep Prepare的源代码

=== Part One ===

<source lang=c>
int tick_per_us = rtc_get_xtal();

REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, p2 << 27, RTC_CNTL_SOC_CLK_SEL_M);

if (p2 == 1) {
    // PLL clock
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 24, RTC_CNTL_PLL_BUF_WAIT_M);  // PLL wait cycles in slow_clk_rtc
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M);  // XTAL wait cycles in slow_clk_rtc
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);      // CK8M wait cycles in slow_clk_rtc
} else if (p2 == 0) {
    // XTAL clock
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M);   // PLL wait cycles in slow_clk_rtc
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M);  // XTAL wait cycles in slow_clk_rtc
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);      // CK8M wait cycles in slow_clk_rtc
    ets_update_cpu_frequency(ticks_per_us);
    rtc_apb_freq_up(ticks_per_us * 1000000);
} else if (p2 == 2) {
    // CK8M clock
    REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 25, RTC_CNTL_ROM_RAM_POWERUP_TIMER_M);
    REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 16, RTC_CNTL_ROM_RAM_WAIT_TIMER_M);
    REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 9, RTC_CNTL_WIFI_POWERUP_TIMER_M);
    REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1, RTC_CNTL_WAIT_TIMER_M); 

    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M);  // PLL wait cycles in slow_clk_rtc
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x3 << 14, RTC_CNTL_XTL_BUF_WAIT_M);  // XTAL wait cycles in slow_clk_rtc
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);     // CK8M wait cycles in slow_clk_rtc
    ets_update_cpu_frequency(8);
    rtc_apb_freq_up(8000000);
}

</source>

<source lang=bash>
0x4008f1c4 <rtc_slp_prep>: entry	a1, 48
0x4008f1c7 <rtc_slp_prep+3>: call8	0x4008f9ec <rtc_get_xtal>
0x4008f1ca <rtc_slp_prep+6>: l32r	a8, 0x4008e53c  /* a8 = *(0x4008e5c0) = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */
0x4008f1cd <rtc_slp_prep+9>: l32r	a9, 0x400865dc  /* a9 = *(0x40086674) = 0xe7ffffff */
0x4008f1d0 <rtc_slp_prep+12>: memw
0x4008f1d3 <rtc_slp_prep+15>: l32i	a12, a8, 0  /* a12 = read RTC_CNTL_CLK_CONF_REG = 0x2d580210 */
0x4008f1d6 <rtc_slp_prep+18>: extui	a11, a3, 0, 2   /* a11 = p2[1:0], 2nd_param of rtc_slp_prep */
0x4008f1d9 <rtc_slp_prep+21>: slli	a11, a11, 27
0x4008f1dc <rtc_slp_prep+24>: and	a9, a12, a9
0x4008f1df <rtc_slp_prep+27>: or	a9, a11, a9  /* set BIT[28:27] of RTC_CNTL_CLK_CONF_REG */
0x4008f1e2 <rtc_slp_prep+30>: memw
0x4008f1e5 <rtc_slp_prep+33>: s32i	a9, a8, 0
/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0; SOC clock sel. 0: XTAL  1: PLL  2: CK8M  3: APLL */

0x4008f1e8 <rtc_slp_prep+36>: or	a13, a10, a10  /* a10 is the return value of rtc_get_xtal() */
0x4008f1eb <rtc_slp_prep+39>: bnei	a3, 1, 0x4008f238 <rtc_slp_prep+116>  ------> If (a3 != 1), not the PLL clock, jump

/* Following is related the PLL clock */
0x4008f1ee <rtc_slp_prep+42>: l32r	a3, 0x4008e57c  /* a3 = 0x3ff4801c, RTC_CNTL_TIMER1_REG */
0x4008f1f1 <rtc_slp_prep+45>: l32r	a8, 0x40084ce0  /* a8 = 0x00ffffff, BIT[31:24] */
0x4008f1f4 <rtc_slp_prep+48>: memw
0x4008f1f7 <rtc_slp_prep+51>: l32i.n	a9, a3, 0
0x4008f1f9 <rtc_slp_prep+53>: and	a8, a9, a8
0x4008f1fc <rtc_slp_prep+56>: l32r	a9, 0x4008f19c  /* a9 = 0x14000000 */
0x4008f1ff <rtc_slp_prep+59>: or	a8, a8, a9       /* set BIT[31:24] = 0x14 */
0x4008f202 <rtc_slp_prep+62>: memw
0x4008f205 <rtc_slp_prep+65>: s32i.n	a8, a3, 0  /* Write back to RTC_CNTL_TIMER1_REG */
0x4008f207 <rtc_slp_prep+67>: memw
/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; PLL wait cycles in slow_clk_rtc */

0x4008f20a <rtc_slp_prep+70>: l32i.n	a9, a3, 0
0x4008f20c <rtc_slp_prep+72>: l32r	a8, 0x4008e580  /* a8 = 0xff003fff, BIT[23:14] */
0x4008f20f <rtc_slp_prep+75>: and	a8, a9, a8
0x4008f212 <rtc_slp_prep+78>: l32r	a9, 0x4008f1a0  /* a9 = 0x00050000 */
0x4008f215 <rtc_slp_prep+81>: or	a8, a8, a9     /* set BIT[23:14] = 0x14 */
0x4008f218 <rtc_slp_prep+84>: memw
0x4008f21b <rtc_slp_prep+87>: s32i.n	a8, a3, 0
0x4008f21d <rtc_slp_prep+89>: memw
/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; XTAL wait cycles in slow_clk_rtc */

0x4008f220 <rtc_slp_prep+92>: l32i.n	a9, a3, 0
0x4008f222 <rtc_slp_prep+94>: l32r	a8, 0x4008e584  /* a8 = 0xffffc03f, BIT[13:6] */
0x4008f225 <rtc_slp_prep+97>: and	a8, a9, a8
0x4008f228 <rtc_slp_prep+100>: movi	a9, 0x500
0x4008f22b <rtc_slp_prep+103>: or	a8, a8, a9  /* set BIT[13:6] = 0x14 */
0x4008f22e <rtc_slp_prep+106>: memw
0x4008f231 <rtc_slp_prep+109>: s32i.n	a8, a3, 0
/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; CK8M wait cycles in slow_clk_rtc */

0x4008f233 <rtc_slp_prep+111>: j	0x4008f34e <rtc_slp_prep+394>  ------> jump 394

0x4008f235 <rtc_slp_prep+113>: ill  (0x0000)  <------------- openocd/gdb bug

>>>>>>>>>
0x4008f238 <rtc_slp_prep+116>: bnez	a3, 0x4008f298 <rtc_slp_prep+212> if (a3 != 0), not the XTAL clock, jump --------->

/* Following should be related to the XTAL clock */
0x4008f23b <rtc_slp_prep+119>: l32r	a3, 0x4008e57c  /* a3 = 0x3ff4801c, RTC_CNTL_TIMER1_REG */
0x4008f23e <rtc_slp_prep+122>: l32r	a8, 0x40084ce0  /* a8 = 0x00ffffff, BIT[31:24] */
0x4008f241 <rtc_slp_prep+125>: memw
0x4008f244 <rtc_slp_prep+128>: l32i.n	a9, a3, 0
0x4008f246 <rtc_slp_prep+130>: and	a8, a9, a8
0x4008f249 <rtc_slp_prep+133>: l32r	a9, 0x40084c80  /* a9 = 0x01000000 */
0x4008f24c <rtc_slp_prep+136>: or	a8, a8, a9  /* set BIT[31:24] = 0x1 */
0x4008f24f <rtc_slp_prep+139>: memw
0x4008f252 <rtc_slp_prep+142>: s32i.n	a8, a3, 0
0x4008f254 <rtc_slp_prep+144>: memw
/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; PLL wait cycles in slow_clk_rtc */

0x4008f257 <rtc_slp_prep+147>: l32i.n	a9, a3, 0
0x4008f259 <rtc_slp_prep+149>: l32r	a8, 0x4008e580  /* a8 = 0xff003fff, BIT[23:14] */
0x4008f25c <rtc_slp_prep+152>: and	a8, a9, a8
0x4008f25f <rtc_slp_prep+155>: l32r	a9, 0x4008f1a0  /* a9 = 0x00050000 */
0x4008f262 <rtc_slp_prep+158>: or	a8, a8, a9     /* set BIT[23:14] = 0x14 */
0x4008f265 <rtc_slp_prep+161>: memw
0x4008f268 <rtc_slp_prep+164>: s32i.n	a8, a3, 0
0x4008f26a <rtc_slp_prep+166>: memw
/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; XTAL wait cycles in slow_clk_rtc */

0x4008f26d <rtc_slp_prep+169>: l32i.n	a9, a3, 0
0x4008f26f <rtc_slp_prep+171>: l32r	a8, 0x4008e584  /* a8 = 0xffffc03f, BIT[13:6] */
0x4008f272 <rtc_slp_prep+174>: and	a8, a9, a8
0x4008f275 <rtc_slp_prep+177>: movi	a9, 0x500
0x4008f278 <rtc_slp_prep+180>: or	a8, a8, a9  /* set BIT[13:6] = 0x14 */
0x4008f27b <rtc_slp_prep+183>: memw
0x4008f27e <rtc_slp_prep+186>: s32i.n	a8, a3, 0
/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; CK8M wait cycles in slow_clk_rtc */

0x4008f280 <rtc_slp_prep+188>: s32i	a13, a1, 0  /* store the a13 into stack */

0x4008f283 <rtc_slp_prep+191>: l32r	a8, 0x4008f1c0  /* a8 = 0x40008550, ets_update_cpu_frequency */
0x4008f286 <rtc_slp_prep+194>: callx8	a8      /* ets_update_cpu_frequency(uint32_t ticks_per_us) */
/* a10 is the ticks_per_us, get from call rtc_get_xtal() */

0x4008f289 <rtc_slp_prep+197>: l32i.n	a13, a1, 0  /* restore a13 */

0x4008f28b <rtc_slp_prep+199>: l32r	a10, 0x40080574  /* a10 = 0x000f4240 */
0x4008f28e <rtc_slp_prep+202>: mull	a10, a13, a10  /* a10 = rtc_get_xtal() * 1000000 */
0x4008f291 <rtc_slp_prep+205>: call8	0x4008fa40 <rtc_apb_freq_up>
0x4008f294 <rtc_slp_prep+208>: j	0x4008f34e <rtc_slp_prep+394>      -----------------------> jump 394
0x4008f296 <rtc_slp_prep+210>:	0x0000             <-------------- openocd/gdb bug

>>>>>>>>>>>>>>>>>
0x4008f298 <rtc_slp_prep+212>:	beqi	a3, 2, 0x4008f29e <rtc_slp_prep+218>  /* if (a3 == 2); CK8M clock, jump */
0x4008f29b <rtc_slp_prep+215>:	j	0x4008f34e <rtc_slp_prep+394>    -------------------------> jump 394

/* Following is related to CK8M clock */
0x4008f29e <rtc_slp_prep+218>:	l32r	a3, 0x4008f1a4  /* a3 = 0x3ff48024, RTC_CNTL_TIMER3_REG */
0x4008f2a1 <rtc_slp_prep+221>: l32r	a8, 0x4008f050  /* a8 = 0x01ffffff, BIT[31:25] */
0x4008f2a4 <rtc_slp_prep+224>: memw
0x4008f2a7 <rtc_slp_prep+227>: l32i	a9, a3, 0  /* a9 = 0x14160a08 */
0x4008f2aa <rtc_slp_prep+230>: movi	a10, 1
0x4008f2ad <rtc_slp_prep+233>: and	a8, a9, a8
0x4008f2b0 <rtc_slp_prep+236>: l32r	a9, 0x40084c00  /* a9 = 0x02000000 */
0x4008f2b3 <rtc_slp_prep+239>: or	a8, a8, a9  /* set BIT[31:25] = 0x1 */
0x4008f2b6 <rtc_slp_prep+242>: memw
0x4008f2b9 <rtc_slp_prep+245>: s32i	a8, a3, 0
0x4008f2bc <rtc_slp_prep+248>: memw
/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */

0x4008f2bf <rtc_slp_prep+251>: l32i.n	a9, a3, 0
0x4008f2c1 <rtc_slp_prep+253>: l32r	a8, 0x4008ba60  /* a8 = 0xfe00ffff, BIT[24:16] */
0x4008f2c4 <rtc_slp_prep+256>: and	a8, a9, a8
0x4008f2c7 <rtc_slp_prep+259>: l32r	a9, 0x40088a98  /* a9 = 0x00010000 */
0x4008f2ca <rtc_slp_prep+262>: or	a8, a8, a9    /* set BIT[24:16] = 0x1 */
0x4008f2cd <rtc_slp_prep+265>: memw
0x4008f2d0 <rtc_slp_prep+268>: s32i.n	a8, a3, 0
0x4008f2d2 <rtc_slp_prep+270>: memw
/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */

0x4008f2d5 <rtc_slp_prep+273>: l32i.n	a9, a3, 0
0x4008f2d7 <rtc_slp_prep+275>: l32r	a8, 0x4008f1a8  /* a8 = 0xffff01ff, BIT[15:9] */
0x4008f2da <rtc_slp_prep+278>: and	a8, a9, a8
0x4008f2dd <rtc_slp_prep+281>: movi	a9, 0x200
0x4008f2e0 <rtc_slp_prep+284>: or	a8, a8, a9     /* set BIT[15:9] = 0x1 */
0x4008f2e3 <rtc_slp_prep+287>: memw
0x4008f2e6 <rtc_slp_prep+290>: s32i.n	a8, a3, 0
0x4008f2e8 <rtc_slp_prep+292>: memw
/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */

0x4008f2eb <rtc_slp_prep+295>: l32i.n	a9, a3, 0
0x4008f2ed <rtc_slp_prep+297>: movi	a8, 0xfffffe00  /* BIT[8:0] */
0x4008f2f0 <rtc_slp_prep+300>: and	a9, a9, a8
0x4008f2f3 <rtc_slp_prep+303>: or	a9, a9, a10    /* a10 == 1, set BIT[8:0] = 1 */
0x4008f2f6 <rtc_slp_prep+306>: l32r	a8, 0x4008e57c  /* a8 = 0x3ff4801c, RTC_CNTL_TIMER1_REG */
0x4008f2f9 <rtc_slp_prep+309>: memw
0x4008f2fc <rtc_slp_prep+312>: s32i.n	a9, a3, 0
0x4008f2fe <rtc_slp_prep+314>: memw
/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */

0x4008f301 <rtc_slp_prep+317>: l32i.n	a9, a8, 0   /* a9 = read TIMER1_REG = 0x14050043 */
0x4008f303 <rtc_slp_prep+319>: l32r	a3, 0x40084ce0  /* a3 = 0x00ffffff, BIT[31:24] */
0x4008f306 <rtc_slp_prep+322>: movi.n	a10, 8
0x4008f308 <rtc_slp_prep+324>: and	a3, a9, a3
0x4008f30b <rtc_slp_prep+327>: l32r	a9, 0x40084c80  /* a9 = 0x01000000 */
0x4008f30e <rtc_slp_prep+330>: or	a3, a3, a9  /* set BIT[31:24] = 0x1 */
0x4008f311 <rtc_slp_prep+333>: memw
0x4008f314 <rtc_slp_prep+336>: s32i.n	a3, a8, 0
0x4008f316 <rtc_slp_prep+338>: memw
/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; PLL wait cycles in slow_clk_rtc*/

0x4008f319 <rtc_slp_prep+341>: l32i.n	a9, a8, 0
0x4008f31b <rtc_slp_prep+343>: l32r	a3, 0x4008e580  /* a3 = 0xff003fff */
0x4008f31e <rtc_slp_prep+346>: and	a3, a9, a3
0x4008f321 <rtc_slp_prep+349>: l32r	a9, 0x4008f1ac  /* a9 = 0x0000c000 */
0x4008f324 <rtc_slp_prep+352>: or	a3, a3, a9     /* set BIT[23:14] = 0x3 */
0x4008f327 <rtc_slp_prep+355>: memw
0x4008f32a <rtc_slp_prep+358>: s32i.n	a3, a8, 0
0x4008f32c <rtc_slp_prep+360>: memw
/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80; XTAL wait cycles in slow_clk_rtc*/

0x4008f32f <rtc_slp_prep+363>: l32i.n	a9, a8, 0
0x4008f331 <rtc_slp_prep+365>: l32r	a3, 0x4008e584  /* a3 = 0xffffc03f */
0x4008f334 <rtc_slp_prep+368>: and	a3, a9, a3
0x4008f337 <rtc_slp_prep+371>: movi	a9, 0x500
0x4008f33a <rtc_slp_prep+374>: or	a3, a3, a9    /* set BIT[13:6] = 0x14 */
0x4008f33d <rtc_slp_prep+377>: memw
0x4008f340 <rtc_slp_prep+380>: s32i.n	a3, a8, 0
/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; CK8M wait cycles in slow_clk_rtc*/

0x4008f342 <rtc_slp_prep+382>: l32r	a8, 0x4008f1c0  /* a8 = 0x40008550, ets_update_cpu_frequency */
0x4008f345 <rtc_slp_prep+385>: callx8	a8   /* a10 = 8 */

0x4008f348 <rtc_slp_prep+388>: l32r	a10, 0x4008f1b0  /* a10 = 0x007a1200 = 8000000 */
0x4008f34b <rtc_slp_prep+391>: call8	0x4008fa40 <rtc_apb_freq_up>  /* rtc_apb_freq_up(8000000) */
</source>

<br>