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=== Detailed Register Description === ==== Line Control Register (LCR) ==== Bit Notes 7 Divisor Latch Access Bit (DLAB) 6 Set Break Enable 3, 4 & 5 Bit 5 Bit 4 Bit 3 Parity Select x x 0 No Parity 0 0 1 Odd Parity 0 1 1 Even Parity 1 0 1 Mark 1 1 1 Space 2 0 One Stop Bit 1 1.5 Stop Bits or 2 Stop Bits 0 & 1 Bit 1 Bit 0 Word Length 0 0 5 Bits 0 1 6 Bits 1 0 7 Bits 1 1 8 Bits This register control the serial data protocol(Tx & Rx). For most serial data transmission, Word Length will be 8 bits. Some military encryption equipment only uses 5 data bits per serial "word", as did some TELEX equipment. Early ASCII teletype terminals only used 7 data bits, and indeed this heritage has been preserved with SMTP format that only uses 7-bit ASCII for e-mail messages. In the case of 5 data bits, the RS-232 protocol instead sends out "1.5 stop bits". What this means is that one serial data "word" istransmitted with only 1 stop bit, and then the next one is transmitted with 2 stop bits. Another thing to keep in mind is that the RS-232 standard only specifies that at least one data bit cycle will be kept a logical "1" at the end of each serial data word (in other words, a complete character from start bit, data bits, parity bits, and stop bits). If you are having timing problems between the two computers but are able to in general get the character sent across one at a time, you might want to add a second stop bit instead of reducing baud rate.This adds a one-bit penalty to the transmission speed per character instead of halving the transmission speed by dropping the baud rate (usually). ==== FIFO Control Register (FCR) ==== Bit Notes 7 & 6 Bit 7 Bit 6 Interrupt Trigger Level (16 byte) Trigger Level (64 byte) 0 0 1 Byte 1 Byte 0 1 4 Bytes 16 Bytes 1 0 8 Bytes 32 Bytes 1 1 14 Bytes 56 Bytes 5 Enable 64 Byte FIFO (16750) 4 Reserved 3 DMA Mode Select 2 Clear Transmit FIFO 1 Clear Receive FIFO 0 Enable FIFOs FCR[0] = 0, turning the UART into 8250 compatibility mode. In effect this also renders the rest of the settings in this register to become useless. FCR[2:1] are "automatically" reset, so if you set either of these to a logical "1" state you will not have to go and put them back to "0" later. On a PC system FCR[3] is of little use and you can safely ignore it. ==== Modem Control Register ==== Bit Notes 7 Reserved 6 Reserved 5 Autoflow Control Enabled (16750) 4 Loopback Mode 3 Auxiliary Output 2 2 Auxiliary Output 1 1 Request To Send (RTS) 0 Data Terminal Ready (DTR) Of these outputs on a typical PC platform, only the Request to Send (RTS) and Data Terminal Ready (DTR) are actually connected to the output of the PC on the DB-9 connector.
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