ESP32 RTC Sleep Prepare - 版本历史

Comcat：/* rtc_slowck_cali */

2016-12-15T11:50:43Z

‎rtc_slowck_cali

Comcat：/* rtc_slowck_cali */

2016-12-15T11:47:16Z

‎rtc_slowck_cali

Comcat：/* rtc_slowck_cali */

2016-12-15T11:24:52Z

‎rtc_slowck_cali

Comcat：/* rtc_ */

2016-12-15T10:49:35Z

‎rtc_

Comcat：/* rtc_slp_prep_lite */

2016-12-15T10:49:11Z

‎rtc_slp_prep_lite

Comcat：/* Overview */

2016-12-08T09:55:36Z

‎Overview

Comcat：/* Part One */

2016-12-08T09:53:04Z

‎Part One

Comcat：/* Part three */

2016-12-08T09:12:04Z

‎Part three

显示差异

Comcat：/* Overview */

2016-12-08T09:11:43Z

‎Overview

显示差异

Comcat：/* Overview */

2016-12-08T09:11:15Z

‎Overview

@@ 第156行： / 第156行： @@
 x4008ed7e <rtc_slowck_cali+170>: l32i.n	a8, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+0x68) */
-x4008ed80 <rtc_slowck_cali+172>: bnone	a8, a9, 0x4008ed7b <rtc_slowck_cali+167>
+x4008ed80 <rtc_slowck_cali+172>: bnone	a8, a9, 0x4008ed7b <rtc_slowck_cali+167> if a8[15] is not set, then branch ---->
 x4008ed83 <rtc_slowck_cali+175>: bnei	a2, 2, 0x4008ed9c <rtc_slowck_cali+200>

@@ 第186行： / 第186行： @@
 x4008edb4 <rtc_slowck_cali+224>: l32r	a2, 0x4008ecd0  /* 0x6001f06c,  (DR_REG_BB_BASE+0x6c) */
 x4008edb7 <rtc_slowck_cali+227>: memw
-x4008edba <rtc_slowck_cali+230>: l32i	a2, a2, 0
+x4008edba <rtc_slowck_cali+230>: l32i	a2, a2, 0  /* a2 = 0x00026280 = 156288 */
 x4008edbd <rtc_slowck_cali+233>: call8	0x4008fb14 <rtc_get_xtal>
-x4008edc0 <rtc_slowck_cali+236>: mull	a12, a10, a3
+x4008edc0 <rtc_slowck_cali+236>: mull	a12, a10, a3  //a12 = 300 * p2,  a10 = 300
-x4008edc3 <rtc_slowck_cali+239>: srli	a10, a2, 7
+x4008edc3 <rtc_slowck_cali+239>: srli	a10, a2, 7  // a10 = 0x4c5 = 1221
-x4008edc6 <rtc_slowck_cali+242>: extui	a11, a2, 20, 12
+x4008edc6 <rtc_slowck_cali+242>: extui	a11, a2, 20, 12  // a11 = 0
-x4008edc9 <rtc_slowck_cali+245>: movi	a13, 0
+x4008edc9 <rtc_slowck_cali+245>: movi	a13, 0  // a13 = 0
-x4008edcc <rtc_slowck_cali+248>: slli	a10, a10, 19
+x4008edcc <rtc_slowck_cali+248>: slli	a10, a10, 19  // a10 = 1221 * 2^19 = 640155648
 x4008edcf <rtc_slowck_cali+251>: call8	0x400e7440 <__udivdi3>
 x4008edd2 <rtc_slowck_cali+254>: mov.n	a2, a10

@@ 第57行： / 第57行： @@
 == rtc_slowck_cali ==
 <source lang=bash>
 x4008ecd4 <rtc_slowck_cali>: entry	a1, 32
 x4008ecd7 <rtc_slowck_cali+3>: bnei	a2, 2, 0x4008ecf1 <rtc_slowck_cali+29>
 x4008ecda <rtc_slowck_cali+6>: l32r	a4, 0x4008e660
 x4008ecdd <rtc_slowck_cali+9>: movi	a8, 0x100
 x4008ece0 <rtc_slowck_cali+12>: memw
 x4008ece3 <rtc_slowck_cali+15>: l32i.n	a9, a4, 0
-x4008ece5 <rtc_slowck_cali+17>: or	a8, a9, a8
+x4008ece5 <rtc_slowck_cali+17>: or	a8, a9, a8  /* set bit[8] */
 x4008ece8 <rtc_slowck_cali+20>: memw
 x4008eceb <rtc_slowck_cali+23>: s32i.n	a8, a4, 0
 x4008eced <rtc_slowck_cali+25>: j	0x4008ed09 <rtc_slowck_cali+53>
@@ 第74行： / 第90行： @@
 >>>>
 x4008ecf1 <rtc_slowck_cali+29>: bnei	a2, 1, 0x4008ed09 <rtc_slowck_cali+53>
 x4008ecf4 <rtc_slowck_cali+32>: l32r	a4, 0x4008e660
 x4008ecf7 <rtc_slowck_cali+35>: movi	a8, 0x200
 x4008ecfa <rtc_slowck_cali+38>: memw
 x4008ecfd <rtc_slowck_cali+41>: l32i	a9, a4, 0
-x4008ed00 <rtc_slowck_cali+44>: or	a8, a9, a8
+x4008ed00 <rtc_slowck_cali+44>: or	a8, a9, a8  /* set bit[9] */
 x4008ed03 <rtc_slowck_cali+47>: memw
 x4008ed06 <rtc_slowck_cali+50>: s32i	a8, a4, 0
->>>>
+>>>>  /* p1 == 0 */
-x4008ed09 <rtc_slowck_cali+53>: l32r	a4, 0x4008ecc4
+x4008ed09 <rtc_slowck_cali+53>: l32r	a4, 0x4008ecc4  /* 0x6001f068 */
-x4008ed0c <rtc_slowck_cali+56>: l32r	a8, 0x4008ecc8
+x4008ed0c <rtc_slowck_cali+56>: l32r	a8, 0x4008ecc8  /* 0xffff9fff */
 x4008ed0f <rtc_slowck_cali+59>: memw
-x4008ed12 <rtc_slowck_cali+62>: l32i.n	a10, a4, 0
+x4008ed12 <rtc_slowck_cali+62>: l32i.n	a10, a4, 0    /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00013000 */
 x4008ed14 <rtc_slowck_cali+64>: extui	a9, a2, 0, 2
 x4008ed17 <rtc_slowck_cali+67>: slli	a9, a9, 13
 x4008ed1a <rtc_slowck_cali+70>: and	a8, a10, a8
-x4008ed1d <rtc_slowck_cali+73>: or	a8, a9, a8
+x4008ed1d <rtc_slowck_cali+73>: or	a8, a9, a8    /* clear and set bit[14:13] */
 x4008ed20 <rtc_slowck_cali+76>: memw
 x4008ed23 <rtc_slowck_cali+79>: s32i.n	a8, a4, 0
 x4008ed25 <rtc_slowck_cali+81>: memw
-x4008ed28 <rtc_slowck_cali+84>: l32i.n	a9, a4, 0
+x4008ed28 <rtc_slowck_cali+84>: l32i.n	a9, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00011000 */
-x4008ed2a <rtc_slowck_cali+86>: l32r	a8, 0x40087370
+x4008ed2a <rtc_slowck_cali+86>: l32r	a8, 0x40087370  /* 0xffffefff */
-x4008ed2d <rtc_slowck_cali+89>: and	a8, a9, a8
+x4008ed2d <rtc_slowck_cali+89>: and	a8, a9, a8  /* clear bit[12] */
 x4008ed30 <rtc_slowck_cali+92>: memw
 x4008ed33 <rtc_slowck_cali+95>: s32i.n	a8, a4, 0
 x4008ed35 <rtc_slowck_cali+97>: memw
-x4008ed38 <rtc_slowck_cali+100>: l32i.n	a10, a4, 0
+x4008ed38 <rtc_slowck_cali+100>: l32i.n	a10, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00010000 */
-x4008ed3a <rtc_slowck_cali+102>: l32r	a8, 0x4008eccc
+x4008ed3a <rtc_slowck_cali+102>: l32r	a8, 0x4008eccc  /* 0x8000ffff */
-x4008ed3d <rtc_slowck_cali+105>: extui	a9, a3, 0, 15
+x4008ed3d <rtc_slowck_cali+105>: extui	a9, a3, 0, 15  /* p2[15:0] */
 x4008ed40 <rtc_slowck_cali+108>: slli	a9, a9, 16
 x4008ed43 <rtc_slowck_cali+111>: and	a8, a10, a8
-x4008ed46 <rtc_slowck_cali+114>: or	a8, a9, a8
+x4008ed46 <rtc_slowck_cali+114>: or	a8, a9, a8  /* clear and set bit[30:16] */
 x4008ed49 <rtc_slowck_cali+117>: memw
 x4008ed4c <rtc_slowck_cali+120>: s32i.n	a8, a4, 0
 x4008ed4e <rtc_slowck_cali+122>: memw
-x4008ed51 <rtc_slowck_cali+125>: l32i.n	a9, a4, 0
+x4008ed51 <rtc_slowck_cali+125>: l32i.n	a9, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00010000 */
-x4008ed53 <rtc_slowck_cali+127>: l32r	a8, 0x400806f4
+x4008ed53 <rtc_slowck_cali+127>: l32r	a8, 0x400806f4  /* 0x7fffffff */
 x4008ed56 <rtc_slowck_cali+130>: movi	a10, 0x12c
-x4008ed59 <rtc_slowck_cali+133>: and	a8, a9, a8
+x4008ed59 <rtc_slowck_cali+133>: and	a8, a9, a8  /* clear bit[31] */
 x4008ed5c <rtc_slowck_cali+136>: memw
 x4008ed5f <rtc_slowck_cali+139>: s32i.n	a8, a4, 0
 x4008ed61 <rtc_slowck_cali+141>: memw
-x4008ed64 <rtc_slowck_cali+144>: l32i.n	a9, a4, 0
+x4008ed64 <rtc_slowck_cali+144>: l32i.n	a9, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00010000 */
-x4008ed66 <rtc_slowck_cali+146>: l32r	a8, 0x400806b8
+x4008ed66 <rtc_slowck_cali+146>: l32r	a8, 0x400806b8  /* 0x80000000 */
-x4008ed69 <rtc_slowck_cali+149>: or	a8, a9, a8
+x4008ed69 <rtc_slowck_cali+149>: or	a8, a9, a8  /* set bit[31] = 1 */
 x4008ed6c <rtc_slowck_cali+152>: memw
 x4008ed6f <rtc_slowck_cali+155>: s32i	a8, a4, 0
-x4008ed72 <rtc_slowck_cali+158>: l32r	a8, 0x40080848
+x4008ed72 <rtc_slowck_cali+158>: l32r	a8, 0x40080848  /* a8 = 0x40008534, ets_delay_us */
-x4008ed75 <rtc_slowck_cali+161>: callx8	a8
+x4008ed75 <rtc_slowck_cali+161>: callx8	a8  /* ets_delay_us(300) */
-x4008ed78 <rtc_slowck_cali+164>: l32r	a9, 0x400879e0
+x4008ed78 <rtc_slowck_cali+164>: l32r	a9, 0x400879e0  /* a9 = 0x00008000 */
 >>>>
 x4008ed7b <rtc_slowck_cali+167>: memw
-x4008ed7e <rtc_slowck_cali+170>: l32i.n	a8, a4, 0
+x4008ed7e <rtc_slowck_cali+170>: l32i.n	a8, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+0x68) */
 x4008ed80 <rtc_slowck_cali+172>: bnone	a8, a9, 0x4008ed7b <rtc_slowck_cali+167>
 x4008ed83 <rtc_slowck_cali+175>: bnei	a2, 2, 0x4008ed9c <rtc_slowck_cali+200>
-x4008ed86 <rtc_slowck_cali+178>: l32r	a2, 0x4008e660
+x4008ed86 <rtc_slowck_cali+178>: l32r	a2, 0x4008e660  /*
 x4008ed89 <rtc_slowck_cali+181>: movi	a4, 0xfffffeff
 x4008ed8c <rtc_slowck_cali+184>: memw
@@ 第150行： / 第171行： @@
 >>>>
 x4008ed9c <rtc_slowck_cali+200>: bnei	a2, 1, 0x4008edb4 <rtc_slowck_cali+224>
 x4008ed9f <rtc_slowck_cali+203>: l32r	a2, 0x4008e660
 x4008eda2 <rtc_slowck_cali+206>: movi	a4, 0xfffffdff
 x4008eda5 <rtc_slowck_cali+209>: memw
 x4008eda8 <rtc_slowck_cali+212>: l32i	a8, a2, 0
-x4008edab <rtc_slowck_cali+215>: and	a4, a8, a4
+x4008edab <rtc_slowck_cali+215>: and	a4, a8, a4  /* clear bit[9] */
 x4008edae <rtc_slowck_cali+218>: memw
 x4008edb1 <rtc_slowck_cali+221>: s32i	a4, a2, 0
 >>>>
-x4008edb4 <rtc_slowck_cali+224>: l32r	a2, 0x4008ecd0
+x4008edb4 <rtc_slowck_cali+224>: l32r	a2, 0x4008ecd0  /* 0x6001f06c,  (DR_REG_BB_BASE+0x6c) */
 x4008edb7 <rtc_slowck_cali+227>: memw
 x4008edba <rtc_slowck_cali+230>: l32i	a2, a2, 0

@@ 第56行： / 第56行： @@
 <br><br>
-== rtc_ ==
+== rtc_slowck_cali ==
 <source lang=bash>

←上一版本		2016年12月15日 (四) 10:49的版本
第53行：		第53行：
	uint32_t rtc_get_xtal();		uint32_t rtc_get_xtal();

		+
		+	<br><br>
		+
		+	== rtc_ ==
		+
		+	<source lang=bash>
		+	0x4008ecd4 <rtc_slowck_cali>: entry a1, 32
		+	0x4008ecd7 <rtc_slowck_cali+3>: bnei a2, 2, 0x4008ecf1 <rtc_slowck_cali+29>
		+	0x4008ecda <rtc_slowck_cali+6>: l32r a4, 0x4008e660
		+	0x4008ecdd <rtc_slowck_cali+9>: movi a8, 0x100
		+	0x4008ece0 <rtc_slowck_cali+12>: memw
		+	0x4008ece3 <rtc_slowck_cali+15>: l32i.n a9, a4, 0
		+	0x4008ece5 <rtc_slowck_cali+17>: or a8, a9, a8
		+	0x4008ece8 <rtc_slowck_cali+20>: memw
		+	0x4008eceb <rtc_slowck_cali+23>: s32i.n a8, a4, 0
		+	0x4008eced <rtc_slowck_cali+25>: j 0x4008ed09 <rtc_slowck_cali+53>
		+
		+	0x4008ecef <rtc_slowck_cali+27>: 0x0000
		+
		+	>>>>
		+	0x4008ecf1 <rtc_slowck_cali+29>: bnei a2, 1, 0x4008ed09 <rtc_slowck_cali+53>
		+	0x4008ecf4 <rtc_slowck_cali+32>: l32r a4, 0x4008e660
		+	0x4008ecf7 <rtc_slowck_cali+35>: movi a8, 0x200
		+	0x4008ecfa <rtc_slowck_cali+38>: memw
		+	0x4008ecfd <rtc_slowck_cali+41>: l32i a9, a4, 0
		+	0x4008ed00 <rtc_slowck_cali+44>: or a8, a9, a8
		+	0x4008ed03 <rtc_slowck_cali+47>: memw
		+	0x4008ed06 <rtc_slowck_cali+50>: s32i a8, a4, 0
		+
		+	>>>>
		+	0x4008ed09 <rtc_slowck_cali+53>: l32r a4, 0x4008ecc4
		+	0x4008ed0c <rtc_slowck_cali+56>: l32r a8, 0x4008ecc8
		+	0x4008ed0f <rtc_slowck_cali+59>: memw
		+	0x4008ed12 <rtc_slowck_cali+62>: l32i.n a10, a4, 0
		+	0x4008ed14 <rtc_slowck_cali+64>: extui a9, a2, 0, 2
		+	0x4008ed17 <rtc_slowck_cali+67>: slli a9, a9, 13
		+	0x4008ed1a <rtc_slowck_cali+70>: and a8, a10, a8
		+	0x4008ed1d <rtc_slowck_cali+73>: or a8, a9, a8
		+	0x4008ed20 <rtc_slowck_cali+76>: memw
		+	0x4008ed23 <rtc_slowck_cali+79>: s32i.n a8, a4, 0
		+	0x4008ed25 <rtc_slowck_cali+81>: memw
		+
		+	0x4008ed28 <rtc_slowck_cali+84>: l32i.n a9, a4, 0
		+	0x4008ed2a <rtc_slowck_cali+86>: l32r a8, 0x40087370
		+	0x4008ed2d <rtc_slowck_cali+89>: and a8, a9, a8
		+	0x4008ed30 <rtc_slowck_cali+92>: memw
		+	0x4008ed33 <rtc_slowck_cali+95>: s32i.n a8, a4, 0
		+	0x4008ed35 <rtc_slowck_cali+97>: memw
		+
		+	0x4008ed38 <rtc_slowck_cali+100>: l32i.n a10, a4, 0
		+	0x4008ed3a <rtc_slowck_cali+102>: l32r a8, 0x4008eccc
		+	0x4008ed3d <rtc_slowck_cali+105>: extui a9, a3, 0, 15
		+	0x4008ed40 <rtc_slowck_cali+108>: slli a9, a9, 16
		+	0x4008ed43 <rtc_slowck_cali+111>: and a8, a10, a8
		+	0x4008ed46 <rtc_slowck_cali+114>: or a8, a9, a8
		+	0x4008ed49 <rtc_slowck_cali+117>: memw
		+	0x4008ed4c <rtc_slowck_cali+120>: s32i.n a8, a4, 0
		+	0x4008ed4e <rtc_slowck_cali+122>: memw
		+
		+	0x4008ed51 <rtc_slowck_cali+125>: l32i.n a9, a4, 0
		+	0x4008ed53 <rtc_slowck_cali+127>: l32r a8, 0x400806f4
		+	0x4008ed56 <rtc_slowck_cali+130>: movi a10, 0x12c
		+	0x4008ed59 <rtc_slowck_cali+133>: and a8, a9, a8
		+	0x4008ed5c <rtc_slowck_cali+136>: memw
		+	0x4008ed5f <rtc_slowck_cali+139>: s32i.n a8, a4, 0
		+	0x4008ed61 <rtc_slowck_cali+141>: memw
		+
		+	0x4008ed64 <rtc_slowck_cali+144>: l32i.n a9, a4, 0
		+	0x4008ed66 <rtc_slowck_cali+146>: l32r a8, 0x400806b8
		+	0x4008ed69 <rtc_slowck_cali+149>: or a8, a9, a8
		+	0x4008ed6c <rtc_slowck_cali+152>: memw
		+	0x4008ed6f <rtc_slowck_cali+155>: s32i a8, a4, 0
		+
		+	0x4008ed72 <rtc_slowck_cali+158>: l32r a8, 0x40080848
		+	0x4008ed75 <rtc_slowck_cali+161>: callx8 a8
		+
		+	0x4008ed78 <rtc_slowck_cali+164>: l32r a9, 0x400879e0
		+
		+	>>>>
		+	0x4008ed7b <rtc_slowck_cali+167>: memw
		+	0x4008ed7e <rtc_slowck_cali+170>: l32i.n a8, a4, 0
		+
		+	0x4008ed80 <rtc_slowck_cali+172>: bnone a8, a9, 0x4008ed7b <rtc_slowck_cali+167>
		+	0x4008ed83 <rtc_slowck_cali+175>: bnei a2, 2, 0x4008ed9c <rtc_slowck_cali+200>
		+
		+	0x4008ed86 <rtc_slowck_cali+178>: l32r a2, 0x4008e660
		+	0x4008ed89 <rtc_slowck_cali+181>: movi a4, 0xfffffeff
		+	0x4008ed8c <rtc_slowck_cali+184>: memw
		+	0x4008ed8f <rtc_slowck_cali+187>: l32i.n a8, a2, 0
		+	0x4008ed91 <rtc_slowck_cali+189>: and a4, a8, a4
		+	0x4008ed94 <rtc_slowck_cali+192>: memw
		+	0x4008ed97 <rtc_slowck_cali+195>: s32i.n a4, a2, 0
		+
		+	0x4008ed99 <rtc_slowck_cali+197>: j 0x4008edb4 <rtc_slowck_cali+224>
		+
		+	>>>>
		+	0x4008ed9c <rtc_slowck_cali+200>: bnei a2, 1, 0x4008edb4 <rtc_slowck_cali+224>
		+	0x4008ed9f <rtc_slowck_cali+203>: l32r a2, 0x4008e660
		+	0x4008eda2 <rtc_slowck_cali+206>: movi a4, 0xfffffdff
		+	0x4008eda5 <rtc_slowck_cali+209>: memw
		+	0x4008eda8 <rtc_slowck_cali+212>: l32i a8, a2, 0
		+	0x4008edab <rtc_slowck_cali+215>: and a4, a8, a4
		+	0x4008edae <rtc_slowck_cali+218>: memw
		+	0x4008edb1 <rtc_slowck_cali+221>: s32i a4, a2, 0
		+
		+	>>>>
		+	0x4008edb4 <rtc_slowck_cali+224>: l32r a2, 0x4008ecd0
		+	0x4008edb7 <rtc_slowck_cali+227>: memw
		+	0x4008edba <rtc_slowck_cali+230>: l32i a2, a2, 0
		+	0x4008edbd <rtc_slowck_cali+233>: call8 0x4008fb14 <rtc_get_xtal>
		+
		+	0x4008edc0 <rtc_slowck_cali+236>: mull a12, a10, a3
		+	0x4008edc3 <rtc_slowck_cali+239>: srli a10, a2, 7
		+	0x4008edc6 <rtc_slowck_cali+242>: extui a11, a2, 20, 12
		+	0x4008edc9 <rtc_slowck_cali+245>: movi a13, 0
		+	0x4008edcc <rtc_slowck_cali+248>: slli a10, a10, 19
		+	0x4008edcf <rtc_slowck_cali+251>: call8 0x400e7440 <__udivdi3>
		+	0x4008edd2 <rtc_slowck_cali+254>: mov.n a2, a10
		+	0x4008edd4 <rtc_slowck_cali+256>: retw.n
		+	</source>

	<br><br>		<br><br>

@@ 第855行： / 第855行： @@
 	REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, p2 << 27, RTC_CNTL_SOC_CLK_SEL_M);
-	if (p1 == 1) {
+	if (p2 == 1) {
 		// PLL clock
 		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 24, RTC_CNTL_PLL_BUF_WAIT_M);	// PLL wait cycles in slow_clk_rtc
 		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M);	// XTAL wait cycles in slow_clk_rtc
 		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);	// CK8M wait cycles in slow_clk_rtc
-	} else if (p1 == 0) {
+	} else if (p2 == 0) {
 		// XTAL clock
 		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M);	// PLL wait cycles in slow_clk_rtc
@@ 第867行： / 第867行： @@
 		ets_update_cpu_frequency(ticks_per_us);
 		rtc_apb_freq_up(ticks_per_us * 1000000);
-	} else if (p1 == 2) {
+	} else if (p2 == 2) {
 		// CK8M clock
 		REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 25,

@@ 第339行： / 第339行： @@
      REG_SET_BITS(RTC_CNTL_REG, p1 << 11, RTC_CNTL_DIG_DBIAS_WAK_M);  // DIG_REG_DBIAS during wakeup
      REG_SET_BITS(RTC_CNTL_REG, p2 << 8, RTC_CNTL_DIG_DBIAS_SLP_M);   // DIG_REG_DBIAS during sleep
+}
 </source>