ESP32 core isa - 版本历史

Comcat：/* CACHE */

2016-11-21T16:29:26Z

‎CACHE

Comcat：/* Interrupts */

2016-11-21T16:29:04Z

‎Interrupts

显示差异

Comcat：/* Debug */

2016-11-21T16:27:48Z

‎Debug

Comcat：/* MISC */

2016-11-21T16:26:11Z

‎MISC

Comcat：/* MMU */

2016-11-21T16:25:14Z

‎MMU

Comcat：/* MMU */

2016-11-21T16:23:05Z

‎MMU

Comcat：/* CACHE */

2016-11-21T16:21:20Z

‎CACHE

Comcat：/* Exceptions */

2016-11-21T16:20:32Z

‎Exceptions

Comcat：/* CACHE */

2016-11-21T16:20:14Z

‎CACHE

Comcat：/* ISA */

2016-11-21T16:17:22Z

‎ISA

@@ 第381行： / 第381行： @@
 <br><br>
-== CACHE ==
+== Cache ==
 <pre>

@@ 第295行： / 第295行： @@
 /*  Perf counters  */
 #define XCHAL_NUM_PERF_COUNTERS     2   /* performance counters */
 </pre>

@@ 第305行： / 第305行： @@
 #define XCHAL_NUM_WRITEBUFFER_ENTRIES   4   /* size of write buffer */
 #define XCHAL_INST_FETCH_WIDTH      4   /* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH        4   /* data width in bytes */
+#define XCHAL_DATA_WIDTH            4   /* data width in bytes */
 #define XCHAL_DATA_PIPE_DELAY       2   /* d-side pipeline delay
-                           (1 = 5-stage, 2 = 7-stage) */
+                                        (1 = 5-stage, 2 = 7-stage) */
 #define XCHAL_CLOCK_GATING_GLOBAL   1   /* global clock gating */
 #define XCHAL_CLOCK_GATING_FUNCUNIT 1   /* funct. unit clock gating */

@@ 第270行： / 第270行： @@
 <br><br>
 <br><br>
 <br><br>

@@ 第252行： / 第252行： @@
 /*  See core-matmap.h header file for more details.  */
-#define XCHAL_HAVE_TLBS         1   /* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_TLBS             1   /* inverse of HAVE_CACHEATTR */
 #define XCHAL_HAVE_SPANNING_WAY     1   /* one way maps I+D 4GB vaddr */
-#define XCHAL_SPANNING_WAY      0   /* TLB spanning way number */
+#define XCHAL_SPANNING_WAY          0   /* TLB spanning way number */
 #define XCHAL_HAVE_IDENTITY_MAP     1   /* vaddr == paddr always */
 #define XCHAL_HAVE_CACHEATTR        0   /* CACHEATTR register present */
 #define XCHAL_HAVE_MIMIC_CACHEATTR  1   /* region protection */
 #define XCHAL_HAVE_XLT_CACHEATTR    0   /* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU      0   /* full MMU (with page table
+#define XCHAL_HAVE_PTP_MMU          0   /* full MMU (with page table
-                           [autorefill] and protection)
+                                           [autorefill] and protection)
-                           usable for an MMU-based OS */
+                                           usable for an MMU-based OS */
 /*  If none of the above last 4 are set, it's a custom TLB configuration.  */

←上一版本		2016年11月21日 (一) 16:20的版本
第115行：		第115行：

	== Exceptions ==		== Exceptions ==
		+
		+	<pre>
		+	#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
		+	number: 1 == XEA1 (old)
		+	2 == XEA2 (new)
		+	0 == XEAX (extern) or TX */
		+	#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
		+	#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
		+	#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
		+	#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
		+	#define XCHAL_HAVE_HALT 0 /* halt architecture option */
		+	#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
		+	#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
		+	#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
		+	#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
		+	#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
		+	#define XCHAL_VECBASE_RESET_PADDR 0x40000000
		+	#define XCHAL_RESET_VECBASE_OVERLAP 0
		+
		+	#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
		+	#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
		+	#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
		+	#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
		+	#define XCHAL_RESET_VECTOR_VADDR 0x40000400
		+	#define XCHAL_RESET_VECTOR_PADDR 0x40000400
		+	#define XCHAL_USER_VECOFS 0x00000340
		+	#define XCHAL_USER_VECTOR_VADDR 0x40000340
		+	#define XCHAL_USER_VECTOR_PADDR 0x40000340
		+	#define XCHAL_KERNEL_VECOFS 0x00000300
		+	#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300
		+	#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300
		+	#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
		+	#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0
		+	#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0
		+	#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
		+	#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
		+	#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
		+	#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
		+	#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
		+	#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
		+	#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
		+	#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
		+	#define XCHAL_INTLEVEL2_VECOFS 0x00000180
		+	#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180
		+	#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180
		+	#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
		+	#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0
		+	#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0
		+	#define XCHAL_INTLEVEL4_VECOFS 0x00000200
		+	#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200
		+	#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200
		+	#define XCHAL_INTLEVEL5_VECOFS 0x00000240
		+	#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240
		+	#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240
		+	#define XCHAL_INTLEVEL6_VECOFS 0x00000280
		+	#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280
		+	#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280
		+	#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
		+	#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
		+	#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
		+	#define XCHAL_NMI_VECOFS 0x000002C0
		+	#define XCHAL_NMI_VECTOR_VADDR 0x400002C0
		+	#define XCHAL_NMI_VECTOR_PADDR 0x400002C0
		+	#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
		+	#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
		+	#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
		+	</pre>

	<br><br>		<br><br>

@@ 第146行： / 第146行： @@
 #define XCHAL_HAVE_ICACHE_DYN_WAYS  0   /* Icache dynamic way support */
 #define XCHAL_HAVE_DCACHE_DYN_WAYS  0   /* Dcache dynamic way support */
 </pre>

←上一版本		2016年11月21日 (一) 16:17的版本
第111行：		第111行：
	#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */		#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
	</pre>		</pre>
		+
		+	<br><br>
		+
		+	== Exceptions ==
		+
		+	<br><br>
		+
		+	== Interrupts ==
		+
		+	<br><br>
		+
		+	== CACHE ==
		+
		+	<pre>
		+	#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
		+	#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
		+	#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
		+	#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */
		+
		+	#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
		+	#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
		+
		+	#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
		+	#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
		+
		+	#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
		+	#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
		+	#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
		+	#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
		+	#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
		+	#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
		+	#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
		+	#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
		+	#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
		+	#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
		+	</pre>
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