IA32 SSE3 精要 - 版本历史

Comcat：/* 指令列表 */

2014-11-11T04:34:49Z

‎指令列表

Comcat：/* 指令列表 */

2014-11-11T04:34:33Z

‎指令列表

Comcat：以“== 简介 == SSE3 系 Intel Streaming SIMD Extensions 的第3次扩展，相较于 SSE2，Intel 新加入了 13 条指令。其最早于 2004 年在 Pentium 4 Presc...”为内容创建页面

2014-11-11T04:33:10Z

以“== 简介 == SSE3 系 Intel Streaming SIMD Extensions 的第3次扩展，相较于 SSE2，Intel 新加入了 13 条指令。其最早于 2004 年在 Pentium 4 Presc...”为内容创建页面

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== 简介 ==

SSE3 系 Intel Streaming SIMD Extensions 的第3次扩展，相较于 SSE2，Intel 新加入了 13 条指令。其最早于 2004 年在 Pentium 4 Prescott 中引入，后续 IA32 的 CPU 都支持之

 

== 支持 SSE3 的 CPU ==

* AMD:
o Athlon 64 (since Venice Stepping E3 and San Diego Stepping E4)
o Athlon 64 X2
o Athlon 64 FX (since San Diego Stepping E4)
o Opteron (since Stepping E4)
o Sempron (since Palermo Stepping E3)
o Turion 64
o Turion 64 X2

* Intel:
o Celeron D
o Pentium 4 (since Prescott)
o Pentium D
o Intel Core Duo
o Intel Core 2 Duo
o Intel Core 2 Extreme
o Xeon (since Nocona)

* VIA/Centaur:
o C7

* Transmeta
o Efficeon TM88xx (NOT Model Numbers TM86xx)

 

== 指令列表 ==

<source lang=bash>
Arithmetic

* ADDSUBPD - ( Add-Subtract-Packed-Double )
o Input - { A0, A1 }, { B0, B1 }
o Output - { A0 - B0, A1 + B1 }

* ADDSUBPS - ( Add-Subtract-Packed-Single )
o Input: { A0, A1, A2, A3 }, { B0, B1, B2, B3 }
o Output: { A0 - B0, A1 + B1, A2 - B2, A3 + B3 }

AOS ( Array Of Structures )

* HADDPD - ( Horizontal-Add-Packed-Double )
o Input: { A0, A1 }, { B0, B1 }
o Output: { A0 + A1, B0 + B1 }

* HADDPS ( Horizontal-Add-Packed-Single )
o Input: { A0, A1, A2, A3 }, { B0, B1, B2, B3 }
o Output: { A0 + A1, A2 + A3, B0 + B1, B2 + B3 }

* HSUBPD - ( Horizontal-Subtract-Packed-Double )
o Input: { A0, A1 }, { B0, B1 }
o Output: { A0 - A1, B0 - B1 }

* HSUBPS - ( Horizontal-Subtract-Packed-Single )
o Input: { A0, A1, A2, A3 }, { B0, B1, B2, B3 }
o Output: { A0 - A1, A2 - A3, B0 - B1, B2 - B3 }

* LDDQU - This is an alternative misaligned integer vector load that has better performance on NetBurst architectures for loads that cross cacheline boundaries. It can be helpful for video compression tasks.

* MOVDDUP, MOVSHDUP, MOVSLDUP - These are also used for complex numbers, and can be helpful for wave calculation like sound.

* FISTTP - Like the older x87 FISTP instruction, but ignores the floating point control register's rounding mode settings and uses the "chop" (truncate) mode instead. Allows omission of the expensive loading and re-loading of the control register in languages such as C where float-to-int conversion requires truncate behaviour by standard.

Intel Instructions

* MONITOR, MWAIT - These optimize multi-threaded applications, giving processors with Hyper-Threading better performance.
</source>

@@ 第71行： / 第71行： @@
                architectures for loads that cross cacheline boundaries. It can be helpful for video compression tasks.
-     * MOVDDUP, MOVSHDUP, MOVSLDUP - These are also used for complex numbers, and can be helpful for wave calculation like sound.
+     * MOVDDUP, MOVSHDUP, MOVSLDUP - These are also used for complex numbers, and can be helpful for wave calculation like
      * FISTTP - Like the older x87 FISTP instruction, but ignores the floating point control register's rounding mode

@@ 第68行： / 第68行： @@
         o Output: { A0 - A1, A2 - A3, B0 - B1, B2 - B3 }
-     * LDDQU - This is an alternative misaligned integer vector load that has better performance on NetBurst architectures for loads that cross cacheline boundaries. It can be helpful for video compression tasks.
+     * LDDQU - This is an alternative misaligned integer vector load that has better performance on NetBurst
      * MOVDDUP, MOVSHDUP, MOVSLDUP - These are also used for complex numbers, and can be helpful for wave calculation like sound.
-     * FISTTP - Like the older x87 FISTP instruction, but ignores the floating point control register's rounding mode settings and uses the "chop" (truncate) mode instead. Allows omission of the expensive loading and re-loading of the control register in languages such as C where float-to-int conversion requires truncate behaviour by standard.
+     * FISTTP - Like the older x87 FISTP instruction, but ignores the floating point control register's rounding mode