ADC
来自Jack's Lab
（版本间的差异）
(以“== MCP3421 == <br><br> == CS53L30 == ;;System Features * Native (no PLL required) support for 6-/12-MHz, 6.144-/12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz mast...”为内容创建页面) |
(→CS53L30) |
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| 第7行： | 第7行： | ||
;;System Features | ;;System Features | ||
| − | * Native (no PLL required) support for 6-/12-MHz, 6.144-/12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master | + | * Native (no PLL required) support for 6-/12-MHz, 6.144-/12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master clock rates and 8- to 48-kHz audio sample rates |
| − | clock rates and 8- to 48-kHz audio sample rates | + | * Master or Slave Mode. Clock dividers can be used to generate common audio clocks from single-master clock input. |
| − | * Master or Slave Mode. Clock dividers can be used to | + | |
| − | generate common audio clocks from single-master clock | + | |
| − | input. | + | |
* Low power consumption | * Low power consumption | ||
* Less than 4.5-mW stereo (16 kHz) analog mic record | * Less than 4.5-mW stereo (16 kHz) analog mic record | ||
2016年9月29日 (四) 10:30的版本
1 MCP3421
2 CS53L30
- System Features
- Native (no PLL required) support for 6-/12-MHz, 6.144-/12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master clock rates and 8- to 48-kHz audio sample rates
- Master or Slave Mode. Clock dividers can be used to generate common audio clocks from single-master clock input.
- Low power consumption
- Less than 4.5-mW stereo (16 kHz) analog mic record
- Less than 2.5-mW mono (8 kHz) analog mic record
- Selectable mic bias and digital interface logic voltages
- High-speed (400-kHz) I²C control port
https://www.cirrus.com/en/pubs/proDatasheet/CS53L30_F2.pdf
