ESP32 RTC
(→rtc_pads_muxsel) |
(→RTC GPIO) |
||
(未显示1个用户的100个中间版本) | |||
第1行: | 第1行: | ||
− | == | + | == RTC GPIO == |
− | + | RTC_GPIO0 ~ RTC_GPIO17 | |
− | + | [[文件:Esp32-pin-adc.jpg | 960px]] | |
− | + | {| border="0" width=89% cellspacing="1" cellpadding="5" align="center" bgcolor=#0066bb | |
+ | | style="background:#eeeeee" width=50| Pin NO. | ||
+ | | style="background:#eeeeee" | Pin Name | ||
+ | | style="background:#eeeeee" | RTC_GPIO | ||
+ | | style="background:#eeeeee" | Control Register | ||
+ | | style="background:#eeeeee" | MUX Bits | ||
+ | | style="background:#eeeeee" | After Reset | ||
+ | | style="background:#eeeeee" | Notes | ||
+ | |- | ||
+ | | style="background:#ffffff" | 5 | ||
+ | | style="background:#ffffff" | SENSOR_VP | ||
+ | | style="background:#ffffff" | RTC_GPIO0 | ||
+ | | style="background:#ffffff" | RTC_IO_SENSOR_PADS_REG | ||
+ | | style="background:#ffffff" | SENSE1_MUX_SEL, BIT[27] | ||
+ | | style="background:#ffffff" | 0 (Route to digital IO_MUX) | ||
+ | | style="background:#ffffff" | Only Input | ||
+ | |- | ||
+ | | style="background:#ffffff" | 6 | ||
+ | | style="background:#ffffff" | SENSOR_CAPP | ||
+ | | style="background:#ffffff" | RTC_GPIO1 | ||
+ | | style="background:#ffffff" | RTC_IO_SENSOR_PADS_REG | ||
+ | | style="background:#ffffff" | SENSE1_MUX_SEL, BIT[26] | ||
+ | | style="background:#ffffff" | 0 | ||
+ | | style="background:#ffffff" | Only Input | ||
+ | |- | ||
+ | | style="background:#ffffff" | 7 | ||
+ | | style="background:#ffffff" | SENSOR_CAPN | ||
+ | | style="background:#ffffff" | RTC_GPIO2 | ||
+ | | style="background:#ffffff" | RTC_IO_SENSOR_PADS_REG | ||
+ | | style="background:#ffffff" | SENSE3_MUX_SEL, BIT[25] | ||
+ | | style="background:#ffffff" | 0 | ||
+ | | style="background:#ffffff" | Only Input | ||
+ | |- | ||
+ | | style="background:#ffffff" | 8 | ||
+ | | style="background:#ffffff" | SENSOR_VN | ||
+ | | style="background:#ffffff" | RTC_GPIO3 | ||
+ | | style="background:#ffffff" | RTC_IO_SENSOR_PADS_REG | ||
+ | | style="background:#ffffff" | SENSE4_MUX_SEL, BIT[24] | ||
+ | | style="background:#ffffff" | 0 | ||
+ | | style="background:#ffffff" | Only Input | ||
+ | |- | ||
+ | | style="background:#ffffff" | 10 | ||
+ | | style="background:#ffffff" | VDET_1 | ||
+ | | style="background:#ffffff" | RTC_GPIO4 | ||
+ | | style="background:#ffffff" | RTC_IO_ADC_PAD_REG | ||
+ | | style="background:#ffffff" | ADC1_MUX_SEL, BIT[29] | ||
+ | | style="background:#ffffff" | 0 | ||
+ | | style="background:#ffffff" | Only Input | ||
+ | |- | ||
+ | | style="background:#ffffff" | 11 | ||
+ | | style="background:#ffffff" | VDET_2 | ||
+ | | style="background:#ffffff" | RTC_GPIO5 | ||
+ | | style="background:#ffffff" | RTC_IO_ADC_PAD_REG | ||
+ | | style="background:#ffffff" | ADC2_MUX_SEL, BIT[28] | ||
+ | | style="background:#ffffff" | 0 | ||
+ | | style="background:#ffffff" | Only Input | ||
+ | |- | ||
+ | | style="background:#ffffff" | 12 | ||
+ | | style="background:#ffffff" | 32K_XP | ||
+ | | style="background:#ffffff" | RTC_GPIO9 | ||
+ | | style="background:#ffffff" | RTC_IO_XTAL_32K_PAD_REG | ||
+ | | style="background:#ffffff" | X32P_MUX_SEL, BIT[17] | ||
+ | | style="background:#ffffff" | 0 (Route to digital IO_MUX) | ||
+ | | style="background:#ffffff" | Set to 1 by esp-idf, route to RTC | ||
+ | |- | ||
+ | | style="background:#ffffff" | 13 | ||
+ | | style="background:#ffffff" | 32K_XN | ||
+ | | style="background:#ffffff" | RTC_GPIO8 | ||
+ | | style="background:#ffffff" | RTC_IO_XTAL_32K_PAD_REG | ||
+ | | style="background:#ffffff" | X32N_MUX_SEL, BIT[18] | ||
+ | | style="background:#ffffff" | 0 (Route to digital IO_MUX) | ||
+ | | style="background:#ffffff" | Set to 1 by esp-idf, route to RTC | ||
+ | |- | ||
+ | | style="background:#ffffff" | 14 | ||
+ | | style="background:#ffffff" | DAC_1 | ||
+ | | style="background:#ffffff" | RTC_GPIO6 | ||
+ | | style="background:#ffffff" | RTC_IO_PAD_DAC1_REG | ||
+ | | style="background:#ffffff" | PDAC1_MUX_SEL, BIT[17] | ||
+ | | style="background:#ffffff" | 0 | ||
+ | | style="background:#ffffff" | | ||
+ | |- | ||
+ | | style="background:#ffffff" | 15 | ||
+ | | style="background:#ffffff" | DAC_2 | ||
+ | | style="background:#ffffff" | RTC_GPIO7 | ||
+ | | style="background:#ffffff" | RTC_IO_PAD_DAC2_REG | ||
+ | | style="background:#ffffff" | PDAC2_MUX_SEL, BIT[17] | ||
+ | | style="background:#ffffff" | 0 | ||
+ | | style="background:#ffffff" | | ||
+ | |- | ||
+ | | style="background:#ffffff" | 16 ~ 24 | ||
+ | | style="background:#ffffff" | TOUCH7 ~ TOUCH0 | ||
+ | | style="background:#ffffff" | RTC_GPIO17 ~ 10 | ||
+ | | style="background:#ffffff" | TOUCH_PADn_REG (n = 7 ~ 0) | ||
+ | | style="background:#ffffff" | PADn_TO_GPIO, BIT[19] | ||
+ | | style="background:#ffffff" | 0 (Route to RTC domain) | ||
+ | | style="background:#ffffff" | | ||
+ | |- | ||
+ | | style="background:#ffffff" | | ||
+ | | style="background:#ffffff" | | ||
+ | | style="background:#ffffff" | | ||
+ | | style="background:#ffffff" | | ||
+ | | style="background:#ffffff" | | ||
+ | | style="background:#ffffff" | | ||
+ | | style="background:#ffffff" | | ||
+ | |} | ||
− | |||
− | + | You need to clear the following bits if you want to use the GPIO32 and GPIO33 as the general GPIO: | |
− | + | <pre> | |
+ | REG_CLR_BIT(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_MUX_SEL); /* gpio32 route to digital io_mux */ | ||
+ | REG_CLR_BIT(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL); /* gpio33 route to digital io_mux */ | ||
+ | </pre> | ||
<br><br> | <br><br> | ||
第176行: | 第282行: | ||
#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c) | #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c) | ||
</source> | </source> | ||
+ | |||
+ | <br><br> | ||
+ | |||
+ | == Memory == | ||
+ | |||
+ | === FAST Memory === | ||
+ | |||
+ | RTC FAST Memory 为 8 KB SRAM,其只能被 PRO_CPU 通过数据总线 0x3FF8_0000 ~ 0x3FF8_1FFF 读写,或被 PRO_CPU 通过指令总线 0x400C_0000~0x400C_1FFF 读写。与其他存储器不同,APP_CPU 不能访问 RTC FAST Memory | ||
+ | |||
+ | |||
+ | PRO_CPU 的这两段地址同序访问 RTC FAST Memory。即地址 0x3FF8_0000 与 0x400C_0000 访问到相同的 word,0x3FF8_0004与0x400C_0004访问到相同的word,0x3FF8_0008与0x400C_0008访问到相同的word, 以此类推。APP_CPU 的这两段地址不能访问到 RTC FAST Memory,也不能访问到其他任何目标 | ||
+ | |||
+ | <br><br> | ||
+ | |||
+ | === SLOW Memory === | ||
+ | |||
+ | RTC SLOW Memory 为 8 KB SRAM,其可以被两个 CPU 通过数据总线与指令总线共用地址段 0x5000_0000 ~ 0x5000_1FFF 读写。 | ||
<br><br> | <br><br> | ||
== Power Consumption == | == Power Consumption == | ||
+ | |||
+ | '''Light Sleep Mode:''' | ||
+ | |||
+ | * The CPU is paused | ||
+ | * WiFi/BT base-band and radio are Off | ||
+ | * The RTC and ULP are running | ||
+ | * Any wake-up events (MAC, host, RTC timer, or external interrupts) will wake up the chip | ||
+ | * Current consumption is 800uA | ||
+ | |||
'''We are care of Deep-Sleep mode:''' | '''We are care of Deep-Sleep mode:''' | ||
第196行: | 第328行: | ||
* Power Consumption: 2.5uA | * Power Consumption: 2.5uA | ||
+ | |||
+ | <br> | ||
+ | |||
+ | === Registers === | ||
+ | |||
+ | <source lang=c> | ||
+ | #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) | ||
+ | /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ | ||
+ | /*description: RTC_REG force power up*/ | ||
+ | #define RTC_CNTL_FORCE_PU_S 31 | ||
+ | /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ | ||
+ | /*description: RTC_REG force power down (for RTC_REG power down means decrease | ||
+ | the voltage to 0.8v or lower )*/ | ||
+ | #define RTC_CNTL_FORCE_PD_S 30 | ||
+ | /* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ | ||
+ | /*description: RTC_DBOOST force power up*/ | ||
+ | #define RTC_CNTL_DBOOST_FORCE_PU_S 29 | ||
+ | /* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ | ||
+ | /*description: RTC_DBOOST force power down*/ | ||
+ | #define RTC_CNTL_DBOOST_FORCE_PD_S 28 | ||
+ | /* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ | ||
+ | /*description: RTC_DBIAS during wakeup*/ | ||
+ | #define RTC_CNTL_DBIAS_WAK_S 25 | ||
+ | /* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ | ||
+ | /*description: RTC_DBIAS during sleep*/ | ||
+ | #define RTC_CNTL_DBIAS_SLP_S 22 | ||
+ | /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ | ||
+ | /*description: SCK_DCAP*/ | ||
+ | #define RTC_CNTL_SCK_DCAP_S 14 | ||
+ | /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ | ||
+ | /*description: DIG_REG_DBIAS during wakeup*/ | ||
+ | #define RTC_CNTL_DIG_DBIAS_WAK_S 11 | ||
+ | /* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */ | ||
+ | /*description: DIG_REG_DBIAS during sleep*/ | ||
+ | #define RTC_CNTL_DIG_DBIAS_SLP_S 8 | ||
+ | /* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */ | ||
+ | /*description: N/A*/ | ||
+ | #define RTC_CNTL_SCK_DCAP_FORCE_S 7 | ||
+ | |||
+ | |||
+ | #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) | ||
+ | /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ | ||
+ | /*description: enable power down rtc_peri in sleep*/ | ||
+ | #define RTC_CNTL_PD_EN_S 20 | ||
+ | /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ | ||
+ | /*description: rtc_peri force power up*/ | ||
+ | #define RTC_CNTL_PWC_FORCE_PU_S 19 | ||
+ | /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ | ||
+ | /*description: rtc_peri force power down*/ | ||
+ | #define RTC_CNTL_PWC_FORCE_PD_S 18 | ||
+ | /* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ | ||
+ | /*description: enable power down RTC memory in sleep*/ | ||
+ | #define RTC_CNTL_SLOWMEM_PD_EN_S 17 | ||
+ | /* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ | ||
+ | /*description: RTC memory force power up*/ | ||
+ | #define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 | ||
+ | /* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ | ||
+ | /*description: RTC memory force power down*/ | ||
+ | #define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 | ||
+ | /* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ | ||
+ | /*description: enable power down fast RTC memory in sleep*/ | ||
+ | #define RTC_CNTL_FASTMEM_PD_EN_S 14 | ||
+ | /* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ | ||
+ | /*description: Fast RTC memory force power up*/ | ||
+ | #define RTC_CNTL_FASTMEM_FORCE_PU_S 13 | ||
+ | /* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ | ||
+ | /*description: Fast RTC memory force power down*/ | ||
+ | #define RTC_CNTL_FASTMEM_FORCE_PD_S 12 | ||
+ | /* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ | ||
+ | /*description: RTC memory force no PD*/ | ||
+ | #define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 | ||
+ | /* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ | ||
+ | /*description: RTC memory force PD*/ | ||
+ | #define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 | ||
+ | /* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ | ||
+ | /*description: 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ | ||
+ | #define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 | ||
+ | /* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ | ||
+ | /*description: Fast RTC memory force no PD*/ | ||
+ | #define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 | ||
+ | /* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ | ||
+ | /*description: Fast RTC memory force PD*/ | ||
+ | #define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 | ||
+ | /* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ | ||
+ | /*description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following | ||
+ | RTC state machine*/ | ||
+ | #define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 | ||
+ | /* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ | ||
+ | /*description: rtc_peri force no ISO*/ | ||
+ | #define RTC_CNTL_FORCE_NOISO_S 5 | ||
+ | /* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ | ||
+ | /*description: rtc_peri force ISO*/ | ||
+ | #define RTC_CNTL_FORCE_ISO_S 4 | ||
+ | /* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ | ||
+ | /*description: RTC memory force ISO*/ | ||
+ | #define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 | ||
+ | /* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ | ||
+ | /*description: RTC memory force no ISO*/ | ||
+ | #define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 | ||
+ | /* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ | ||
+ | /*description: Fast RTC memory force ISO*/ | ||
+ | #define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 | ||
+ | /* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ | ||
+ | /*description: Fast RTC memory force no ISO*/ | ||
+ | #define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 | ||
+ | </source> | ||
<br><br> | <br><br> | ||
第209行: | 第447行: | ||
* Internal 31.25KHz clock (derived from the internal 8MHz oscillator divided by 256) | * Internal 31.25KHz clock (derived from the internal 8MHz oscillator divided by 256) | ||
+ | <br> | ||
+ | |||
+ | === API === | ||
+ | |||
+ | ==== rtc_set_fast_freq ==== | ||
+ | |||
+ | <source lang=bash> | ||
+ | 0x4008f87c <rtc_set_fast_freq>: entry a1, 32 | ||
+ | 0x4008f87f <rtc_set_fast_freq+3>: l32r a8, 0x4008e53c /* a8 = *(0x4008e53c) = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */ | ||
+ | 0x4008f882 <rtc_set_fast_freq+6>: l32r a11, 0x40086318 /* a11 = *(0x40086318) = 0xdfffffff, BIT(29), fast_clk_rtc sel */ | ||
+ | 0x4008f885 <rtc_set_fast_freq+9>: memw | ||
+ | 0x4008f888 <rtc_set_fast_freq+12>: l32i.n a9, a8, 0 /* a9 = read RTC_CNTL_CLK_CONF_REG */ | ||
+ | 0x4008f88a <rtc_set_fast_freq+14>: extui a2, a2, 0, 1 /* a2 = p1[0] */ | ||
+ | 0x4008f88d <rtc_set_fast_freq+17>: slli a10, a2, 29 /* a10 = p1[0] << 29 */ | ||
+ | 0x4008f890 <rtc_set_fast_freq+20>: and a9, a9, a11 | ||
+ | 0x4008f893 <rtc_set_fast_freq+23>: or a9, a10, a9 /* a9 = RTC_CNTL_CLK_CONF_REG & 0xdfffffff | (p1[0] << 29) | ||
+ | 0x4008f896 <rtc_set_fast_freq+26>: memw | ||
+ | 0x4008f899 <rtc_set_fast_freq+29>: s32i.n a9, a8, 0 /* write to RTC_CNTL_CLK_CONF_REG */ | ||
+ | /* fast_clk_rtc sel. 0: XTAL div 4 1: CK8M */ | ||
+ | |||
+ | 0x4008f89b <rtc_set_fast_freq+31>: movi a10, 3 | ||
+ | 0x4008f89e <rtc_set_fast_freq+34>: l32r a8, 0x40080850 /* a8 = *(0x40080850) = 0x40008534, ets_delay_us */ | ||
+ | 0x4008f8a1 <rtc_set_fast_freq+37>: callx8 a8 /* ets_delay_us(3) */ | ||
+ | 0x4008f8a4 <rtc_set_fast_freq+40>: retw.n | ||
+ | </source> | ||
+ | |||
+ | So: | ||
+ | |||
+ | <source lang=c> | ||
+ | /* | ||
+ | * fast_clk_rtc_sel = 0: XTAL div 4 | ||
+ | * fast_clk_rtc_sel = 1: CK8M | ||
+ | */ | ||
+ | void rtc_set_fast_freq(uint8_t fast_clk_rtc_sel); | ||
+ | </source> | ||
+ | |||
+ | <br> | ||
+ | |||
+ | ==== rtc_set_slow_freq ==== | ||
+ | |||
+ | <source lang=bash> | ||
+ | 0x4008f854 <rtc_set_slow_freq>: entry a1, 32 | ||
+ | 0x4008f857 <rtc_set_slow_freq+3>: l32r a8, 0x4008e53c /* a8 = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */ | ||
+ | 0x4008f85a <rtc_set_slow_freq+6>: l32r a10, 0x4008af18 /* a10 = 0x3fffffff, BIT[31:30] */ | ||
+ | 0x4008f85d <rtc_set_slow_freq+9>: memw | ||
+ | 0x4008f860 <rtc_set_slow_freq+12>: l32i.n a9, a8, 0 | ||
+ | 0x4008f862 <rtc_set_slow_freq+14>: slli a2, a2, 30 | ||
+ | 0x4008f865 <rtc_set_slow_freq+17>: and a9, a9, a10 | ||
+ | 0x4008f868 <rtc_set_slow_freq+20>: or a9, a2, a9 | ||
+ | 0x4008f86b <rtc_set_slow_freq+23>: memw | ||
+ | 0x4008f86e <rtc_set_slow_freq+26>: s32i.n a9, a8, 0 | ||
+ | |||
+ | 0x4008f870 <rtc_set_slow_freq+28>: movi a10, 0x12c /* a10 = 300 */ | ||
+ | 0x4008f873 <rtc_set_slow_freq+31>: l32r a8, 0x40080850 | ||
+ | 0x4008f876 <rtc_set_slow_freq+34>: callx8 a8 /* ets_delay_us(300) */ | ||
+ | 0x4008f879 <rtc_set_slow_freq+37>: retw.n | ||
+ | </source> | ||
+ | |||
+ | So: | ||
+ | |||
+ | <source lang=c> | ||
+ | /* | ||
+ | * slow_clk_rtc_sel = 0: SLOW_CK | ||
+ | * slow_clk_rtc_sel = 1: CK_XTAL_32K | ||
+ | * slow_clk_rtc_sel = 2: CK8M_D256_OUT | ||
+ | */ | ||
+ | void rtc_set_slow_freq(uint8_t slow_clk_rtc_sel); | ||
+ | </source> | ||
+ | |||
+ | <br> | ||
+ | |||
+ | ==== rtc_xtal_32k_ena ==== | ||
+ | |||
+ | <source lang=c> | ||
+ | void rtc_xtal_32k_ena(uint8_t enabled); | ||
+ | </source> | ||
+ | |||
+ | more details please refer to: [http://wiki.jackslab.org/ESP32_Smoke_Detector#0x4008f5f4 RTC XTAL 32K enable] | ||
+ | |||
+ | <br> | ||
+ | |||
+ | ==== rtc_init_clk_lite ==== | ||
+ | |||
+ | <source lang=c> | ||
+ | void rtc_init_clk_lite(uint32_t st) | ||
+ | { | ||
+ | rtc_init_clk(st, 1, 0, 0, 255, 172); | ||
+ | } | ||
+ | </source> | ||
+ | |||
+ | More details please refer to: [http://wiki.jackslab.org/ESP32_Smoke_Detector#rtc_init_clk_lite RTC Init Clock Lite] | ||
+ | |||
+ | <br> | ||
+ | |||
+ | ==== rtc_init_clk ==== | ||
+ | |||
+ | <source lang=c> | ||
+ | void rtc_init_clk(uint32_t st, uint8_t fast_clk_sel, uint8_t ck8m_divider, | ||
+ | uint8_t slow_clk_sel,uint8_t sck_dcap,uint8_t ck8_dfreq); | ||
+ | |||
+ | rtc_init_clk(0, 1, 0, 0, 255, 172); | ||
+ | </source> | ||
+ | |||
+ | More details please refer to: [http://wiki.jackslab.org/ESP32_Smoke_Detector#rtc_init_clk RTC Init Clock] | ||
+ | |||
+ | <br> | ||
− | + | === Register === | |
<source lang=cpp> | <source lang=cpp> | ||
第216行: | 第560行: | ||
/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ | /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ | ||
/*description: slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ | /*description: slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 | #define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 | ||
/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ | /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ | ||
/*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ | /*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 | #define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 | ||
/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ | /* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ | ||
/*description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ | /*description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_SOC_CLK_SEL_S 27 | #define RTC_CNTL_SOC_CLK_SEL_S 27 | ||
/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ | /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ | ||
/*description: CK8M force power up*/ | /*description: CK8M force power up*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_CK8M_FORCE_PU_S 26 | #define RTC_CNTL_CK8M_FORCE_PU_S 26 | ||
/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ | /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ | ||
/*description: CK8M force power down*/ | /*description: CK8M force power down*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_CK8M_FORCE_PD_S 25 | #define RTC_CNTL_CK8M_FORCE_PD_S 25 | ||
/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */ | /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */ | ||
/*description: CK8M_DFREQ*/ | /*description: CK8M_DFREQ*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_CK8M_DFREQ_S 17 | #define RTC_CNTL_CK8M_DFREQ_S 17 | ||
/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ | /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ | ||
/*description: CK8M force no gating during sleep*/ | /*description: CK8M force no gating during sleep*/ | ||
− | |||
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− | |||
#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 | #define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 | ||
/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ | /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ | ||
/*description: XTAL force no gating during sleep*/ | /*description: XTAL force no gating during sleep*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 | #define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 | ||
/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */ | /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */ | ||
/*description: divider = reg_ck8m_div_sel + 1*/ | /*description: divider = reg_ck8m_div_sel + 1*/ | ||
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#define RTC_CNTL_CK8M_DIV_SEL_S 12 | #define RTC_CNTL_CK8M_DIV_SEL_S 12 | ||
/* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */ | /* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */ | ||
/*description: */ | /*description: */ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_CK8M_DFREQ_FORCE_S 11 | #define RTC_CNTL_CK8M_DFREQ_FORCE_S 11 | ||
/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ | /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ | ||
/*description: enable CK8M for digital core (no relationship with RTC core)*/ | /*description: enable CK8M for digital core (no relationship with RTC core)*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_DIG_CLK8M_EN_S 10 | #define RTC_CNTL_DIG_CLK8M_EN_S 10 | ||
/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ | /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ | ||
/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ | /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 | #define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 | ||
/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ | /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ | ||
/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ | /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_DIG_XTAL32K_EN_S 8 | #define RTC_CNTL_DIG_XTAL32K_EN_S 8 | ||
/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ | /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ | ||
/*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ | /*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_ENB_CK8M_DIV_S 7 | #define RTC_CNTL_ENB_CK8M_DIV_S 7 | ||
/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ | /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ | ||
/*description: disable CK8M and CK8M_D256_OUT*/ | /*description: disable CK8M and CK8M_D256_OUT*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_ENB_CK8M_S 6 | #define RTC_CNTL_ENB_CK8M_S 6 | ||
/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ | /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ | ||
/*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ | /*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ | ||
− | |||
− | |||
− | |||
#define RTC_CNTL_CK8M_DIV_S 4 | #define RTC_CNTL_CK8M_DIV_S 4 | ||
#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) | #define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) | ||
+ | /* e.g. 0x84160018 */ | ||
+ | /* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */ | ||
+ | /*description: Power up 32kHz crystal oscillator*/ | ||
+ | #define RTC_IO_XPD_XTAL_32K_S 19 | ||
+ | /* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */ | ||
+ | /*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ | ||
+ | #define RTC_IO_X32N_MUX_SEL_S 18 | ||
+ | /* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ | ||
+ | /*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ | ||
+ | #define RTC_IO_X32P_MUX_SEL_S 17 | ||
+ | /* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ | ||
+ | /*description: the functional selection signal of the pad*/ | ||
+ | #define RTC_IO_X32N_FUN_SEL_S 15 | ||
+ | /* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ | ||
+ | /*description: the functional selection signal of the pad*/ | ||
+ | #define RTC_IO_X32P_FUN_SEL_S 9 | ||
</source> | </source> | ||
第355行: | 第667行: | ||
</source> | </source> | ||
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=== rtc_sleep_prep === | === rtc_sleep_prep === | ||
第507行: | 第760行: | ||
<br><br> | <br><br> | ||
− | === | + | === Undocumented === |
==== rtc_pads_muxsel ==== | ==== rtc_pads_muxsel ==== | ||
+ | |||
+ | Set the pad route to the digital IO_MUX (0) or RTC block (1) | ||
<source lang=bash> | <source lang=bash> | ||
第606行: | 第861行: | ||
} rtc_gpio_num_t; | } rtc_gpio_num_t; | ||
+ | /* | ||
+ | * set == 0, route to digital IO_MUX | ||
+ | * set == 1, route to RTC block | ||
+ | */ | ||
void rtc_pads_muxsel(rtc_gpio_num_t rtc_gpio_num, uint8_t sel); | void rtc_pads_muxsel(rtc_gpio_num_t rtc_gpio_num, uint8_t sel); | ||
</source> | </source> | ||
第612行: | 第871行: | ||
==== rtc_pads_funsel ==== | ==== rtc_pads_funsel ==== | ||
+ | |||
+ | Select the RTC function for this pad. | ||
<source lang=bash> | <source lang=bash> | ||
第661行: | 第922行: | ||
0x4008d485 <rtc_pads_funsel+133>: bbci a2, 4, 0x4008d4a5 <rtc_pads_funsel+165> | 0x4008d485 <rtc_pads_funsel+133>: bbci a2, 4, 0x4008d4a5 <rtc_pads_funsel+165> | ||
0x4008d488 <rtc_pads_funsel+136>: l32r a8, 0x4008c9c8 | 0x4008d488 <rtc_pads_funsel+136>: l32r a8, 0x4008c9c8 | ||
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...... | ...... | ||
...... | ...... | ||
+ | </source> | ||
+ | |||
+ | |||
+ | <source lang=cpp> | ||
+ | typedef enum { | ||
+ | RTC_GPIO0 = BIT(0), | ||
+ | RTC_GPIO1 = BIT(1), | ||
+ | ...... | ||
+ | ...... | ||
+ | RTC_GPIO17 = BIT(17) | ||
+ | } rtc_gpio_num_t; | ||
+ | |||
+ | /* | ||
+ | * sel == 0, select the function 0 of rtc | ||
+ | * sel == 1, select the function 1 of rtc | ||
+ | * sel == 2, select the function 2 of rtc | ||
+ | * sel == 3, select the function 3 of rtc | ||
+ | */ | ||
+ | void rtc_pads_funsel(rtc_gpio_num_t rtc_gpio_num, uint8_t sel); | ||
</source> | </source> | ||
第702行: | 第949行: | ||
==== rtc_pads_slpsel ==== | ==== rtc_pads_slpsel ==== | ||
− | + | Sleep mode selection signal of the pad, Set to 1 to put the pad in sleep mode | |
− | = | + | <source lang=bash> |
+ | 0x4008d648 <rtc_pads_slpsel>: entry a1, 32 | ||
+ | 0x4008d64b <rtc_pads_slpsel+3>: bbci a2, 0, 0x4008d66c <rtc_pads_slpsel+36> | ||
+ | 0x4008d64e <rtc_pads_slpsel+6>: l32r a8, 0x4008c9b4 | ||
+ | 0x4008d651 <rtc_pads_slpsel+9>: l32r a9, 0x4008add4 | ||
+ | 0x4008d654 <rtc_pads_slpsel+12>: memw | ||
+ | 0x4008d657 <rtc_pads_slpsel+15>: l32i a11, a8, 0 | ||
+ | 0x4008d65a <rtc_pads_slpsel+18>: extui a10, a3, 0, 1 | ||
+ | 0x4008d65d <rtc_pads_slpsel+21>: slli a10, a10, 21 | ||
+ | 0x4008d660 <rtc_pads_slpsel+24>: and a9, a11, a9 | ||
+ | 0x4008d663 <rtc_pads_slpsel+27>: or a9, a10, a9 | ||
+ | 0x4008d666 <rtc_pads_slpsel+30>: memw | ||
+ | 0x4008d669 <rtc_pads_slpsel+33>: s32i a9, a8, 0 | ||
+ | 0x4008d66c <rtc_pads_slpsel+36>: bbci a2, 1, 0x4008d68d <rtc_pads_slpsel+69> | ||
+ | 0x4008d66f <rtc_pads_slpsel+39>: l32r a8, 0x4008c9b4 | ||
+ | 0x4008d672 <rtc_pads_slpsel+42>: l32r a9, 0x4008bf98 | ||
+ | 0x4008d675 <rtc_pads_slpsel+45>: memw | ||
+ | 0x4008d678 <rtc_pads_slpsel+48>: l32i a11, a8, 0 | ||
+ | 0x4008d67b <rtc_pads_slpsel+51>: extui a10, a3, 0, 1 | ||
+ | 0x4008d67e <rtc_pads_slpsel+54>: slli a10, a10, 16 | ||
+ | 0x4008d681 <rtc_pads_slpsel+57>: and a9, a11, a9 | ||
+ | 0x4008d684 <rtc_pads_slpsel+60>: or a9, a10, a9 | ||
+ | 0x4008d687 <rtc_pads_slpsel+63>: memw | ||
+ | 0x4008d68a <rtc_pads_slpsel+66>: s32i a9, a8, 0 | ||
+ | 0x4008d68d <rtc_pads_slpsel+69>: bbci a2, 2, 0x4008d6ad <rtc_pads_slpsel+101> | ||
+ | 0x4008d690 <rtc_pads_slpsel+72>: l32r a8, 0x4008c9b4 | ||
+ | 0x4008d693 <rtc_pads_slpsel+75>: l32r a9, 0x400888dc | ||
+ | 0x4008d696 <rtc_pads_slpsel+78>: memw | ||
+ | 0x4008d699 <rtc_pads_slpsel+81>: l32i.n a11, a8, 0 | ||
+ | 0x4008d69b <rtc_pads_slpsel+83>: extui a10, a3, 0, 1 | ||
+ | 0x4008d69e <rtc_pads_slpsel+86>: slli a10, a10, 11 | ||
+ | 0x4008d6a1 <rtc_pads_slpsel+89>: and a9, a11, a9 | ||
+ | 0x4008d6a4 <rtc_pads_slpsel+92>: or a9, a10, a9 | ||
+ | 0x4008d6a7 <rtc_pads_slpsel+95>: memw | ||
+ | 0x4008d6aa <rtc_pads_slpsel+98>: s32i a9, a8, 0 | ||
+ | 0x4008d6ad <rtc_pads_slpsel+101>: bbci a2, 3, 0x4008d6cd <rtc_pads_slpsel+133> | ||
+ | 0x4008d6b0 <rtc_pads_slpsel+104>: l32r a8, 0x4008c9b4 | ||
+ | ...... | ||
+ | ...... | ||
+ | </source> | ||
− | |||
− | ==== | + | <source lang=cpp> |
+ | typedef enum { | ||
+ | RTC_GPIO0 = BIT(0), | ||
+ | RTC_GPIO1 = BIT(1), | ||
+ | ...... | ||
+ | ...... | ||
+ | RTC_GPIO17 = BIT(17) | ||
+ | } rtc_gpio_num_t; | ||
+ | |||
+ | /* | ||
+ | * sel == 1, put the pad in sleep mode | ||
+ | */ | ||
+ | void rtc_pads_slpsel(rtc_gpio_num_t rtc_gpio_num, uint8_t sel); | ||
+ | </source> | ||
<br> | <br> | ||
==== rtc_pads_slpie ==== | ==== rtc_pads_slpie ==== | ||
+ | |||
+ | <source lang=bash> | ||
+ | 0x4008da1c <rtc_pads_slpie>: entry a1, 32 | ||
+ | 0x4008da1f <rtc_pads_slpie+3>: bbci a2, 6, 0x4008da40 <rtc_pads_slpie+36> | ||
+ | 0x4008da22 <rtc_pads_slpie+6>: l32r a8, 0x4008bfa4 | ||
+ | 0x4008da25 <rtc_pads_slpie+9>: l32r a9, 0x4008da18 | ||
+ | 0x4008da28 <rtc_pads_slpie+12>: memw | ||
+ | 0x4008da2b <rtc_pads_slpie+15>: l32i a11, a8, 0 | ||
+ | 0x4008da2e <rtc_pads_slpie+18>: extui a10, a3, 0, 1 | ||
+ | 0x4008da31 <rtc_pads_slpie+21>: slli a10, a10, 13 | ||
+ | 0x4008da34 <rtc_pads_slpie+24>: and a9, a11, a9 | ||
+ | 0x4008da37 <rtc_pads_slpie+27>: or a9, a10, a9 | ||
+ | 0x4008da3a <rtc_pads_slpie+30>: memw | ||
+ | 0x4008da3d <rtc_pads_slpie+33>: s32i a9, a8, 0 | ||
+ | 0x4008da40 <rtc_pads_slpie+36>: bbci a2, 7, 0x4008da61 <rtc_pads_slpie+69> | ||
+ | 0x4008da43 <rtc_pads_slpie+39>: l32r a8, 0x4008bfb0 | ||
+ | 0x4008da46 <rtc_pads_slpie+42>: l32r a9, 0x4008da18 | ||
+ | 0x4008da49 <rtc_pads_slpie+45>: memw | ||
+ | 0x4008da4c <rtc_pads_slpie+48>: l32i a11, a8, 0 | ||
+ | 0x4008da4f <rtc_pads_slpie+51>: extui a10, a3, 0, 1 | ||
+ | 0x4008da52 <rtc_pads_slpie+54>: slli a10, a10, 13 | ||
+ | 0x4008da55 <rtc_pads_slpie+57>: and a9, a11, a9 | ||
+ | 0x4008da58 <rtc_pads_slpie+60>: or a9, a10, a9 | ||
+ | 0x4008da5b <rtc_pads_slpie+63>: memw | ||
+ | 0x4008da5e <rtc_pads_slpie+66>: s32i a9, a8, 0 | ||
+ | 0x4008da61 <rtc_pads_slpie+69>: bbci a2, 8, 0x4008da81 <rtc_pads_slpie+101> | ||
+ | 0x4008da64 <rtc_pads_slpie+72>: l32r a8, 0x4008c9bc | ||
+ | 0x4008da67 <rtc_pads_slpie+75>: l32r a9, 0x4008da18 | ||
+ | 0x4008da6a <rtc_pads_slpie+78>: memw | ||
+ | 0x4008da6d <rtc_pads_slpie+81>: l32i.n a11, a8, 0 | ||
+ | 0x4008da6f <rtc_pads_slpie+83>: extui a10, a3, 0, 1 | ||
+ | 0x4008da72 <rtc_pads_slpie+86>: slli a10, a10, 13 | ||
+ | 0x4008da75 <rtc_pads_slpie+89>: and a9, a11, a9 | ||
+ | 0x4008da78 <rtc_pads_slpie+92>: or a9, a10, a9 | ||
+ | 0x4008da7b <rtc_pads_slpie+95>: memw | ||
+ | 0x4008da7e <rtc_pads_slpie+98>: s32i a9, a8, 0 | ||
+ | 0x4008da81 <rtc_pads_slpie+101>: bbci a2, 9, 0x4008daa1 <rtc_pads_slpie+133> | ||
+ | 0x4008da84 <rtc_pads_slpie+104>: l32r a8, 0x4008c9bc | ||
+ | ...... | ||
+ | ...... | ||
+ | </source> | ||
+ | |||
+ | <source lang=cpp> | ||
+ | typedef enum { | ||
+ | RTC_GPIO0 = BIT(0), | ||
+ | RTC_GPIO1 = BIT(1), | ||
+ | ...... | ||
+ | ...... | ||
+ | RTC_GPIO17 = BIT(17) | ||
+ | } rtc_gpio_num_t; | ||
+ | |||
+ | /* | ||
+ | * sel == 1, put the pad in sleep mode | ||
+ | * | ||
+ | * Only valide for RTC_GPIO6 - RTC_GPIO17 | ||
+ | */ | ||
+ | void rtc_pads_slpie(rtc_gpio_num_t rtc_gpio_num, uint8_t enable); | ||
+ | </source> | ||
<br> | <br> | ||
==== rtc_pads_funie ==== | ==== rtc_pads_funie ==== | ||
+ | |||
+ | Input enable of the pad. | ||
+ | |||
+ | <source lang=bash> | ||
+ | 0x4008dba4 <rtc_pads_funie>: entry a1, 32 | ||
+ | 0x4008dba7 <rtc_pads_funie+3>: bbci a2, 6, 0x4008dbc8 <rtc_pads_funie+36> | ||
+ | 0x4008dbaa <rtc_pads_funie+6>: l32r a8, 0x4008bfa4 | ||
+ | 0x4008dbad <rtc_pads_funie+9>: l32r a9, 0x400888dc | ||
+ | 0x4008dbb0 <rtc_pads_funie+12>: memw | ||
+ | 0x4008dbb3 <rtc_pads_funie+15>: l32i a11, a8, 0 | ||
+ | 0x4008dbb6 <rtc_pads_funie+18>: extui a10, a3, 0, 1 | ||
+ | 0x4008dbb9 <rtc_pads_funie+21>: slli a10, a10, 11 | ||
+ | 0x4008dbbc <rtc_pads_funie+24>: and a9, a11, a9 | ||
+ | 0x4008dbbf <rtc_pads_funie+27>: or a9, a10, a9 | ||
+ | 0x4008dbc2 <rtc_pads_funie+30>: memw | ||
+ | 0x4008dbc5 <rtc_pads_funie+33>: s32i a9, a8, 0 | ||
+ | 0x4008dbc8 <rtc_pads_funie+36>: bbci a2, 7, 0x4008dbe9 <rtc_pads_funie+69> | ||
+ | 0x4008dbcb <rtc_pads_funie+39>: l32r a8, 0x4008bfb0 | ||
+ | 0x4008dbce <rtc_pads_funie+42>: l32r a9, 0x400888dc | ||
+ | 0x4008dbd1 <rtc_pads_funie+45>: memw | ||
+ | 0x4008dbd4 <rtc_pads_funie+48>: l32i a11, a8, 0 | ||
+ | 0x4008dbd7 <rtc_pads_funie+51>: extui a10, a3, 0, 1 | ||
+ | 0x4008dbda <rtc_pads_funie+54>: slli a10, a10, 11 | ||
+ | 0x4008dbdd <rtc_pads_funie+57>: and a9, a11, a9 | ||
+ | 0x4008dbe0 <rtc_pads_funie+60>: or a9, a10, a9 | ||
+ | 0x4008dbe3 <rtc_pads_funie+63>: memw | ||
+ | 0x4008dbe6 <rtc_pads_funie+66>: s32i a9, a8, 0 | ||
+ | 0x4008dbe9 <rtc_pads_funie+69>: bbci a2, 8, 0x4008dc09 <rtc_pads_funie+101> | ||
+ | 0x4008dbec <rtc_pads_funie+72>: l32r a8, 0x4008c9bc | ||
+ | ...... | ||
+ | ...... | ||
+ | </source> | ||
+ | |||
+ | <source lang=cpp> | ||
+ | typedef enum { | ||
+ | RTC_GPIO0 = BIT(0), | ||
+ | RTC_GPIO1 = BIT(1), | ||
+ | ...... | ||
+ | ...... | ||
+ | RTC_GPIO17 = BIT(17) | ||
+ | } rtc_gpio_num_t; | ||
+ | |||
+ | /* | ||
+ | * enable == 1, input enable | ||
+ | * enable == 0, input disable | ||
+ | * | ||
+ | * Only the RTC_GPIO6 - RTC_GPIO17 are valide | ||
+ | */ | ||
+ | void rtc_pads_funie (rtc_gpio_num_t rtc_gpio_num, uint8_t enable); | ||
+ | </source> | ||
+ | |||
+ | <br> | ||
+ | |||
+ | ==== rtc_pads_slpoe ==== | ||
+ | |||
+ | Output enable of the pad. | ||
+ | |||
+ | <source lang=bash> | ||
+ | 0x4008d890 <rtc_pads_slpoe>: entry a1, 32 | ||
+ | 0x4008d893 <rtc_pads_slpoe+3>: bbci a2, 6, 0x4008d8b4 <rtc_pads_slpoe+36> | ||
+ | 0x4008d896 <rtc_pads_slpoe+6>: l32r a8, 0x4008bfa4 | ||
+ | 0x4008d899 <rtc_pads_slpoe+9>: l32r a9, 0x40087114 | ||
+ | 0x4008d89c <rtc_pads_slpoe+12>: memw | ||
+ | 0x4008d89f <rtc_pads_slpoe+15>: l32i a11, a8, 0 | ||
+ | 0x4008d8a2 <rtc_pads_slpoe+18>: extui a10, a3, 0, 1 | ||
+ | 0x4008d8a5 <rtc_pads_slpoe+21>: slli a10, a10, 12 | ||
+ | 0x4008d8a8 <rtc_pads_slpoe+24>: and a9, a11, a9 | ||
+ | 0x4008d8ab <rtc_pads_slpoe+27>: or a9, a10, a9 | ||
+ | 0x4008d8ae <rtc_pads_slpoe+30>: memw | ||
+ | 0x4008d8b1 <rtc_pads_slpoe+33>: s32i a9, a8, 0 | ||
+ | 0x4008d8b4 <rtc_pads_slpoe+36>: bbci a2, 7, 0x4008d8d5 <rtc_pads_slpoe+69> | ||
+ | 0x4008d8b7 <rtc_pads_slpoe+39>: l32r a8, 0x4008bfb0 | ||
+ | 0x4008d8ba <rtc_pads_slpoe+42>: l32r a9, 0x40087114 | ||
+ | 0x4008d8bd <rtc_pads_slpoe+45>: memw | ||
+ | 0x4008d8c0 <rtc_pads_slpoe+48>: l32i a11, a8, 0 | ||
+ | 0x4008d8c3 <rtc_pads_slpoe+51>: extui a10, a3, 0, 1 | ||
+ | 0x4008d8c6 <rtc_pads_slpoe+54>: slli a10, a10, 12 | ||
+ | 0x4008d8c9 <rtc_pads_slpoe+57>: and a9, a11, a9 | ||
+ | 0x4008d8cc <rtc_pads_slpoe+60>: or a9, a10, a9 | ||
+ | 0x4008d8cf <rtc_pads_slpoe+63>: memw | ||
+ | 0x4008d8d2 <rtc_pads_slpoe+66>: s32i a9, a8, 0 | ||
+ | 0x4008d8d5 <rtc_pads_slpoe+69>: bbci a2, 8, 0x4008d8f5 <rtc_pads_slpoe+101> | ||
+ | 0x4008d8d8 <rtc_pads_slpoe+72>: l32r a8, 0x4008c9bc | ||
+ | ...... | ||
+ | ...... | ||
+ | </source> | ||
+ | |||
+ | <source lang=cpp> | ||
+ | typedef enum { | ||
+ | RTC_GPIO0 = BIT(0), | ||
+ | RTC_GPIO1 = BIT(1), | ||
+ | ...... | ||
+ | ...... | ||
+ | RTC_GPIO17 = BIT(17) | ||
+ | } rtc_gpio_num_t; | ||
+ | |||
+ | /* | ||
+ | * enable == 1, Output enable | ||
+ | * enable == 0, Output disable | ||
+ | * Only RTC_GPIO6 - RTC_GPIO17 are valide | ||
+ | */ | ||
+ | void rtc_pads_slpoe(rtc_gpio_num_t rtc_gpio_num, uint8_t enable); | ||
+ | </source> | ||
+ | |||
+ | <br> | ||
+ | |||
+ | ==== rtc_pads_hold ==== | ||
+ | |||
+ | <source lang=bash> | ||
+ | 0x4008e03c <rtc_pads_hold>: entry a1, 32 | ||
+ | 0x4008e03f <rtc_pads_hold+3>: bbci a2, 6, 0x4008e060 <rtc_pads_hold+36> | ||
+ | 0x4008e042 <rtc_pads_hold+6>: l32r a8, 0x4008bfa4 | ||
+ | 0x4008e045 <rtc_pads_hold+9>: l32r a9, 0x4008620c | ||
+ | 0x4008e048 <rtc_pads_hold+12>: memw | ||
+ | 0x4008e04b <rtc_pads_hold+15>: l32i a11, a8, 0 | ||
+ | 0x4008e04e <rtc_pads_hold+18>: extui a10, a3, 0, 1 | ||
+ | 0x4008e051 <rtc_pads_hold+21>: slli a10, a10, 29 | ||
+ | 0x4008e054 <rtc_pads_hold+24>: and a9, a11, a9 | ||
+ | 0x4008e057 <rtc_pads_hold+27>: or a9, a10, a9 | ||
+ | 0x4008e05a <rtc_pads_hold+30>: memw | ||
+ | 0x4008e05d <rtc_pads_hold+33>: s32i a9, a8, 0 | ||
+ | 0x4008e060 <rtc_pads_hold+36>: bbci a2, 7, 0x4008e081 <rtc_pads_hold+69> | ||
+ | 0x4008e063 <rtc_pads_hold+39>: l32r a8, 0x4008bfb0 | ||
+ | 0x4008e066 <rtc_pads_hold+42>: l32r a9, 0x4008620c | ||
+ | 0x4008e069 <rtc_pads_hold+45>: memw | ||
+ | 0x4008e06c <rtc_pads_hold+48>: l32i a11, a8, 0 | ||
+ | 0x4008e06f <rtc_pads_hold+51>: extui a10, a3, 0, 1 | ||
+ | 0x4008e072 <rtc_pads_hold+54>: slli a10, a10, 29 | ||
+ | 0x4008e075 <rtc_pads_hold+57>: and a9, a11, a9 | ||
+ | 0x4008e078 <rtc_pads_hold+60>: or a9, a10, a9 | ||
+ | 0x4008e07b <rtc_pads_hold+63>: memw | ||
+ | 0x4008e07e <rtc_pads_hold+66>: s32i a9, a8, 0 | ||
+ | 0x4008e081 <rtc_pads_hold+69>: bbci a2, 8, 0x4008e0a1 <rtc_pads_hold+101> | ||
+ | 0x4008e084 <rtc_pads_hold+72>: l32r a8, 0x4008c9bc | ||
+ | 0x4008e087 <rtc_pads_hold+75>: l32r a9, 0x4008620c | ||
+ | ...... | ||
+ | ...... | ||
+ | </source> | ||
+ | |||
+ | <source lang=cpp> | ||
+ | typedef enum { | ||
+ | RTC_GPIO0 = BIT(0), | ||
+ | RTC_GPIO1 = BIT(1), | ||
+ | ...... | ||
+ | ...... | ||
+ | RTC_GPIO17 = BIT(17) | ||
+ | } rtc_gpio_num_t; | ||
+ | |||
+ | /* | ||
+ | * hold == 1, Hold output value | ||
+ | * hold == 0, normal operation | ||
+ | * Only RTC_GPIO6 - RTC_GPIO17 are valide | ||
+ | */ | ||
+ | void rtc_pads_hold(rtc_gpio_num_t rtc_gpio_num, uint8_t hold); | ||
+ | </source> | ||
<br> | <br> | ||
==== rtc_pads_pu ==== | ==== rtc_pads_pu ==== | ||
+ | |||
+ | <source lang=bash> | ||
+ | 0x4008dd2c <rtc_pads_pu>: entry a1, 32 | ||
+ | 0x4008dd2f <rtc_pads_pu+3>: bbci a2, 6, 0x4008dd50 <rtc_pads_pu+36> | ||
+ | 0x4008dd32 <rtc_pads_pu+6>: l32r a8, 0x4008bfa4 | ||
+ | 0x4008dd35 <rtc_pads_pu+9>: l32r a9, 0x40084bc0 | ||
+ | 0x4008dd38 <rtc_pads_pu+12>: memw | ||
+ | 0x4008dd3b <rtc_pads_pu+15>: l32i a11, a8, 0 | ||
+ | 0x4008dd3e <rtc_pads_pu+18>: extui a10, a3, 0, 1 | ||
+ | 0x4008dd41 <rtc_pads_pu+21>: slli a10, a10, 27 | ||
+ | 0x4008dd44 <rtc_pads_pu+24>: and a9, a11, a9 | ||
+ | 0x4008dd47 <rtc_pads_pu+27>: or a9, a10, a9 | ||
+ | 0x4008dd4a <rtc_pads_pu+30>: memw | ||
+ | 0x4008dd4d <rtc_pads_pu+33>: s32i a9, a8, 0 | ||
+ | 0x4008dd50 <rtc_pads_pu+36>: bbci a2, 7, 0x4008dd71 <rtc_pads_pu+69> | ||
+ | 0x4008dd53 <rtc_pads_pu+39>: l32r a8, 0x4008bfb0 | ||
+ | 0x4008dd56 <rtc_pads_pu+42>: l32r a9, 0x40084bc0 | ||
+ | 0x4008dd59 <rtc_pads_pu+45>: memw | ||
+ | 0x4008dd5c <rtc_pads_pu+48>: l32i a11, a8, 0 | ||
+ | 0x4008dd5f <rtc_pads_pu+51>: extui a10, a3, 0, 1 | ||
+ | 0x4008dd62 <rtc_pads_pu+54>: slli a10, a10, 27 | ||
+ | 0x4008dd65 <rtc_pads_pu+57>: and a9, a11, a9 | ||
+ | 0x4008dd68 <rtc_pads_pu+60>: or a9, a10, a9 | ||
+ | 0x4008dd6b <rtc_pads_pu+63>: memw | ||
+ | 0x4008dd6e <rtc_pads_pu+66>: s32i a9, a8, 0 | ||
+ | 0x4008dd71 <rtc_pads_pu+69>: bbci a2, 8, 0x4008dd91 <rtc_pads_pu+101> | ||
+ | 0x4008dd74 <rtc_pads_pu+72>: l32r a8, 0x4008c9bc | ||
+ | 0x4008dd77 <rtc_pads_pu+75>: l32r a9, 0x40084bc0 | ||
+ | ...... | ||
+ | ...... | ||
+ | </source> | ||
+ | |||
+ | <source lang=cpp> | ||
+ | typedef enum { | ||
+ | RTC_GPIO0 = BIT(0), | ||
+ | RTC_GPIO1 = BIT(1), | ||
+ | ...... | ||
+ | ...... | ||
+ | RTC_GPIO17 = BIT(17) | ||
+ | } rtc_gpio_num_t; | ||
+ | |||
+ | /* | ||
+ | * pu == 1, pull-up enable | ||
+ | * pu == 0, pull-up disable | ||
+ | * Only RTC_GPIO6 - RTC_GPIO17 are valide | ||
+ | */ | ||
+ | void rtc_pads_pu(rtc_gpio_num_t rtc_gpio_num, uint8_t pu); | ||
+ | </source> | ||
<br> | <br> | ||
==== rtc_pads_pd ==== | ==== rtc_pads_pd ==== | ||
+ | |||
+ | <source lang=bash> | ||
+ | 0x4008deb4 <rtc_pads_pd>: entry a1, 32 | ||
+ | 0x4008deb7 <rtc_pads_pd+3>: bbci a2, 6, 0x4008ded8 <rtc_pads_pd+36> | ||
+ | 0x4008deba <rtc_pads_pd+6>: l32r a8, 0x4008bfa4 | ||
+ | 0x4008debd <rtc_pads_pd+9>: l32r a9, 0x40087110 | ||
+ | 0x4008dec0 <rtc_pads_pd+12>: memw | ||
+ | 0x4008dec3 <rtc_pads_pd+15>: l32i a11, a8, 0 | ||
+ | 0x4008dec6 <rtc_pads_pd+18>: extui a10, a3, 0, 1 | ||
+ | 0x4008dec9 <rtc_pads_pd+21>: slli a10, a10, 28 | ||
+ | 0x4008decc <rtc_pads_pd+24>: and a9, a11, a9 | ||
+ | 0x4008decf <rtc_pads_pd+27>: or a9, a10, a9 | ||
+ | 0x4008ded2 <rtc_pads_pd+30>: memw | ||
+ | 0x4008ded5 <rtc_pads_pd+33>: s32i a9, a8, 0 | ||
+ | 0x4008ded8 <rtc_pads_pd+36>: bbci a2, 7, 0x4008def9 <rtc_pads_pd+69> | ||
+ | 0x4008dedb <rtc_pads_pd+39>: l32r a8, 0x4008bfb0 | ||
+ | 0x4008dede <rtc_pads_pd+42>: l32r a9, 0x40087110 | ||
+ | 0x4008dee1 <rtc_pads_pd+45>: memw | ||
+ | 0x4008dee4 <rtc_pads_pd+48>: l32i a11, a8, 0 | ||
+ | 0x4008dee7 <rtc_pads_pd+51>: extui a10, a3, 0, 1 | ||
+ | 0x4008deea <rtc_pads_pd+54>: slli a10, a10, 28 | ||
+ | 0x4008deed <rtc_pads_pd+57>: and a9, a11, a9 | ||
+ | 0x4008def0 <rtc_pads_pd+60>: or a9, a10, a9 | ||
+ | 0x4008def3 <rtc_pads_pd+63>: memw | ||
+ | 0x4008def6 <rtc_pads_pd+66>: s32i a9, a8, 0 | ||
+ | 0x4008def9 <rtc_pads_pd+69>: bbci a2, 8, 0x4008df19 <rtc_pads_pd+101> | ||
+ | 0x4008defc <rtc_pads_pd+72>: l32r a8, 0x4008c9bc | ||
+ | 0x4008deff <rtc_pads_pd+75>: l32r a9, 0x40087110 | ||
+ | ...... | ||
+ | ...... | ||
+ | </source> | ||
+ | |||
+ | <source lang=cpp> | ||
+ | typedef enum { | ||
+ | RTC_GPIO0 = BIT(0), | ||
+ | RTC_GPIO1 = BIT(1), | ||
+ | ...... | ||
+ | ...... | ||
+ | RTC_GPIO17 = BIT(17) | ||
+ | } rtc_gpio_num_t; | ||
+ | |||
+ | /* | ||
+ | * pd == 1, pull-down enable | ||
+ | * pd == 0, pull-down disable | ||
+ | * Only RTC_GPIO6 - RTC_GPIO17 are valide | ||
+ | */ | ||
+ | void rtc_pads_pd(rtc_gpio_num_t rtc_gpio_num, uint8_t pd); | ||
+ | </source> | ||
<br> | <br> | ||
第787行: | 第1,394行: | ||
==== rtc_pad_ext_wakeup ==== | ==== rtc_pad_ext_wakeup ==== | ||
− | + | Following: | |
− | ==== | + | * p1 is the 1st parameter of rtc_pad_ext_wakeup |
+ | * p2 is the 2nd parameter of rtc_pad_ext_wakeup | ||
+ | * p3 is the 3rd parameter of rtc_pad_ext_wakeup | ||
+ | |||
+ | <source lang=c> | ||
+ | 0x4008ee9c <rtc_pad_ext_wakeup>: entry a1, 32 | ||
+ | 0x4008ee9f <rtc_pad_ext_wakeup+3>: mov.n a10, a2 | ||
+ | 0x4008eea1 <rtc_pad_ext_wakeup+5>: movi.n a11, 1 | ||
+ | 0x4008eea3 <rtc_pad_ext_wakeup+7>: call8 0x4008d2f4 <rtc_pads_muxsel> /* rtc_pads_muxsel (p1, 1) */ | ||
+ | |||
+ | 0x4008eea6 <rtc_pad_ext_wakeup+10>: mov.n a10, a2 | ||
+ | 0x4008eea8 <rtc_pad_ext_wakeup+12>: movi.n a11, 0 | ||
+ | 0x4008eeaa <rtc_pad_ext_wakeup+14>: call8 0x4008d54c <rtc_pads_funsel> /* rtc_pads_funsel (p1, 0) */ | ||
+ | |||
+ | 0x4008eead <rtc_pad_ext_wakeup+17>: l32r a8, 0x4008edf4 /* a8 = *(4008edf4) = 0x3ff4840c, RTC_GPIO_ENABLE_REG */ | ||
+ | 0x4008eeb0 <rtc_pad_ext_wakeup+20>: slli a9, a2, 14 | ||
+ | 0x4008eeb3 <rtc_pad_ext_wakeup+23>: memw | ||
+ | 0x4008eeb6 <rtc_pad_ext_wakeup+26>: l32i.n a10, a8, 0 /* a10 = read RTC_GPIO_ENABLE_REG */ | ||
+ | 0x4008eeb8 <rtc_pad_ext_wakeup+28>: movi.n a11, -1 /* a11 = 0xffff ffff */ | ||
+ | 0x4008eeba <rtc_pad_ext_wakeup+30>: xor a9, a11, a9 /* a9 = ~a9 */ | ||
+ | 0x4008eebd <rtc_pad_ext_wakeup+33>: and a9, a9, a10 /* a9 = a10 & a9 */ | ||
+ | 0x4008eec0 <rtc_pad_ext_wakeup+36>: memw | ||
+ | 0x4008eec3 <rtc_pad_ext_wakeup+39>: s32i.n a9, a8, 0 /* store to RTC_GPIO_ENABLE_REG, disable the output of the RTC_PAD */ | ||
+ | |||
+ | 0x4008eec5 <rtc_pad_ext_wakeup+41>: mov.n a10, a2 | ||
+ | 0x4008eec7 <rtc_pad_ext_wakeup+43>: movi a11, 1 | ||
+ | 0x4008eeca <rtc_pad_ext_wakeup+46>: call8 0x4008d794 <rtc_pads_slpsel> /* rtc_pads_slpsel (p1, 1) */ | ||
+ | |||
+ | 0x4008eecd <rtc_pad_ext_wakeup+49>: mov.n a10, a2 | ||
+ | 0x4008eecf <rtc_pad_ext_wakeup+51>: movi a11, 0 | ||
+ | 0x4008eed2 <rtc_pad_ext_wakeup+54>: call8 0x4008d9dc <rtc_pads_slpoe> /* rtc_pads_slpoe (p1, 0) */ | ||
+ | |||
+ | 0x4008eed5 <rtc_pad_ext_wakeup+57>: mov.n a10, a2 | ||
+ | 0x4008eed7 <rtc_pad_ext_wakeup+59>: movi a11, 1 | ||
+ | 0x4008eeda <rtc_pad_ext_wakeup+62>: call8 0x4008db68 <rtc_pads_slpie> /* rtc_pads_slpie (p1, 1) */ | ||
+ | |||
+ | 0x4008eedd <rtc_pad_ext_wakeup+65>: mov.n a10, a2 | ||
+ | 0x4008eedf <rtc_pad_ext_wakeup+67>: movi a11, 1 | ||
+ | 0x4008eee2 <rtc_pad_ext_wakeup+70>: call8 0x4008dcf0 <rtc_pads_funie> /* rtc_pads_funie (p1, 1) */ | ||
+ | |||
+ | 0x4008eee5 <rtc_pad_ext_wakeup+73>: mov.n a10, a2 | ||
+ | 0x4008eee7 <rtc_pad_ext_wakeup+75>: movi a11, 0 | ||
+ | 0x4008eeea <rtc_pad_ext_wakeup+78>: call8 0x4008de78 <rtc_pads_pu> /* rtc_pads_pu (p1, 0) */ | ||
+ | |||
+ | 0x4008eeed <rtc_pad_ext_wakeup+81>: mov.n a10, a2 | ||
+ | 0x4008eeef <rtc_pad_ext_wakeup+83>: movi.n a11, 0 | ||
+ | 0x4008eef1 <rtc_pad_ext_wakeup+85>: call8 0x4008e000 <rtc_pads_pd> /* rtc_pads_pd (p1, 0) */ | ||
+ | |||
+ | 0x4008eef4 <rtc_pad_ext_wakeup+88>: l32r a8, 0x4008ee90 /* a8 = *(0x4008ee90) = 0x3ff484bc, RTC_IO_EXT_WAKEUP0_REG */ | ||
+ | 0x4008eef7 <rtc_pad_ext_wakeup+91>: l32r a2, 0x4008ee94 /* a2 = *(0x4008ee94) = 0x07ffffff */ | ||
+ | 0x4008eefa <rtc_pad_ext_wakeup+94>: memw | ||
+ | 0x4008eefd <rtc_pad_ext_wakeup+97>: l32i.n a9, a8, 0 /* a9 = read RTC_IO_EXT_WAKEUP0_REG */ | ||
+ | 0x4008eeff <rtc_pad_ext_wakeup+99>: slli a3, a3, 27 /* a3 = p2 << 27 */ | ||
+ | 0x4008ef02 <rtc_pad_ext_wakeup+102>: and a9, a9, a2 /* a9 = RTC_IO_EXT_WAKEUP0_REG & 0x07ff ffff */ | ||
+ | 0x4008ef05 <rtc_pad_ext_wakeup+105>: or a3, a3, a9 /* a3 = (p2 << 27) | a9 */ | ||
+ | |||
+ | 0x4008ef08 <rtc_pad_ext_wakeup+108>: l32r a2, 0x4008ee98 /* a2 = *(0x4008ee98) = 0x3ff48060, RTC_CNTL_EXT_WAKEUP_CONF_REG */ | ||
+ | 0x4008ef0b <rtc_pad_ext_wakeup+111>: memw | ||
+ | 0x4008ef0e <rtc_pad_ext_wakeup+114>: s32i.n a3, a8, 0 /* write to RTC_IO_EXT_WAKEUP0_REG */ | ||
+ | |||
+ | 0x4008ef10 <rtc_pad_ext_wakeup+116>: memw | ||
+ | 0x4008ef13 <rtc_pad_ext_wakeup+119>: l32i.n a8, a2, 0 /* a8 = read RTC_CNTL_EXT_WAKEUP_CONF_REG */ | ||
+ | 0x4008ef15 <rtc_pad_ext_wakeup+121>: l32r a3, 0x4008838c /* a3 = *(0x4008838c) = 0xbfffffff */ | ||
+ | |||
+ | 0x4008ef18 <rtc_pad_ext_wakeup+124>: extui a4, a4, 0, 1 /* a4 = p3[0] */ | ||
+ | 0x4008ef1b <rtc_pad_ext_wakeup+127>: slli a4, a4, 30 /* a4 = a4 << 30 */ | ||
+ | |||
+ | 0x4008ef1e <rtc_pad_ext_wakeup+130>: and a3, a8, a3 /* a3 = a8 & a3 = RTC_CNTL_EXT_WAKEUP_CONF_REG & 0xbfff ffff */ | ||
+ | 0x4008ef21 <rtc_pad_ext_wakeup+133>: or a4, a4, a3 /* a4 = RTC_CNTL_EXT_WAKEUP_CONF_REG & 0xbfff ffff | (p3[0] << 30) */ | ||
+ | 0x4008ef24 <rtc_pad_ext_wakeup+136>: memw | ||
+ | 0x4008ef27 <rtc_pad_ext_wakeup+139>: s32i.n a4, a2, 0 /* write to RTC_CNTL_EXT_WAKEUP_CONF_REG */ | ||
+ | |||
+ | /* use the EXT_WAKEUP0, 0: external wakeup at low level 1: external wakeup at high level */ | ||
+ | |||
+ | 0x4008ef29 <rtc_pad_ext_wakeup+141>: retw.n | ||
+ | </source> | ||
+ | |||
+ | So: | ||
+ | |||
+ | <source lang=c> | ||
+ | typedef enum { | ||
+ | RTC_GPIO0 = BIT(0), | ||
+ | RTC_GPIO1 = BIT(1), | ||
+ | ...... | ||
+ | ...... | ||
+ | RTC_GPIO17 = BIT(17) | ||
+ | } rtc_gpio_num_t; | ||
+ | |||
+ | /* | ||
+ | * rtc_io_num is the number of rtc_pad. e.g. The number of RTC_GPIO5 is 5 | ||
+ | * wakeup_level = 0: external wakeup at low level | ||
+ | * wakeup_level = 1: external wakeup at high level | ||
+ | */ | ||
+ | void rtc_pad_ext_wakeup(rtc_gpio_num_t rtc_pad, uint8_t rtc_io_num, uint8_t wakeup_level); | ||
+ | </source> | ||
<br> | <br> | ||
==== rtc_cmd_ext_wakeup ==== | ==== rtc_cmd_ext_wakeup ==== | ||
+ | |||
+ | <source lang=bash> | ||
+ | 0x4008ef2c <rtc_cmd_ext_wakeup>: entry a1, 32 | ||
+ | 0x4008ef2f <rtc_cmd_ext_wakeup+3>: mov.n a10, a2 | ||
+ | 0x4008ef31 <rtc_cmd_ext_wakeup+5>: movi.n a11, 1 | ||
+ | 0x4008ef33 <rtc_cmd_ext_wakeup+7>: call8 0x4008d2f4 <rtc_pads_muxsel> | ||
+ | 0x4008ef36 <rtc_cmd_ext_wakeup+10>: mov.n a10, a2 | ||
+ | 0x4008ef38 <rtc_cmd_ext_wakeup+12>: movi.n a11, 0 | ||
+ | 0x4008ef3a <rtc_cmd_ext_wakeup+14>: call8 0x4008d54c <rtc_pads_funsel> | ||
+ | 0x4008ef3d <rtc_cmd_ext_wakeup+17>: l32r a8, 0x4008edf4 | ||
+ | 0x4008ef40 <rtc_cmd_ext_wakeup+20>: slli a9, a2, 14 | ||
+ | 0x4008ef43 <rtc_cmd_ext_wakeup+23>: memw | ||
+ | 0x4008ef46 <rtc_cmd_ext_wakeup+26>: l32i.n a10, a8, 0 | ||
+ | 0x4008ef48 <rtc_cmd_ext_wakeup+28>: movi.n a11, -1 | ||
+ | 0x4008ef4a <rtc_cmd_ext_wakeup+30>: xor a9, a11, a9 | ||
+ | 0x4008ef4d <rtc_cmd_ext_wakeup+33>: and a9, a9, a10 | ||
+ | 0x4008ef50 <rtc_cmd_ext_wakeup+36>: memw | ||
+ | 0x4008ef53 <rtc_cmd_ext_wakeup+39>: s32i.n a9, a8, 0 | ||
+ | 0x4008ef55 <rtc_cmd_ext_wakeup+41>: mov.n a10, a2 | ||
+ | 0x4008ef57 <rtc_cmd_ext_wakeup+43>: movi a11, 1 | ||
+ | 0x4008ef5a <rtc_cmd_ext_wakeup+46>: call8 0x4008d794 <rtc_pads_slpsel> | ||
+ | 0x4008ef5d <rtc_cmd_ext_wakeup+49>: mov.n a10, a2 | ||
+ | 0x4008ef5f <rtc_cmd_ext_wakeup+51>: movi a11, 0 | ||
+ | 0x4008ef62 <rtc_cmd_ext_wakeup+54>: call8 0x4008d9dc <rtc_pads_slpoe> | ||
+ | 0x4008ef65 <rtc_cmd_ext_wakeup+57>: mov.n a10, a2 | ||
+ | 0x4008ef67 <rtc_cmd_ext_wakeup+59>: movi a11, 1 | ||
+ | 0x4008ef6a <rtc_cmd_ext_wakeup+62>: call8 0x4008db68 <rtc_pads_slpie> | ||
+ | 0x4008ef6d <rtc_cmd_ext_wakeup+65>: mov.n a10, a2 | ||
+ | 0x4008ef6f <rtc_cmd_ext_wakeup+67>: movi a11, 1 | ||
+ | 0x4008ef72 <rtc_cmd_ext_wakeup+70>: call8 0x4008dcf0 <rtc_pads_funie> | ||
+ | 0x4008ef75 <rtc_cmd_ext_wakeup+73>: mov.n a10, a2 | ||
+ | 0x4008ef77 <rtc_cmd_ext_wakeup+75>: movi a11, 0 | ||
+ | 0x4008ef7a <rtc_cmd_ext_wakeup+78>: call8 0x4008de78 <rtc_pads_pu> | ||
+ | 0x4008ef7d <rtc_cmd_ext_wakeup+81>: mov.n a10, a2 | ||
+ | 0x4008ef7f <rtc_cmd_ext_wakeup+83>: movi.n a11, 0 | ||
+ | 0x4008ef81 <rtc_cmd_ext_wakeup+85>: call8 0x4008e000 <rtc_pads_pd> | ||
+ | |||
+ | 0x4008ef84 <rtc_cmd_ext_wakeup+88>: l32r a8, 0x4008ee90 | ||
+ | 0x4008ef87 <rtc_cmd_ext_wakeup+91>: l32r a2, 0x4008ee94 | ||
+ | 0x4008ef8a <rtc_cmd_ext_wakeup+94>: memw | ||
+ | 0x4008ef8d <rtc_cmd_ext_wakeup+97>: l32i.n a9, a8, 0 | ||
+ | 0x4008ef8f <rtc_cmd_ext_wakeup+99>: slli a3, a3, 27 | ||
+ | 0x4008ef92 <rtc_cmd_ext_wakeup+102>: and a9, a9, a2 | ||
+ | 0x4008ef95 <rtc_cmd_ext_wakeup+105>: or a3, a3, a9 | ||
+ | 0x4008ef98 <rtc_cmd_ext_wakeup+108>: l32r a2, 0x4008ee98 /* a2 = *(0x4008ee98) = 0x3ff48060, RTC_CNTL_EXT_WAKEUP_CONF_REG */ | ||
+ | 0x4008ef9b <rtc_cmd_ext_wakeup+111>: memw | ||
+ | 0x4008ef9e <rtc_cmd_ext_wakeup+114>: s32i.n a3, a8, 0 | ||
+ | 0x4008efa0 <rtc_cmd_ext_wakeup+116>: memw | ||
+ | |||
+ | /* All above is same as rtc_pad_ext_wakeup ! */ | ||
+ | |||
+ | 0x4008efa3 <rtc_cmd_ext_wakeup+119>: l32i.n a8, a2, 0 /* a8 = read RTC_CNTL_EXT_WAKEUP_CONF_REG */ | ||
+ | 0x4008efa5 <rtc_cmd_ext_wakeup+121>: l32r a3, 0x400805fc /* a3 = *(0x400805fc) = 0x40000000 */ | ||
+ | 0x4008efa8 <rtc_cmd_ext_wakeup+124>: or a3, a8, a3 /* a3 = 0x40000000 | RTC_CNTL_EXT_WAKEUP_CONF_REG, Set BIT(30) to 1 */ | ||
+ | |||
+ | /* EXT_WAKEUP0, external wake up at high level */ | ||
+ | |||
+ | 0x4008efab <rtc_cmd_ext_wakeup+127>: memw | ||
+ | 0x4008efae <rtc_cmd_ext_wakeup+130>: s32i.n a3, a2, 0 | ||
+ | 0x4008efb0 <rtc_cmd_ext_wakeup+132>: retw.n | ||
+ | </source> | ||
+ | |||
+ | So: | ||
+ | |||
+ | <source lang=c> | ||
+ | typedef enum { | ||
+ | RTC_GPIO0 = BIT(0), | ||
+ | RTC_GPIO1 = BIT(1), | ||
+ | ...... | ||
+ | ...... | ||
+ | RTC_GPIO17 = BIT(17) | ||
+ | } rtc_gpio_num_t; | ||
+ | |||
+ | /* | ||
+ | * rtc_io_num is the number of rtc_pad. e.g. The number of RTC_GPIO5 is 5 | ||
+ | */ | ||
+ | void rtc_cmd_ext_wakeup(rtc_gpio_num_t rtc_pad, uint8_t rtc_io_num); | ||
+ | </source> | ||
+ | |||
+ | <br> | ||
+ | |||
+ | ==== rtc_pad_gpio_wakeup ==== | ||
+ | |||
+ | Only available in light sleep mode | ||
+ | |||
+ | <source lang=bash> | ||
+ | 0x4008edfc <rtc_pad_gpio_wakeup>: entry a1, 32 | ||
+ | 0x4008edff <rtc_pad_gpio_wakeup+3>: mov.n a10, a2 | ||
+ | 0x4008ee01 <rtc_pad_gpio_wakeup+5>: movi.n a11, 1 | ||
+ | 0x4008ee03 <rtc_pad_gpio_wakeup+7>: call8 0x4008d2f4 <rtc_pads_muxsel> /* rtc_pads_muxsel(p1, 1) */ | ||
+ | 0x4008ee06 <rtc_pad_gpio_wakeup+10>: mov.n a10, a2 | ||
+ | 0x4008ee08 <rtc_pad_gpio_wakeup+12>: movi.n a11, 0 | ||
+ | 0x4008ee0a <rtc_pad_gpio_wakeup+14>: call8 0x4008d54c <rtc_pads_funsel> /* rtc_pad_funsel(p1, 0) */ | ||
+ | |||
+ | 0x4008ee0d <rtc_pad_gpio_wakeup+17>: l32r a8, 0x4008edf4 /* a8 = 0x3ff4840c, RTC_GPIO_ENABLE_REG */ | ||
+ | 0x4008ee10 <rtc_pad_gpio_wakeup+20>: movi.n a9, -1 /* a9 = 0xffff ffff */ | ||
+ | 0x4008ee12 <rtc_pad_gpio_wakeup+22>: memw | ||
+ | 0x4008ee15 <rtc_pad_gpio_wakeup+25>: l32i.n a10, a8, 0 /* a10 = read RTC_GPIO_ENABLE_REG */ | ||
+ | 0x4008ee17 <rtc_pad_gpio_wakeup+27>: xor a9, a9, a2 /* a9 = ~p1 = p1 ^ 0xffff ffff */ | ||
+ | 0x4008ee1a <rtc_pad_gpio_wakeup+30>: and a9, a9, a10 /* a9 = a9 & RTC_GPIO_ENABLE_REG */ | ||
+ | 0x4008ee1d <rtc_pad_gpio_wakeup+33>: memw | ||
+ | 0x4008ee20 <rtc_pad_gpio_wakeup+36>: s32i.n a9, a8, 0 | ||
+ | |||
+ | 0x4008ee22 <rtc_pad_gpio_wakeup+38>: mov.n a10, a2 | ||
+ | 0x4008ee24 <rtc_pad_gpio_wakeup+40>: movi a11, 1 | ||
+ | 0x4008ee27 <rtc_pad_gpio_wakeup+43>: call8 0x4008d794 <rtc_pads_slpsel> /* rtc_pads_slpsel(p1, 1) */ | ||
+ | 0x4008ee2a <rtc_pad_gpio_wakeup+46>: mov.n a10, a2 | ||
+ | 0x4008ee2c <rtc_pad_gpio_wakeup+48>: movi a11, 0 | ||
+ | 0x4008ee2f <rtc_pad_gpio_wakeup+51>: call8 0x4008d9dc <rtc_pads_slpoe> /* rtc_pads_slpoe(p1, 0) */ | ||
+ | 0x4008ee32 <rtc_pad_gpio_wakeup+54>: mov.n a10, a2 | ||
+ | 0x4008ee34 <rtc_pad_gpio_wakeup+56>: movi a11, 1 | ||
+ | 0x4008ee37 <rtc_pad_gpio_wakeup+59>: call8 0x4008db68 <rtc_pads_slpie> /* rtc_pads_slpie(p1, 1) */ | ||
+ | 0x4008ee3a <rtc_pad_gpio_wakeup+62>: mov.n a10, a2 | ||
+ | 0x4008ee3c <rtc_pad_gpio_wakeup+64>: movi a11, 1 | ||
+ | 0x4008ee3f <rtc_pad_gpio_wakeup+67>: call8 0x4008dcf0 <rtc_pads_funie> /* rtc_pads_funie(p1, 1) */ | ||
+ | 0x4008ee42 <rtc_pad_gpio_wakeup+70>: mov.n a10, a2 | ||
+ | 0x4008ee44 <rtc_pad_gpio_wakeup+72>: movi.n a11, 0 | ||
+ | 0x4008ee46 <rtc_pad_gpio_wakeup+74>: call8 0x4008de78 <rtc_pads_pu> /* rtc_pads_pu(p1, 0) */ | ||
+ | 0x4008ee49 <rtc_pad_gpio_wakeup+77>: mov.n a10, a2 | ||
+ | 0x4008ee4b <rtc_pad_gpio_wakeup+79>: movi.n a11, 0 | ||
+ | 0x4008ee4d <rtc_pad_gpio_wakeup+81>: call8 0x4008e000 <rtc_pads_pd> /* rtc_pads_pd(p1, 0) */ | ||
+ | |||
+ | 0x4008ee50 <rtc_pad_gpio_wakeup+84>: extui a3, a3, 0, 3 /* a3 = p2[2:0] */ | ||
+ | 0x4008ee53 <rtc_pad_gpio_wakeup+87>: l32r a8, 0x4008edf0 /* a8 = *(0x4008edf0) = 0x3ff48428, RTC_GPIO_PIN0_REG */ | ||
+ | 0x4008ee56 <rtc_pad_gpio_wakeup+90>: l32r a10, 0x4008edf8 /* a10 = *(0x4008edf8) = 0x3ff48470 */ | ||
+ | |||
+ | /* RTC_GPIO_PIN17_REG addr is 0x3ff4846c */ | ||
+ | |||
+ | 0x4008ee59 <rtc_pad_gpio_wakeup+93>: slli a14, a3, 7 /* a14 = p2[2:0] << 7 */ | ||
+ | 0x4008ee5c <rtc_pad_gpio_wakeup+96>: movi.n a9, 1 | ||
+ | 0x4008ee5e <rtc_pad_gpio_wakeup+98>: movi a13, 0x400 | ||
+ | 0x4008ee61 <rtc_pad_gpio_wakeup+101>: movi a12, 0xfffffc7f | ||
+ | 0x4008ee64 <rtc_pad_gpio_wakeup+104>: bnone a9, a2, 0x4008ee84 <rtc_pad_gpio_wakeup+136> /* branch; if (a9 & a2 == 0); */ | ||
+ | 0x4008ee67 <rtc_pad_gpio_wakeup+107>: memw | ||
+ | 0x4008ee6a <rtc_pad_gpio_wakeup+110>: l32i.n a11, a8, 0 /* a11 = read RTC_GPIO_PINx_REG */ | ||
+ | 0x4008ee6c <rtc_pad_gpio_wakeup+112>: or a11, a11, a13 /* a11 = RTC_GPIO_PINx_REG | 0x400 */ | ||
+ | 0x4008ee6f <rtc_pad_gpio_wakeup+115>: memw | ||
+ | 0x4008ee72 <rtc_pad_gpio_wakeup+118>: s32i.n a11, a8, 0 /* write to RTC_GPIO_PINx_REG */ | ||
+ | |||
+ | 0x4008ee74 <rtc_pad_gpio_wakeup+120>: memw | ||
+ | 0x4008ee77 <rtc_pad_gpio_wakeup+123>: l32i.n a11, a8, 0 /* a11 = read RTC_GPIO_PINx_REG */ | ||
+ | 0x4008ee79 <rtc_pad_gpio_wakeup+125>: and a11, a11, a12 /* a11 = RTC_GPIO_PINx_REG & 0xfffffc7f */ | ||
+ | 0x4008ee7c <rtc_pad_gpio_wakeup+128>: or a11, a11, a14 /* a11 |= (p2[2:0] << 7) */ | ||
+ | 0x4008ee7f <rtc_pad_gpio_wakeup+131>: memw | ||
+ | 0x4008ee82 <rtc_pad_gpio_wakeup+134>: s32i.n a11, a8, 0 /* write to RTC_GPIO_PIN0_REG */ | ||
+ | |||
+ | 0x4008ee84 <rtc_pad_gpio_wakeup+136>: addi.n a8, a8, 4 /* a8 = 0x3ff48428 + i*4, RTC_GPIO_PINx_REG */ | ||
+ | 0x4008ee86 <rtc_pad_gpio_wakeup+138>: slli a9, a9, 1 /* a9 <<= 1 */ | ||
+ | 0x4008ee89 <rtc_pad_gpio_wakeup+141>: bne a8, a10, 0x4008ee64 <rtc_pad_gpio_wakeup+104> /* branch; if (a8 != a10); */ | ||
+ | 0x4008ee8c <rtc_pad_gpio_wakeup+144>: retw.n | ||
+ | </source> | ||
+ | |||
+ | So: | ||
+ | |||
+ | <source lang=c> | ||
+ | typedef enum { | ||
+ | RTC_GPIO0 = BIT(0), | ||
+ | RTC_GPIO1 = BIT(1), | ||
+ | ...... | ||
+ | ...... | ||
+ | RTC_GPIO17 = BIT(17) | ||
+ | } rtc_gpio_num_t; | ||
+ | |||
+ | /* | ||
+ | * int_type: | ||
+ | * 0: GPIO interrupt disable | ||
+ | * 1: rising edge | ||
+ | * 2: falling edge trigger | ||
+ | * 3: any edge trigger | ||
+ | * 4: low level trigger | ||
+ | * 5: high level trigger | ||
+ | */ | ||
+ | void rtc_pad_gpio_wakeup(rtc_gpio_num_t rtc_pad, uint8_t int_type); | ||
+ | </source> | ||
<br> | <br> | ||
第822行: | 第1,697行: | ||
=== External Wakeup === | === External Wakeup === | ||
+ | |||
+ | Please refer to: [[ESP32 RTC External Wakeup]] | ||
<source lang=cpp> | <source lang=cpp> | ||
第916行: | 第1,793行: | ||
<br><br> | <br><br> | ||
− | == ULP | + | == ULP == |
− | + | ULP coprocessor is a simple FSM which is designed to perform measurements using ADC, temperature sensor, and external I2C sensors, while main processors are in deep sleep mode. | |
− | + | ULP coprocessor can access RTC_SLOW_MEM memory region, and registers in RTC_CNTL, RTC_IO, and SARADC peripherals. | |
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− | + | ULP coprocessor uses fixed-width 32-bit instructions, 32-bit memory addressing, and has 4 general purpose 16-bit registers. | |
− | + | More details, please refer to [[ESP32 ULP]] | |
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− | + | <br><br> | |
− | + | == Demo == | |
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− | === | + | === Smoke Detector === |
− | + | More details, please refer to: [[ESP32 Smoke Detector]] | |
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− | + | More details, please refer to: [[ESP32 Touch Pad]] | |
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2016年12月15日 (四) 11:51的最后版本
目录 |
[编辑] 1 RTC GPIO
RTC_GPIO0 ~ RTC_GPIO17
Pin NO. | Pin Name | RTC_GPIO | Control Register | MUX Bits | After Reset | Notes |
5 | SENSOR_VP | RTC_GPIO0 | RTC_IO_SENSOR_PADS_REG | SENSE1_MUX_SEL, BIT[27] | 0 (Route to digital IO_MUX) | Only Input |
6 | SENSOR_CAPP | RTC_GPIO1 | RTC_IO_SENSOR_PADS_REG | SENSE1_MUX_SEL, BIT[26] | 0 | Only Input |
7 | SENSOR_CAPN | RTC_GPIO2 | RTC_IO_SENSOR_PADS_REG | SENSE3_MUX_SEL, BIT[25] | 0 | Only Input |
8 | SENSOR_VN | RTC_GPIO3 | RTC_IO_SENSOR_PADS_REG | SENSE4_MUX_SEL, BIT[24] | 0 | Only Input |
10 | VDET_1 | RTC_GPIO4 | RTC_IO_ADC_PAD_REG | ADC1_MUX_SEL, BIT[29] | 0 | Only Input |
11 | VDET_2 | RTC_GPIO5 | RTC_IO_ADC_PAD_REG | ADC2_MUX_SEL, BIT[28] | 0 | Only Input |
12 | 32K_XP | RTC_GPIO9 | RTC_IO_XTAL_32K_PAD_REG | X32P_MUX_SEL, BIT[17] | 0 (Route to digital IO_MUX) | Set to 1 by esp-idf, route to RTC |
13 | 32K_XN | RTC_GPIO8 | RTC_IO_XTAL_32K_PAD_REG | X32N_MUX_SEL, BIT[18] | 0 (Route to digital IO_MUX) | Set to 1 by esp-idf, route to RTC |
14 | DAC_1 | RTC_GPIO6 | RTC_IO_PAD_DAC1_REG | PDAC1_MUX_SEL, BIT[17] | 0 | |
15 | DAC_2 | RTC_GPIO7 | RTC_IO_PAD_DAC2_REG | PDAC2_MUX_SEL, BIT[17] | 0 | |
16 ~ 24 | TOUCH7 ~ TOUCH0 | RTC_GPIO17 ~ 10 | TOUCH_PADn_REG (n = 7 ~ 0) | PADn_TO_GPIO, BIT[19] | 0 (Route to RTC domain) | |
You need to clear the following bits if you want to use the GPIO32 and GPIO33 as the general GPIO:
REG_CLR_BIT(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_MUX_SEL); /* gpio32 route to digital io_mux */ REG_CLR_BIT(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL); /* gpio33 route to digital io_mux */
[编辑] 2 Register
[编辑] 2.1 RTC IO
components/esp32/include/soc/rtc_io_reg.h
#define DR_REG_RTCIO_BASE 0x3ff48400 #define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) #define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) #define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) #define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc) #define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) #define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) #define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) #define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c) #define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) #define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) #define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) #define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c) #define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) #define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) #define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) #define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c) #define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) #define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) #define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) #define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c) #define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) #define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) #define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) #define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c) #define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) #define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) #define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) #define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c) #define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x70) #define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74) #define RTC_IO_HALL_SENS_REG (DR_REG_RTCIO_BASE + 0x78) #define RTC_IO_SENSOR_PADS_REG (DR_REG_RTCIO_BASE + 0x7c) #define RTC_IO_ADC_PAD_REG (DR_REG_RTCIO_BASE + 0x80) #define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x84) #define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x88) #define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) #define RTC_IO_TOUCH_CFG_REG (DR_REG_RTCIO_BASE + 0x90) #define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x94) #define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x98) #define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c) #define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0) #define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4) #define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8) #define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac) #define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0) #define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4) #define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xb8) #define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc) #define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0) #define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xc4) #define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0xc8)
[编辑] 2.2 RTC Ctrl
components/esp32/include/soc/rtc_cntl_reg.h
/************************************************************************************** * Note: * * Some Rtc memory and registers are used, in ROM or in internal library. * * Please do not use reserved or used rtc memory or registers. * * * ************************************************************************************* * RTC Memory & Store Register usage ************************************************************************************* * rtc memory addr type size usage * 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry * 0x3ff61000+SIZE_CP Slow 4096-SIZE_CP * 0x3ff62800 Slow 4096 Reserved * * 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code * ************************************************************************************* * Rtc store registers usage * RTC_CNTL_STORE0_REG * RTC_CNTL_STORE1_REG * RTC_CNTL_STORE2_REG * RTC_CNTL_STORE3_REG * RTC_CNTL_STORE4_REG Reserved * RTC_CNTL_STORE5_REG External Xtal Frequency * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC ************************************************************************************* */ #define DR_REG_RTCCNTL_BASE 0x3ff48000 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) #define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10) #define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14) #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) #define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) #define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) #define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30) #define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x34) #define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) #define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x3c) #define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x40) #define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x44) #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48) #define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x4c) #define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50) #define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x54) #define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x58) #define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) #define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) #define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) #define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) #define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) #define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) #define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) #define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) #define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) #define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) #define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x94) #define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x98) #define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x9c) #define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa0) #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xa4) #define RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0xa8) #define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xac) #define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0) #define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4) #define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xb8) #define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xbc) #define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xc0) #define RTC_CNTL_DIAG1_REG (DR_REG_RTCCNTL_BASE + 0xc4) #define RTC_CNTL_HOLD_FORCE_REG (DR_REG_RTCCNTL_BASE + 0xc8) #define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) #define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) #define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xd4) #define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4) #define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4) #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c)
[编辑] 3 Memory
[编辑] 3.1 FAST Memory
RTC FAST Memory 为 8 KB SRAM,其只能被 PRO_CPU 通过数据总线 0x3FF8_0000 ~ 0x3FF8_1FFF 读写,或被 PRO_CPU 通过指令总线 0x400C_0000~0x400C_1FFF 读写。与其他存储器不同,APP_CPU 不能访问 RTC FAST Memory
PRO_CPU 的这两段地址同序访问 RTC FAST Memory。即地址 0x3FF8_0000 与 0x400C_0000 访问到相同的 word,0x3FF8_0004与0x400C_0004访问到相同的word,0x3FF8_0008与0x400C_0008访问到相同的word, 以此类推。APP_CPU 的这两段地址不能访问到 RTC FAST Memory,也不能访问到其他任何目标
[编辑] 3.2 SLOW Memory
RTC SLOW Memory 为 8 KB SRAM,其可以被两个 CPU 通过数据总线与指令总线共用地址段 0x5000_0000 ~ 0x5000_1FFF 读写。
[编辑] 4 Power Consumption
Light Sleep Mode:
- The CPU is paused
- WiFi/BT base-band and radio are Off
- The RTC and ULP are running
- Any wake-up events (MAC, host, RTC timer, or external interrupts) will wake up the chip
- Current consumption is 800uA
We are care of Deep-Sleep mode:
- The ULP co-porcessor is powered on: 150uA current consumption
- ULP sensor-monitored pattern: 25uA @ 1% duty
- RTC timer + RTC memory: 10uA
And Hibernate Mode:
- The internal 8MHz oscillator and ULP coprocessor are disabled
- The RTC recovery memory are power-down
- Only one RTC timer on the slow clock and some RTC GPIOs are active.
- The RTC timer or the RTC GPIOs can wake up the chip from the Hibernation mode
- Power Consumption: 2.5uA
[编辑] 4.1 Registers
#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ /*description: RTC_REG force power up*/ #define RTC_CNTL_FORCE_PU_S 31 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ /*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ #define RTC_CNTL_FORCE_PD_S 30 /* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ /*description: RTC_DBOOST force power up*/ #define RTC_CNTL_DBOOST_FORCE_PU_S 29 /* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ /*description: RTC_DBOOST force power down*/ #define RTC_CNTL_DBOOST_FORCE_PD_S 28 /* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ /*description: RTC_DBIAS during wakeup*/ #define RTC_CNTL_DBIAS_WAK_S 25 /* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ /*description: RTC_DBIAS during sleep*/ #define RTC_CNTL_DBIAS_SLP_S 22 /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ /*description: SCK_DCAP*/ #define RTC_CNTL_SCK_DCAP_S 14 /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ /*description: DIG_REG_DBIAS during wakeup*/ #define RTC_CNTL_DIG_DBIAS_WAK_S 11 /* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */ /*description: DIG_REG_DBIAS during sleep*/ #define RTC_CNTL_DIG_DBIAS_SLP_S 8 /* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */ /*description: N/A*/ #define RTC_CNTL_SCK_DCAP_FORCE_S 7 #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ /*description: enable power down rtc_peri in sleep*/ #define RTC_CNTL_PD_EN_S 20 /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ /*description: rtc_peri force power up*/ #define RTC_CNTL_PWC_FORCE_PU_S 19 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ /*description: rtc_peri force power down*/ #define RTC_CNTL_PWC_FORCE_PD_S 18 /* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ /*description: enable power down RTC memory in sleep*/ #define RTC_CNTL_SLOWMEM_PD_EN_S 17 /* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ /*description: RTC memory force power up*/ #define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 /* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ /*description: RTC memory force power down*/ #define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 /* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ /*description: enable power down fast RTC memory in sleep*/ #define RTC_CNTL_FASTMEM_PD_EN_S 14 /* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ /*description: Fast RTC memory force power up*/ #define RTC_CNTL_FASTMEM_FORCE_PU_S 13 /* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: Fast RTC memory force power down*/ #define RTC_CNTL_FASTMEM_FORCE_PD_S 12 /* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ /*description: RTC memory force no PD*/ #define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 /* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ /*description: RTC memory force PD*/ #define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 /* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ /*description: 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ #define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 /* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ /*description: Fast RTC memory force no PD*/ #define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 /* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ /*description: Fast RTC memory force PD*/ #define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 /* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ /*description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC state machine*/ #define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 /* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ /*description: rtc_peri force no ISO*/ #define RTC_CNTL_FORCE_NOISO_S 5 /* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ /*description: rtc_peri force ISO*/ #define RTC_CNTL_FORCE_ISO_S 4 /* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: RTC memory force ISO*/ #define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 /* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ /*description: RTC memory force no ISO*/ #define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 /* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ /*description: Fast RTC memory force ISO*/ #define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 /* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: Fast RTC memory force no ISO*/ #define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0
[编辑] 5 Clock
The RTC clock has five possible sources:
- External low speed (32 KHz) crystal clock
- External crystal clock divided by 4 (40MHz/4 ?)
- Internal RC oscillator (typically about 150 KHz and adjustable)
- Internal 8 MHz oscillator
- Internal 31.25KHz clock (derived from the internal 8MHz oscillator divided by 256)
[编辑] 5.1 API
[编辑] 5.1.1 rtc_set_fast_freq
0x4008f87c <rtc_set_fast_freq>: entry a1, 32 0x4008f87f <rtc_set_fast_freq+3>: l32r a8, 0x4008e53c /* a8 = *(0x4008e53c) = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */ 0x4008f882 <rtc_set_fast_freq+6>: l32r a11, 0x40086318 /* a11 = *(0x40086318) = 0xdfffffff, BIT(29), fast_clk_rtc sel */ 0x4008f885 <rtc_set_fast_freq+9>: memw 0x4008f888 <rtc_set_fast_freq+12>: l32i.n a9, a8, 0 /* a9 = read RTC_CNTL_CLK_CONF_REG */ 0x4008f88a <rtc_set_fast_freq+14>: extui a2, a2, 0, 1 /* a2 = p1[0] */ 0x4008f88d <rtc_set_fast_freq+17>: slli a10, a2, 29 /* a10 = p1[0] << 29 */ 0x4008f890 <rtc_set_fast_freq+20>: and a9, a9, a11 0x4008f893 <rtc_set_fast_freq+23>: or a9, a10, a9 /* a9 = RTC_CNTL_CLK_CONF_REG & 0xdfffffff | (p1[0] << 29) 0x4008f896 <rtc_set_fast_freq+26>: memw 0x4008f899 <rtc_set_fast_freq+29>: s32i.n a9, a8, 0 /* write to RTC_CNTL_CLK_CONF_REG */ /* fast_clk_rtc sel. 0: XTAL div 4 1: CK8M */ 0x4008f89b <rtc_set_fast_freq+31>: movi a10, 3 0x4008f89e <rtc_set_fast_freq+34>: l32r a8, 0x40080850 /* a8 = *(0x40080850) = 0x40008534, ets_delay_us */ 0x4008f8a1 <rtc_set_fast_freq+37>: callx8 a8 /* ets_delay_us(3) */ 0x4008f8a4 <rtc_set_fast_freq+40>: retw.n
So:
/* * fast_clk_rtc_sel = 0: XTAL div 4 * fast_clk_rtc_sel = 1: CK8M */ void rtc_set_fast_freq(uint8_t fast_clk_rtc_sel);
[编辑] 5.1.2 rtc_set_slow_freq
0x4008f854 <rtc_set_slow_freq>: entry a1, 32 0x4008f857 <rtc_set_slow_freq+3>: l32r a8, 0x4008e53c /* a8 = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */ 0x4008f85a <rtc_set_slow_freq+6>: l32r a10, 0x4008af18 /* a10 = 0x3fffffff, BIT[31:30] */ 0x4008f85d <rtc_set_slow_freq+9>: memw 0x4008f860 <rtc_set_slow_freq+12>: l32i.n a9, a8, 0 0x4008f862 <rtc_set_slow_freq+14>: slli a2, a2, 30 0x4008f865 <rtc_set_slow_freq+17>: and a9, a9, a10 0x4008f868 <rtc_set_slow_freq+20>: or a9, a2, a9 0x4008f86b <rtc_set_slow_freq+23>: memw 0x4008f86e <rtc_set_slow_freq+26>: s32i.n a9, a8, 0 0x4008f870 <rtc_set_slow_freq+28>: movi a10, 0x12c /* a10 = 300 */ 0x4008f873 <rtc_set_slow_freq+31>: l32r a8, 0x40080850 0x4008f876 <rtc_set_slow_freq+34>: callx8 a8 /* ets_delay_us(300) */ 0x4008f879 <rtc_set_slow_freq+37>: retw.n
So:
/* * slow_clk_rtc_sel = 0: SLOW_CK * slow_clk_rtc_sel = 1: CK_XTAL_32K * slow_clk_rtc_sel = 2: CK8M_D256_OUT */ void rtc_set_slow_freq(uint8_t slow_clk_rtc_sel);
[编辑] 5.1.3 rtc_xtal_32k_ena
void rtc_xtal_32k_ena(uint8_t enabled);
more details please refer to: RTC XTAL 32K enable
[编辑] 5.1.4 rtc_init_clk_lite
void rtc_init_clk_lite(uint32_t st) { rtc_init_clk(st, 1, 0, 0, 255, 172); }
More details please refer to: RTC Init Clock Lite
[编辑] 5.1.5 rtc_init_clk
void rtc_init_clk(uint32_t st, uint8_t fast_clk_sel, uint8_t ck8m_divider, uint8_t slow_clk_sel,uint8_t sck_dcap,uint8_t ck8_dfreq); rtc_init_clk(0, 1, 0, 0, 255, 172);
More details please refer to: RTC Init Clock
[编辑] 5.2 Register
#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ /*description: slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ #define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ /*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ #define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 /* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ /*description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ #define RTC_CNTL_SOC_CLK_SEL_S 27 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ /*description: CK8M force power up*/ #define RTC_CNTL_CK8M_FORCE_PU_S 26 /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ /*description: CK8M force power down*/ #define RTC_CNTL_CK8M_FORCE_PD_S 25 /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */ /*description: CK8M_DFREQ*/ #define RTC_CNTL_CK8M_DFREQ_S 17 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ /*description: CK8M force no gating during sleep*/ #define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ /*description: XTAL force no gating during sleep*/ #define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */ /*description: divider = reg_ck8m_div_sel + 1*/ #define RTC_CNTL_CK8M_DIV_SEL_S 12 /* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */ /*description: */ #define RTC_CNTL_CK8M_DFREQ_FORCE_S 11 /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ /*description: enable CK8M for digital core (no relationship with RTC core)*/ #define RTC_CNTL_DIG_CLK8M_EN_S 10 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ #define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ #define RTC_CNTL_DIG_XTAL32K_EN_S 8 /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ /*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ #define RTC_CNTL_ENB_CK8M_DIV_S 7 /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ /*description: disable CK8M and CK8M_D256_OUT*/ #define RTC_CNTL_ENB_CK8M_S 6 /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ /*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ #define RTC_CNTL_CK8M_DIV_S 4 #define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) /* e.g. 0x84160018 */ /* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */ /*description: Power up 32kHz crystal oscillator*/ #define RTC_IO_XPD_XTAL_32K_S 19 /* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */ /*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ #define RTC_IO_X32N_MUX_SEL_S 18 /* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ /*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ #define RTC_IO_X32P_MUX_SEL_S 17 /* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ /*description: the functional selection signal of the pad*/ #define RTC_IO_X32N_FUN_SEL_S 15 /* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ /*description: the functional selection signal of the pad*/ #define RTC_IO_X32P_FUN_SEL_S 9
[编辑] 6 API
#define DEEP_SLEEP_PD_NORMAL BIT(0) /* Base deep sleep mode */ #define DEEP_SLEEP_PD_RTC_PERIPH BIT(1) /* Power down RTC peripherals */ #define DEEP_SLEEP_PD_RTC_SLOW_MEM BIT(2) /* Power down RTC SLOW memory */ #define DEEP_SLEEP_PD_RTC_FAST_MEM BIT(3) /* Power down RTC FAST memory */ /* * @brief Prepare for entering sleep mode * @param deep_slp DEEP_SLEEP_PD_ flags combined with OR (DEEP_SLEEP_PD_NORMAL must be included) * @param cpu_lp_mode for deep sleep, should be 0 */ void rtc_slp_prep_lite(uint32_t deep_slp, uint32_t cpu_lp_mode); #define RTC_EXT_EVENT0_TRIG BIT(0) #define RTC_EXT_EVENT1_TRIG BIT(1) #define RTC_GPIO_TRIG BIT(2) /* Only available in light sleep */ #define RTC_TIMER_EXPIRE BIT(3) #define RTC_SDIO_TRIG BIT(4) #define RTC_MAC_TRIG BIT(5) #define RTC_UART0_TRIG BIT(6) #define RTC_UART1_TRIG BIT(7) #define RTC_TOUCH_TRIG BIT(8) #define RTC_SAR_TRIG BIT(9) #define RTC_BT_TRIG BIT(10) /* * @brief Enter sleep mode for given number of cycles * @param cycles_h higher 32 bit part of number of slow clock cycles * @param cycles_l lower 32 bit part of number of slow clock cycles * @param wakeup_opt wake up reason to enable (RTC_xxx_TRIG flags combined with OR) * @param reject_opt reserved, should be 0 * @return TBD */ uint32_t rtc_sleep(uint32_t cycles_h, uint32_t cycles_l, uint32_t wakeup_opt, uint32_t reject_opt);
[编辑] 6.1 rtc_sleep_prep
(gdb) x /345i rtc_slp_prep
More details: ESP32 RTC Sleep Prepare
[编辑] 6.2 rtc_sleep
0x4009011c <rtc_sleep>: entry a1, 32 0x4009011f <rtc_sleep+3>: l32r a9, 0x4008ff08 /* a9 = *(0x4008ff08) = 0x3ff4800c */ 0x40090122 <rtc_sleep+6>: l32r a11, 0x4008073c /* a11 = *(0x4008073c) = 0x80000000 */ 0x40090125 <rtc_sleep+9>: memw 0x40090128 <rtc_sleep+12>: l32i.n a8, a9, 0 /* a8 = *(0x3ff4800c) = 0x40000000 */ 0x4009012a <rtc_sleep+14>: l32r a10, 0x40080630 /* a10 = *(0x40080630) = 0x40000000 */ 0x4009012d <rtc_sleep+17>: or a8, a8, a11 0x40090130 <rtc_sleep+20>: memw 0x40090133 <rtc_sleep+23>: s32i.n a8, a9, 0 /* *(0x3ff4800c) = 0xC0000000 */ 0x40090135 <rtc_sleep+25>: memw 0x40090138 <rtc_sleep+28>: l32i.n a8, a9, 0 /* a8 = 0xC0000000 */ 0x4009013a <rtc_sleep+30>: bnone a8, a10, 0x40090135 /* if (a8 & a19 == 0) branch */ 0x4009013d <rtc_sleep+33>: l32r a10, 0x4008ff0c /* a10 = *(0x4008ff0c) = 0x3ff48048, RTC_CNTL_INT_CLR_REG */ 0x40090140 <rtc_sleep+36>: movi.n a8, 16 /* a8 = 16 = 0x10 */ 0x40090142 <rtc_sleep+38>: memw 0x40090145 <rtc_sleep+41>: l32i.n a9, a10, 0 /* a9 = *(0x3ff48048) = 0x0 */ 0x40090147 <rtc_sleep+43>: or a8, a9, a8 /* Clear RTC time valid interrupt state */ 0x4009014a <rtc_sleep+46>: memw 0x4009014d <rtc_sleep+49>: s32i.n a8, a10, 0 /* update to *(0x3ff48048), RTC_CNTL_INT_CLR_REG */ 0x4009014f <rtc_sleep+51>: l32r a8, 0x4008ff10 /* a8 = *(0x4008ff10) = 0x3ff48010 RTC_CNTL_TIME0_REG */ 0x40090152 <rtc_sleep+54>: l32r a9, 0x4008ff14 /* a9 = *(0x4008ff14) = 0x3ff48014 RTC_CNTL_TIME1_REG */ 0x40090155 <rtc_sleep+57>: memw 0x40090158 <rtc_sleep+60>: l32i.n a8, a8, 0 /* a8 = *(0x3ff48010) = 0x000124ee, time0 value */ 0x4009015a <rtc_sleep+62>: memw 0x4009015d <rtc_sleep+65>: l32i.n a12, a9, 0 /* a12 = *(0x3ff48014) = 0x0, time1 value */ 0x4009015f <rtc_sleep+67>: add.n a8, a3, a8 /* a8 += 2nd_param, 2nd_param is cycles_l */ 0x40090161 <rtc_sleep+69>: movi.n a9, 1 /* a9 = 1 */ 0x40090163 <rtc_sleep+71>: bltu a8, a3, 0x40090169 /* if (a8 < a3); branch */ 0x40090166 <rtc_sleep+74>: movi a9, 0 /* a9 = 0 */ 0x40090169 <rtc_sleep+77>: l32r a3, 0x4008ff64 /* a3 = *(0x4008ff64) = 0x3ff48004, RTC_CNTL_SLP_TIME0_REG */ 0x4009016c <rtc_sleep+80>: add.n a2, a2, a12 /* a2 = 1st_param_cycles_h + a12 */ 0x4009016e <rtc_sleep+82>: memw 0x40090171 <rtc_sleep+85>: s32i.n a8, a3, 0 /* update a8 into RTC_CNTL_SLP_TIME0_REG */ 0x40090173 <rtc_sleep+87>: l32r a8, 0x4008ff68 /* a8 = *(0x4008ff68) = 0x3ff48008, RTC_CNTL_SLP_TIME1_REG */ 0x40090176 <rtc_sleep+90>: l32r a3, 0x4008ff84 /* a3 = *(0x4008ff84) = 0x3ff48038, RTC_CNTL_WAKEUP_STATE_REG */ 0x40090179 <rtc_sleep+93>: add.n a9, a9, a2 /* a9 += a2, time1_val + cycles_h */ 0x4009017b <rtc_sleep+95>: memw 0x4009017e <rtc_sleep+98>: s32i.n a9, a8, 0 /* update a9 into RTC_CNTL_SLP_TIME1_REG */ 0x40090180 <rtc_sleep+100>: memw 0x40090183 <rtc_sleep+103>: l32i.n a8, a3, 0 /* a8 = *(0x3ff48038) = 0x00006000, read RTC_CNTL_WAKEUP_STATE_REG */ 0x40090185 <rtc_sleep+105>: l32r a2, 0x4008d188 /* a2 = *(0x4008d188) = 0xffc007ff */ 0x40090188 <rtc_sleep+108>: extui a4, a4, 0, 11 /* a4 is the 3rd param, extract the low 11 bits */ 0x4009018b <rtc_sleep+111>: and a2, a8, a2 /* a2 = RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff (only bitpos:[21:11]) */ 0x4009018e <rtc_sleep+114>: slli a4, a4, 11 /* a4 <<= 11 */ 0x40090191 <rtc_sleep+117>: or a4, a4, a2 /* a4 = wakeup_opt | (RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff) */ 0x40090194 <rtc_sleep+120>: l32r a2, 0x4008ff88 /* a2 = *(0x4008ff88) = 0x3ff48064, RTC_CNTL_SLP_REJECT_CONF_REG */ 0x40090197 <rtc_sleep+123>: memw 0x4009019a <rtc_sleep+126>: s32i.n a4, a3, 0 /* update the a4 into RTC_CNTL_WAKEUP_STATE_REG */ 0x4009019c <rtc_sleep+128>: l32r a3, 0x4008d1f0 /* a3 = *(0x4008d1f0) = 0x3ff48018, RTC_CNTL_STATE0_REG */ 0x4009019f <rtc_sleep+131>: memw 0x400901a2 <rtc_sleep+134>: s32i.n a5, a2, 0 /* update the a5 (4th param) into RTC_CNTL_SLP_REJECT_CONF_REG directly */ 0x400901a4 <rtc_sleep+136>: memw 0x400901a7 <rtc_sleep+139>: l32i.n a2, a3, 0 /* a2 = *(0x3ff48018) = 0x20300000, read RTC_CNTL_STATE0_REG */ 0x400901a9 <rtc_sleep+141>: l32r a9, 0x4008ffb8 /* a9 = *(0x4008ffb8) = 0x3ff48040, RTC_CNTL_INT_RAW_REG */ 0x400901ac <rtc_sleep+144>: or a11, a2, a11 /* a11 = RTC_CNTL_STATE0_REG | 0x8000 0000 */ 0x400901af <rtc_sleep+147>: memw 0x400901b2 <rtc_sleep+150>: s32i.n a11, a3, 0 /* update a11 into RTC_CNTL_STATE0_REG */ 0x400901b4 <rtc_sleep+152>: memw 0x400901b7 <rtc_sleep+155>: l32i.n a8, a9, 0 /* a8 = *(0x3ff48040) = 0x0000 0014, read RTC_CNTL_INT_RAW_REG */ 0x400901b9 <rtc_sleep+157>: extui a8, a8, 0, 2 /* a8 = extract the low 2 bits of a8 */ 0x400901bc <rtc_sleep+160>: beqz a8, 0x400901b4 /* if (a8 == 0); branch */ 0x400901bf <rtc_sleep+163>: memw 0x400901c2 <rtc_sleep+166>: l32i.n a2, a9, 0 /* a2 = *(0x3ff48040) = 0x0000 0014, read RTC_CNTL_INT_RAW_REG */ 0x400901c4 <rtc_sleep+168>: memw 0x400901c7 <rtc_sleep+171>: l32i.n a4, a10, 0 /* a4 = *(0x3ff48048) = 0x0, read RTC_CNTL_INT_CLR_REG */ 0x400901c9 <rtc_sleep+173>: movi.n a3, 3 /* a3 = 3 */ 0x400901cb <rtc_sleep+175>: or a3, a4, a3 /* a3 |= a4, set the clear bit of the reject_int and wakeup_int */ 0x400901ce <rtc_sleep+178>: memw 0x400901d1 <rtc_sleep+181>: s32i.n a3, a10, 0 /* update the a3 into RTC_CNTL_INT_CLR_REG */ 0x400901d3 <rtc_sleep+183>: extui a2, a2, 1, 1 /* a2 = (a2 >> 1) & 0x1, return a2 */ 0x400901d6 <rtc_sleep+186>: retw.n
[编辑] 6.3 Undocumented
[编辑] 6.3.1 rtc_pads_muxsel
Set the pad route to the digital IO_MUX (0) or RTC block (1)
0x4008d1a8 <rtc_pads_muxsel>: entry a1, 32 0x4008d1ab <rtc_pads_muxsel+3>: bbci a2, 0, 0x4008d1cc <rtc_pads_muxsel+36> 0x4008d1ae <rtc_pads_muxsel+6>: l32r a8, 0x4008c9b4 0x4008d1b1 <rtc_pads_muxsel+9>: l32r a9, 0x40084bc0 /* a9 = *(0x40084bc0) = 0xf7ffffff, BIT(27) */ 0x4008d1b4 <rtc_pads_muxsel+12>: memw 0x4008d1b7 <rtc_pads_muxsel+15>: l32i a11, a8, 0 0x4008d1ba <rtc_pads_muxsel+18>: extui a10, a3, 0, 1 0x4008d1bd <rtc_pads_muxsel+21>: slli a10, a10, 27 0x4008d1c0 <rtc_pads_muxsel+24>: and a9, a11, a9 0x4008d1c3 <rtc_pads_muxsel+27>: or a9, a10, a9 0x4008d1c6 <rtc_pads_muxsel+30>: memw 0x4008d1c9 <rtc_pads_muxsel+33>: s32i a9, a8, 0 0x4008d1cc <rtc_pads_muxsel+36>: bbci a2, 1, 0x4008d1ed <rtc_pads_muxsel+69> 0x4008d1cf <rtc_pads_muxsel+39>: l32r a8, 0x4008c9b4 0x4008d1d2 <rtc_pads_muxsel+42>: l32r a9, 0x4008bebc 0x4008d1d5 <rtc_pads_muxsel+45>: memw 0x4008d1d8 <rtc_pads_muxsel+48>: l32i a11, a8, 0 0x4008d1db <rtc_pads_muxsel+51>: extui a10, a3, 0, 1 0x4008d1de <rtc_pads_muxsel+54>: slli a10, a10, 26 0x4008d1e1 <rtc_pads_muxsel+57>: and a9, a11, a9 0x4008d1e4 <rtc_pads_muxsel+60>: or a9, a10, a9 0x4008d1e7 <rtc_pads_muxsel+63>: memw 0x4008d1ea <rtc_pads_muxsel+66>: s32i a9, a8, 0 0x4008d1ed <rtc_pads_muxsel+69>: bbci a2, 2, 0x4008d20d <rtc_pads_muxsel+101> 0x4008d1f0 <rtc_pads_muxsel+72>: l32r a8, 0x4008c9b4 0x4008d1f3 <rtc_pads_muxsel+75>: l32r a9, 0x40085f20 0x4008d1f6 <rtc_pads_muxsel+78>: memw 0x4008d1f9 <rtc_pads_muxsel+81>: l32i.n a11, a8, 0 0x4008d1fb <rtc_pads_muxsel+83>: extui a10, a3, 0, 1 0x4008d1fe <rtc_pads_muxsel+86>: slli a10, a10, 25 0x4008d201 <rtc_pads_muxsel+89>: and a9, a11, a9 0x4008d204 <rtc_pads_muxsel+92>: or a9, a10, a9 0x4008d207 <rtc_pads_muxsel+95>: memw 0x4008d20a <rtc_pads_muxsel+98>: s32i a9, a8, 0 0x4008d20d <rtc_pads_muxsel+101>: bbci a2, 3, 0x4008d22d <rtc_pads_muxsel+133> 0x4008d210 <rtc_pads_muxsel+104>: l32r a8, 0x4008c9b4 0x4008d213 <rtc_pads_muxsel+107>: l32r a9, 0x4008beb4 0x4008d216 <rtc_pads_muxsel+110>: memw 0x4008d219 <rtc_pads_muxsel+113>: l32i.n a11, a8, 0 0x4008d21b <rtc_pads_muxsel+115>: extui a10, a3, 0, 1 0x4008d21e <rtc_pads_muxsel+118>: slli a10, a10, 24 0x4008d221 <rtc_pads_muxsel+121>: and a9, a11, a9 0x4008d224 <rtc_pads_muxsel+124>: or a9, a10, a9 0x4008d227 <rtc_pads_muxsel+127>: memw 0x4008d22a <rtc_pads_muxsel+130>: s32i a9, a8, 0 0x4008d22d <rtc_pads_muxsel+133>: bbci a2, 4, 0x4008d24d <rtc_pads_muxsel+165> 0x4008d230 <rtc_pads_muxsel+136>: l32r a8, 0x4008c9c8 0x4008d233 <rtc_pads_muxsel+139>: l32r a9, 0x4008620c 0x4008d236 <rtc_pads_muxsel+142>: memw 0x4008d239 <rtc_pads_muxsel+145>: l32i.n a11, a8, 0 0x4008d23b <rtc_pads_muxsel+147>: extui a10, a3, 0, 1 0x4008d23e <rtc_pads_muxsel+150>: slli a10, a10, 29 0x4008d241 <rtc_pads_muxsel+153>: and a9, a11, a9 0x4008d244 <rtc_pads_muxsel+156>: or a9, a10, a9 0x4008d247 <rtc_pads_muxsel+159>: memw 0x4008d24a <rtc_pads_muxsel+162>: s32i a9, a8, 0 0x4008d24d <rtc_pads_muxsel+165>: bbci a2, 5, 0x4008d26d <rtc_pads_muxsel+197> 0x4008d250 <rtc_pads_muxsel+168>: l32r a8, 0x4008c9c8 0x4008d253 <rtc_pads_muxsel+171>: l32r a9, 0x40087110 0x4008d256 <rtc_pads_muxsel+174>: memw 0x4008d259 <rtc_pads_muxsel+177>: l32i.n a11, a8, 0 0x4008d25b <rtc_pads_muxsel+179>: extui a10, a3, 0, 1 0x4008d25e <rtc_pads_muxsel+182>: slli a10, a10, 28 0x4008d261 <rtc_pads_muxsel+185>: and a9, a11, a9 0x4008d264 <rtc_pads_muxsel+188>: or a9, a10, a9 0x4008d267 <rtc_pads_muxsel+191>: memw 0x4008d26a <rtc_pads_muxsel+194>: s32i a9, a8, 0 0x4008d26d <rtc_pads_muxsel+197>: bbci a2, 6, 0x4008d28d <rtc_pads_muxsel+229> 0x4008d270 <rtc_pads_muxsel+200>: l32r a8, 0x4008bfa4 0x4008d273 <rtc_pads_muxsel+203>: l32r a9, 0x400854d4 0x4008d276 <rtc_pads_muxsel+206>: memw 0x4008d279 <rtc_pads_muxsel+209>: l32i.n a11, a8, 0 0x4008d27b <rtc_pads_muxsel+211>: extui a10, a3, 0, 1 0x4008d27e <rtc_pads_muxsel+214>: slli a10, a10, 17 0x4008d281 <rtc_pads_muxsel+217>: and a9, a11, a9 0x4008d284 <rtc_pads_muxsel+220>: or a9, a10, a9 0x4008d287 <rtc_pads_muxsel+223>: memw 0x4008d28a <rtc_pads_muxsel+226>: s32i a9, a8, 0 0x4008d28d <rtc_pads_muxsel+229>: bbci a2, 7, 0x4008d2ad <rtc_pads_muxsel+261> 0x4008d290 <rtc_pads_muxsel+232>: l32r a8, 0x4008bfb0 ...... ......
typedef enum { RTC_GPIO0 = BIT(0), RTC_GPIO1 = BIT(1), ...... ...... RTC_GPIO17 = BIT(17) } rtc_gpio_num_t; /* * set == 0, route to digital IO_MUX * set == 1, route to RTC block */ void rtc_pads_muxsel(rtc_gpio_num_t rtc_gpio_num, uint8_t sel);
[编辑] 6.3.2 rtc_pads_funsel
Select the RTC function for this pad.
0x4008d400 <rtc_pads_funsel>: entry a1, 32 0x4008d403 <rtc_pads_funsel+3>: bbci a2, 0, 0x4008d424 <rtc_pads_funsel+36> 0x4008d406 <rtc_pads_funsel+6>: l32r a8, 0x4008c9b4 0x4008d409 <rtc_pads_funsel+9>: l32r a9, 0x4008bfac 0x4008d40c <rtc_pads_funsel+12>: memw 0x4008d40f <rtc_pads_funsel+15>: l32i a11, a8, 0 0x4008d412 <rtc_pads_funsel+18>: extui a10, a3, 0, 2 0x4008d415 <rtc_pads_funsel+21>: slli a10, a10, 22 0x4008d418 <rtc_pads_funsel+24>: and a9, a11, a9 0x4008d41b <rtc_pads_funsel+27>: or a9, a10, a9 0x4008d41e <rtc_pads_funsel+30>: memw 0x4008d421 <rtc_pads_funsel+33>: s32i a9, a8, 0 0x4008d424 <rtc_pads_funsel+36>: bbci a2, 1, 0x4008d445 <rtc_pads_funsel+69> 0x4008d427 <rtc_pads_funsel+39>: l32r a8, 0x4008c9b4 0x4008d42a <rtc_pads_funsel+42>: l32r a9, 0x4008d3f0 0x4008d42d <rtc_pads_funsel+45>: memw 0x4008d430 <rtc_pads_funsel+48>: l32i a11, a8, 0 0x4008d433 <rtc_pads_funsel+51>: extui a10, a3, 0, 2 0x4008d436 <rtc_pads_funsel+54>: slli a10, a10, 17 0x4008d439 <rtc_pads_funsel+57>: and a9, a11, a9 0x4008d43c <rtc_pads_funsel+60>: or a9, a10, a9 0x4008d43f <rtc_pads_funsel+63>: memw 0x4008d442 <rtc_pads_funsel+66>: s32i a9, a8, 0 0x4008d445 <rtc_pads_funsel+69>: bbci a2, 2, 0x4008d465 <rtc_pads_funsel+101> 0x4008d448 <rtc_pads_funsel+72>: l32r a8, 0x4008c9b4 0x4008d44b <rtc_pads_funsel+75>: l32r a9, 0x4008c274 0x4008d44e <rtc_pads_funsel+78>: memw 0x4008d451 <rtc_pads_funsel+81>: l32i.n a11, a8, 0 0x4008d453 <rtc_pads_funsel+83>: extui a10, a3, 0, 2 0x4008d456 <rtc_pads_funsel+86>: slli a10, a10, 12 0x4008d459 <rtc_pads_funsel+89>: and a9, a11, a9 0x4008d45c <rtc_pads_funsel+92>: or a9, a10, a9 0x4008d45f <rtc_pads_funsel+95>: memw 0x4008d462 <rtc_pads_funsel+98>: s32i a9, a8, 0 0x4008d465 <rtc_pads_funsel+101>: bbci a2, 3, 0x4008d485 <rtc_pads_funsel+133> 0x4008d468 <rtc_pads_funsel+104>: l32r a8, 0x4008c9b4 0x4008d46b <rtc_pads_funsel+107>: extui a10, a3, 0, 2 0x4008d46e <rtc_pads_funsel+110>: memw 0x4008d471 <rtc_pads_funsel+113>: l32i.n a11, a8, 0 0x4008d473 <rtc_pads_funsel+115>: movi a9, 0xfffffe7f 0x4008d476 <rtc_pads_funsel+118>: slli a10, a10, 7 0x4008d479 <rtc_pads_funsel+121>: and a9, a11, a9 0x4008d47c <rtc_pads_funsel+124>: or a9, a10, a9 0x4008d47f <rtc_pads_funsel+127>: memw 0x4008d482 <rtc_pads_funsel+130>: s32i a9, a8, 0 0x4008d485 <rtc_pads_funsel+133>: bbci a2, 4, 0x4008d4a5 <rtc_pads_funsel+165> 0x4008d488 <rtc_pads_funsel+136>: l32r a8, 0x4008c9c8 ...... ......
typedef enum { RTC_GPIO0 = BIT(0), RTC_GPIO1 = BIT(1), ...... ...... RTC_GPIO17 = BIT(17) } rtc_gpio_num_t; /* * sel == 0, select the function 0 of rtc * sel == 1, select the function 1 of rtc * sel == 2, select the function 2 of rtc * sel == 3, select the function 3 of rtc */ void rtc_pads_funsel(rtc_gpio_num_t rtc_gpio_num, uint8_t sel);
[编辑] 6.3.3 rtc_pads_slpsel
Sleep mode selection signal of the pad, Set to 1 to put the pad in sleep mode
0x4008d648 <rtc_pads_slpsel>: entry a1, 32 0x4008d64b <rtc_pads_slpsel+3>: bbci a2, 0, 0x4008d66c <rtc_pads_slpsel+36> 0x4008d64e <rtc_pads_slpsel+6>: l32r a8, 0x4008c9b4 0x4008d651 <rtc_pads_slpsel+9>: l32r a9, 0x4008add4 0x4008d654 <rtc_pads_slpsel+12>: memw 0x4008d657 <rtc_pads_slpsel+15>: l32i a11, a8, 0 0x4008d65a <rtc_pads_slpsel+18>: extui a10, a3, 0, 1 0x4008d65d <rtc_pads_slpsel+21>: slli a10, a10, 21 0x4008d660 <rtc_pads_slpsel+24>: and a9, a11, a9 0x4008d663 <rtc_pads_slpsel+27>: or a9, a10, a9 0x4008d666 <rtc_pads_slpsel+30>: memw 0x4008d669 <rtc_pads_slpsel+33>: s32i a9, a8, 0 0x4008d66c <rtc_pads_slpsel+36>: bbci a2, 1, 0x4008d68d <rtc_pads_slpsel+69> 0x4008d66f <rtc_pads_slpsel+39>: l32r a8, 0x4008c9b4 0x4008d672 <rtc_pads_slpsel+42>: l32r a9, 0x4008bf98 0x4008d675 <rtc_pads_slpsel+45>: memw 0x4008d678 <rtc_pads_slpsel+48>: l32i a11, a8, 0 0x4008d67b <rtc_pads_slpsel+51>: extui a10, a3, 0, 1 0x4008d67e <rtc_pads_slpsel+54>: slli a10, a10, 16 0x4008d681 <rtc_pads_slpsel+57>: and a9, a11, a9 0x4008d684 <rtc_pads_slpsel+60>: or a9, a10, a9 0x4008d687 <rtc_pads_slpsel+63>: memw 0x4008d68a <rtc_pads_slpsel+66>: s32i a9, a8, 0 0x4008d68d <rtc_pads_slpsel+69>: bbci a2, 2, 0x4008d6ad <rtc_pads_slpsel+101> 0x4008d690 <rtc_pads_slpsel+72>: l32r a8, 0x4008c9b4 0x4008d693 <rtc_pads_slpsel+75>: l32r a9, 0x400888dc 0x4008d696 <rtc_pads_slpsel+78>: memw 0x4008d699 <rtc_pads_slpsel+81>: l32i.n a11, a8, 0 0x4008d69b <rtc_pads_slpsel+83>: extui a10, a3, 0, 1 0x4008d69e <rtc_pads_slpsel+86>: slli a10, a10, 11 0x4008d6a1 <rtc_pads_slpsel+89>: and a9, a11, a9 0x4008d6a4 <rtc_pads_slpsel+92>: or a9, a10, a9 0x4008d6a7 <rtc_pads_slpsel+95>: memw 0x4008d6aa <rtc_pads_slpsel+98>: s32i a9, a8, 0 0x4008d6ad <rtc_pads_slpsel+101>: bbci a2, 3, 0x4008d6cd <rtc_pads_slpsel+133> 0x4008d6b0 <rtc_pads_slpsel+104>: l32r a8, 0x4008c9b4 ...... ......
typedef enum { RTC_GPIO0 = BIT(0), RTC_GPIO1 = BIT(1), ...... ...... RTC_GPIO17 = BIT(17) } rtc_gpio_num_t; /* * sel == 1, put the pad in sleep mode */ void rtc_pads_slpsel(rtc_gpio_num_t rtc_gpio_num, uint8_t sel);
[编辑] 6.3.4 rtc_pads_slpie
0x4008da1c <rtc_pads_slpie>: entry a1, 32 0x4008da1f <rtc_pads_slpie+3>: bbci a2, 6, 0x4008da40 <rtc_pads_slpie+36> 0x4008da22 <rtc_pads_slpie+6>: l32r a8, 0x4008bfa4 0x4008da25 <rtc_pads_slpie+9>: l32r a9, 0x4008da18 0x4008da28 <rtc_pads_slpie+12>: memw 0x4008da2b <rtc_pads_slpie+15>: l32i a11, a8, 0 0x4008da2e <rtc_pads_slpie+18>: extui a10, a3, 0, 1 0x4008da31 <rtc_pads_slpie+21>: slli a10, a10, 13 0x4008da34 <rtc_pads_slpie+24>: and a9, a11, a9 0x4008da37 <rtc_pads_slpie+27>: or a9, a10, a9 0x4008da3a <rtc_pads_slpie+30>: memw 0x4008da3d <rtc_pads_slpie+33>: s32i a9, a8, 0 0x4008da40 <rtc_pads_slpie+36>: bbci a2, 7, 0x4008da61 <rtc_pads_slpie+69> 0x4008da43 <rtc_pads_slpie+39>: l32r a8, 0x4008bfb0 0x4008da46 <rtc_pads_slpie+42>: l32r a9, 0x4008da18 0x4008da49 <rtc_pads_slpie+45>: memw 0x4008da4c <rtc_pads_slpie+48>: l32i a11, a8, 0 0x4008da4f <rtc_pads_slpie+51>: extui a10, a3, 0, 1 0x4008da52 <rtc_pads_slpie+54>: slli a10, a10, 13 0x4008da55 <rtc_pads_slpie+57>: and a9, a11, a9 0x4008da58 <rtc_pads_slpie+60>: or a9, a10, a9 0x4008da5b <rtc_pads_slpie+63>: memw 0x4008da5e <rtc_pads_slpie+66>: s32i a9, a8, 0 0x4008da61 <rtc_pads_slpie+69>: bbci a2, 8, 0x4008da81 <rtc_pads_slpie+101> 0x4008da64 <rtc_pads_slpie+72>: l32r a8, 0x4008c9bc 0x4008da67 <rtc_pads_slpie+75>: l32r a9, 0x4008da18 0x4008da6a <rtc_pads_slpie+78>: memw 0x4008da6d <rtc_pads_slpie+81>: l32i.n a11, a8, 0 0x4008da6f <rtc_pads_slpie+83>: extui a10, a3, 0, 1 0x4008da72 <rtc_pads_slpie+86>: slli a10, a10, 13 0x4008da75 <rtc_pads_slpie+89>: and a9, a11, a9 0x4008da78 <rtc_pads_slpie+92>: or a9, a10, a9 0x4008da7b <rtc_pads_slpie+95>: memw 0x4008da7e <rtc_pads_slpie+98>: s32i a9, a8, 0 0x4008da81 <rtc_pads_slpie+101>: bbci a2, 9, 0x4008daa1 <rtc_pads_slpie+133> 0x4008da84 <rtc_pads_slpie+104>: l32r a8, 0x4008c9bc ...... ......
typedef enum { RTC_GPIO0 = BIT(0), RTC_GPIO1 = BIT(1), ...... ...... RTC_GPIO17 = BIT(17) } rtc_gpio_num_t; /* * sel == 1, put the pad in sleep mode * * Only valide for RTC_GPIO6 - RTC_GPIO17 */ void rtc_pads_slpie(rtc_gpio_num_t rtc_gpio_num, uint8_t enable);
[编辑] 6.3.5 rtc_pads_funie
Input enable of the pad.
0x4008dba4 <rtc_pads_funie>: entry a1, 32 0x4008dba7 <rtc_pads_funie+3>: bbci a2, 6, 0x4008dbc8 <rtc_pads_funie+36> 0x4008dbaa <rtc_pads_funie+6>: l32r a8, 0x4008bfa4 0x4008dbad <rtc_pads_funie+9>: l32r a9, 0x400888dc 0x4008dbb0 <rtc_pads_funie+12>: memw 0x4008dbb3 <rtc_pads_funie+15>: l32i a11, a8, 0 0x4008dbb6 <rtc_pads_funie+18>: extui a10, a3, 0, 1 0x4008dbb9 <rtc_pads_funie+21>: slli a10, a10, 11 0x4008dbbc <rtc_pads_funie+24>: and a9, a11, a9 0x4008dbbf <rtc_pads_funie+27>: or a9, a10, a9 0x4008dbc2 <rtc_pads_funie+30>: memw 0x4008dbc5 <rtc_pads_funie+33>: s32i a9, a8, 0 0x4008dbc8 <rtc_pads_funie+36>: bbci a2, 7, 0x4008dbe9 <rtc_pads_funie+69> 0x4008dbcb <rtc_pads_funie+39>: l32r a8, 0x4008bfb0 0x4008dbce <rtc_pads_funie+42>: l32r a9, 0x400888dc 0x4008dbd1 <rtc_pads_funie+45>: memw 0x4008dbd4 <rtc_pads_funie+48>: l32i a11, a8, 0 0x4008dbd7 <rtc_pads_funie+51>: extui a10, a3, 0, 1 0x4008dbda <rtc_pads_funie+54>: slli a10, a10, 11 0x4008dbdd <rtc_pads_funie+57>: and a9, a11, a9 0x4008dbe0 <rtc_pads_funie+60>: or a9, a10, a9 0x4008dbe3 <rtc_pads_funie+63>: memw 0x4008dbe6 <rtc_pads_funie+66>: s32i a9, a8, 0 0x4008dbe9 <rtc_pads_funie+69>: bbci a2, 8, 0x4008dc09 <rtc_pads_funie+101> 0x4008dbec <rtc_pads_funie+72>: l32r a8, 0x4008c9bc ...... ......
typedef enum { RTC_GPIO0 = BIT(0), RTC_GPIO1 = BIT(1), ...... ...... RTC_GPIO17 = BIT(17) } rtc_gpio_num_t; /* * enable == 1, input enable * enable == 0, input disable * * Only the RTC_GPIO6 - RTC_GPIO17 are valide */ void rtc_pads_funie (rtc_gpio_num_t rtc_gpio_num, uint8_t enable);
[编辑] 6.3.6 rtc_pads_slpoe
Output enable of the pad.
0x4008d890 <rtc_pads_slpoe>: entry a1, 32 0x4008d893 <rtc_pads_slpoe+3>: bbci a2, 6, 0x4008d8b4 <rtc_pads_slpoe+36> 0x4008d896 <rtc_pads_slpoe+6>: l32r a8, 0x4008bfa4 0x4008d899 <rtc_pads_slpoe+9>: l32r a9, 0x40087114 0x4008d89c <rtc_pads_slpoe+12>: memw 0x4008d89f <rtc_pads_slpoe+15>: l32i a11, a8, 0 0x4008d8a2 <rtc_pads_slpoe+18>: extui a10, a3, 0, 1 0x4008d8a5 <rtc_pads_slpoe+21>: slli a10, a10, 12 0x4008d8a8 <rtc_pads_slpoe+24>: and a9, a11, a9 0x4008d8ab <rtc_pads_slpoe+27>: or a9, a10, a9 0x4008d8ae <rtc_pads_slpoe+30>: memw 0x4008d8b1 <rtc_pads_slpoe+33>: s32i a9, a8, 0 0x4008d8b4 <rtc_pads_slpoe+36>: bbci a2, 7, 0x4008d8d5 <rtc_pads_slpoe+69> 0x4008d8b7 <rtc_pads_slpoe+39>: l32r a8, 0x4008bfb0 0x4008d8ba <rtc_pads_slpoe+42>: l32r a9, 0x40087114 0x4008d8bd <rtc_pads_slpoe+45>: memw 0x4008d8c0 <rtc_pads_slpoe+48>: l32i a11, a8, 0 0x4008d8c3 <rtc_pads_slpoe+51>: extui a10, a3, 0, 1 0x4008d8c6 <rtc_pads_slpoe+54>: slli a10, a10, 12 0x4008d8c9 <rtc_pads_slpoe+57>: and a9, a11, a9 0x4008d8cc <rtc_pads_slpoe+60>: or a9, a10, a9 0x4008d8cf <rtc_pads_slpoe+63>: memw 0x4008d8d2 <rtc_pads_slpoe+66>: s32i a9, a8, 0 0x4008d8d5 <rtc_pads_slpoe+69>: bbci a2, 8, 0x4008d8f5 <rtc_pads_slpoe+101> 0x4008d8d8 <rtc_pads_slpoe+72>: l32r a8, 0x4008c9bc ...... ......
typedef enum { RTC_GPIO0 = BIT(0), RTC_GPIO1 = BIT(1), ...... ...... RTC_GPIO17 = BIT(17) } rtc_gpio_num_t; /* * enable == 1, Output enable * enable == 0, Output disable * Only RTC_GPIO6 - RTC_GPIO17 are valide */ void rtc_pads_slpoe(rtc_gpio_num_t rtc_gpio_num, uint8_t enable);
[编辑] 6.3.7 rtc_pads_hold
0x4008e03c <rtc_pads_hold>: entry a1, 32 0x4008e03f <rtc_pads_hold+3>: bbci a2, 6, 0x4008e060 <rtc_pads_hold+36> 0x4008e042 <rtc_pads_hold+6>: l32r a8, 0x4008bfa4 0x4008e045 <rtc_pads_hold+9>: l32r a9, 0x4008620c 0x4008e048 <rtc_pads_hold+12>: memw 0x4008e04b <rtc_pads_hold+15>: l32i a11, a8, 0 0x4008e04e <rtc_pads_hold+18>: extui a10, a3, 0, 1 0x4008e051 <rtc_pads_hold+21>: slli a10, a10, 29 0x4008e054 <rtc_pads_hold+24>: and a9, a11, a9 0x4008e057 <rtc_pads_hold+27>: or a9, a10, a9 0x4008e05a <rtc_pads_hold+30>: memw 0x4008e05d <rtc_pads_hold+33>: s32i a9, a8, 0 0x4008e060 <rtc_pads_hold+36>: bbci a2, 7, 0x4008e081 <rtc_pads_hold+69> 0x4008e063 <rtc_pads_hold+39>: l32r a8, 0x4008bfb0 0x4008e066 <rtc_pads_hold+42>: l32r a9, 0x4008620c 0x4008e069 <rtc_pads_hold+45>: memw 0x4008e06c <rtc_pads_hold+48>: l32i a11, a8, 0 0x4008e06f <rtc_pads_hold+51>: extui a10, a3, 0, 1 0x4008e072 <rtc_pads_hold+54>: slli a10, a10, 29 0x4008e075 <rtc_pads_hold+57>: and a9, a11, a9 0x4008e078 <rtc_pads_hold+60>: or a9, a10, a9 0x4008e07b <rtc_pads_hold+63>: memw 0x4008e07e <rtc_pads_hold+66>: s32i a9, a8, 0 0x4008e081 <rtc_pads_hold+69>: bbci a2, 8, 0x4008e0a1 <rtc_pads_hold+101> 0x4008e084 <rtc_pads_hold+72>: l32r a8, 0x4008c9bc 0x4008e087 <rtc_pads_hold+75>: l32r a9, 0x4008620c ...... ......
typedef enum { RTC_GPIO0 = BIT(0), RTC_GPIO1 = BIT(1), ...... ...... RTC_GPIO17 = BIT(17) } rtc_gpio_num_t; /* * hold == 1, Hold output value * hold == 0, normal operation * Only RTC_GPIO6 - RTC_GPIO17 are valide */ void rtc_pads_hold(rtc_gpio_num_t rtc_gpio_num, uint8_t hold);
[编辑] 6.3.8 rtc_pads_pu
0x4008dd2c <rtc_pads_pu>: entry a1, 32 0x4008dd2f <rtc_pads_pu+3>: bbci a2, 6, 0x4008dd50 <rtc_pads_pu+36> 0x4008dd32 <rtc_pads_pu+6>: l32r a8, 0x4008bfa4 0x4008dd35 <rtc_pads_pu+9>: l32r a9, 0x40084bc0 0x4008dd38 <rtc_pads_pu+12>: memw 0x4008dd3b <rtc_pads_pu+15>: l32i a11, a8, 0 0x4008dd3e <rtc_pads_pu+18>: extui a10, a3, 0, 1 0x4008dd41 <rtc_pads_pu+21>: slli a10, a10, 27 0x4008dd44 <rtc_pads_pu+24>: and a9, a11, a9 0x4008dd47 <rtc_pads_pu+27>: or a9, a10, a9 0x4008dd4a <rtc_pads_pu+30>: memw 0x4008dd4d <rtc_pads_pu+33>: s32i a9, a8, 0 0x4008dd50 <rtc_pads_pu+36>: bbci a2, 7, 0x4008dd71 <rtc_pads_pu+69> 0x4008dd53 <rtc_pads_pu+39>: l32r a8, 0x4008bfb0 0x4008dd56 <rtc_pads_pu+42>: l32r a9, 0x40084bc0 0x4008dd59 <rtc_pads_pu+45>: memw 0x4008dd5c <rtc_pads_pu+48>: l32i a11, a8, 0 0x4008dd5f <rtc_pads_pu+51>: extui a10, a3, 0, 1 0x4008dd62 <rtc_pads_pu+54>: slli a10, a10, 27 0x4008dd65 <rtc_pads_pu+57>: and a9, a11, a9 0x4008dd68 <rtc_pads_pu+60>: or a9, a10, a9 0x4008dd6b <rtc_pads_pu+63>: memw 0x4008dd6e <rtc_pads_pu+66>: s32i a9, a8, 0 0x4008dd71 <rtc_pads_pu+69>: bbci a2, 8, 0x4008dd91 <rtc_pads_pu+101> 0x4008dd74 <rtc_pads_pu+72>: l32r a8, 0x4008c9bc 0x4008dd77 <rtc_pads_pu+75>: l32r a9, 0x40084bc0 ...... ......
typedef enum { RTC_GPIO0 = BIT(0), RTC_GPIO1 = BIT(1), ...... ...... RTC_GPIO17 = BIT(17) } rtc_gpio_num_t; /* * pu == 1, pull-up enable * pu == 0, pull-up disable * Only RTC_GPIO6 - RTC_GPIO17 are valide */ void rtc_pads_pu(rtc_gpio_num_t rtc_gpio_num, uint8_t pu);
[编辑] 6.3.9 rtc_pads_pd
0x4008deb4 <rtc_pads_pd>: entry a1, 32 0x4008deb7 <rtc_pads_pd+3>: bbci a2, 6, 0x4008ded8 <rtc_pads_pd+36> 0x4008deba <rtc_pads_pd+6>: l32r a8, 0x4008bfa4 0x4008debd <rtc_pads_pd+9>: l32r a9, 0x40087110 0x4008dec0 <rtc_pads_pd+12>: memw 0x4008dec3 <rtc_pads_pd+15>: l32i a11, a8, 0 0x4008dec6 <rtc_pads_pd+18>: extui a10, a3, 0, 1 0x4008dec9 <rtc_pads_pd+21>: slli a10, a10, 28 0x4008decc <rtc_pads_pd+24>: and a9, a11, a9 0x4008decf <rtc_pads_pd+27>: or a9, a10, a9 0x4008ded2 <rtc_pads_pd+30>: memw 0x4008ded5 <rtc_pads_pd+33>: s32i a9, a8, 0 0x4008ded8 <rtc_pads_pd+36>: bbci a2, 7, 0x4008def9 <rtc_pads_pd+69> 0x4008dedb <rtc_pads_pd+39>: l32r a8, 0x4008bfb0 0x4008dede <rtc_pads_pd+42>: l32r a9, 0x40087110 0x4008dee1 <rtc_pads_pd+45>: memw 0x4008dee4 <rtc_pads_pd+48>: l32i a11, a8, 0 0x4008dee7 <rtc_pads_pd+51>: extui a10, a3, 0, 1 0x4008deea <rtc_pads_pd+54>: slli a10, a10, 28 0x4008deed <rtc_pads_pd+57>: and a9, a11, a9 0x4008def0 <rtc_pads_pd+60>: or a9, a10, a9 0x4008def3 <rtc_pads_pd+63>: memw 0x4008def6 <rtc_pads_pd+66>: s32i a9, a8, 0 0x4008def9 <rtc_pads_pd+69>: bbci a2, 8, 0x4008df19 <rtc_pads_pd+101> 0x4008defc <rtc_pads_pd+72>: l32r a8, 0x4008c9bc 0x4008deff <rtc_pads_pd+75>: l32r a9, 0x40087110 ...... ......
typedef enum { RTC_GPIO0 = BIT(0), RTC_GPIO1 = BIT(1), ...... ...... RTC_GPIO17 = BIT(17) } rtc_gpio_num_t; /* * pd == 1, pull-down enable * pd == 0, pull-down disable * Only RTC_GPIO6 - RTC_GPIO17 are valide */ void rtc_pads_pd(rtc_gpio_num_t rtc_gpio_num, uint8_t pd);
[编辑] 6.3.10 rtc_set_wakeup_opt
0x4008ff8c <rtc_set_wakeup_opt>: entry a1, 32 0x4008ff8f <rtc_set_wakeup_opt+3>: l32r a8, 0x4008ff84 <-- load the address of RTC_CNTL_WAKEUP_STATE_REG 0x4008ff92 <rtc_set_wakeup_opt+6>: l32r a11, 0x4008d188 <-- a11 = 0xffc007ff 0x4008ff95 <rtc_set_wakeup_opt+9>: memw 0x4008ff98 <rtc_set_wakeup_opt+12>: l32i.n a9, a8, 0 <-- Read the RTC_CNTL_WAKEUP_STATE_REG 0x4008ff9a <rtc_set_wakeup_opt+14>: extui a2, a2, 0, 11 <-- Extract the low 11 bits of 1st parameter 0x4008ff9d <rtc_set_wakeup_opt+17>: slli a10, a2, 11 <-- Shift left 11 0x4008ffa0 <rtc_set_wakeup_opt+20>: and a9, a9, a11 <-- RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff (only bitpos:[21:11]) 0x4008ffa3 <rtc_set_wakeup_opt+23>: or a9, a10, a9 <-- (RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff) | wakeup_opt 0x4008ffa6 <rtc_set_wakeup_opt+26>: memw 0x4008ffa9 <rtc_set_wakeup_opt+29>: s32i.n a9, a8, 0 <-- Write to RTC_CNTL_WAKEUP_STATE_REG 0x4008ffab <rtc_set_wakeup_opt+31>: l32r a8, 0x4008ff88 <--- load the address of RTC_CNTL_SLP_REJECT_CONF_REG 0x4008ffae <rtc_set_wakeup_opt+34>: memw 0x4008ffb1 <rtc_set_wakeup_opt+37>: s32i.n a3, a8, 0 <-- store the 2nd parameter into RTC_CNTL_SLP_REJECT_CONF_REG directly 0x4008ffb3 <rtc_set_wakeup_opt+39>: retw.n (gdb) x /1x 0x4008ff84 0x4008ff84: 0x3ff48038 (gdb) x /1x 0x4008d188 0x4008d188: 0xffc007ff (gdb) x /1x 0x4008ff88 0x4008ff88: 0x3ff48064 #define DR_REG_RTCCNTL_BASE 0x3ff48000 #define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) #define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) /* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */ /*description: enable filter for gpio wakeup event*/ #define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22)) #define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(22)) #define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 #define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22 /* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */ /*description: wakeup enable bitmap*/ #define RTC_CNTL_WAKEUP_ENA 0x000007FF #define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) #define RTC_CNTL_WAKEUP_ENA_V 0x7FF #define RTC_CNTL_WAKEUP_ENA_S 11 /* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */ /*description: wakeup cause*/ #define RTC_CNTL_WAKEUP_CAUSE 0x000007FF #define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) #define RTC_CNTL_WAKEUP_CAUSE_V 0x7FF #define RTC_CNTL_WAKEUP_CAUSE_S 0
>>> So the rtc_set_wakeup_opt should be:
void rtc_set_wakeup_opt(uint32_t wakeup_opt, uint32_t sleep_reject_conf);
[编辑] 6.3.11 rtc_pad_ext_wakeup
Following:
- p1 is the 1st parameter of rtc_pad_ext_wakeup
- p2 is the 2nd parameter of rtc_pad_ext_wakeup
- p3 is the 3rd parameter of rtc_pad_ext_wakeup
0x4008ee9c <rtc_pad_ext_wakeup>: entry a1, 32 0x4008ee9f <rtc_pad_ext_wakeup+3>: mov.n a10, a2 0x4008eea1 <rtc_pad_ext_wakeup+5>: movi.n a11, 1 0x4008eea3 <rtc_pad_ext_wakeup+7>: call8 0x4008d2f4 <rtc_pads_muxsel> /* rtc_pads_muxsel (p1, 1) */ 0x4008eea6 <rtc_pad_ext_wakeup+10>: mov.n a10, a2 0x4008eea8 <rtc_pad_ext_wakeup+12>: movi.n a11, 0 0x4008eeaa <rtc_pad_ext_wakeup+14>: call8 0x4008d54c <rtc_pads_funsel> /* rtc_pads_funsel (p1, 0) */ 0x4008eead <rtc_pad_ext_wakeup+17>: l32r a8, 0x4008edf4 /* a8 = *(4008edf4) = 0x3ff4840c, RTC_GPIO_ENABLE_REG */ 0x4008eeb0 <rtc_pad_ext_wakeup+20>: slli a9, a2, 14 0x4008eeb3 <rtc_pad_ext_wakeup+23>: memw 0x4008eeb6 <rtc_pad_ext_wakeup+26>: l32i.n a10, a8, 0 /* a10 = read RTC_GPIO_ENABLE_REG */ 0x4008eeb8 <rtc_pad_ext_wakeup+28>: movi.n a11, -1 /* a11 = 0xffff ffff */ 0x4008eeba <rtc_pad_ext_wakeup+30>: xor a9, a11, a9 /* a9 = ~a9 */ 0x4008eebd <rtc_pad_ext_wakeup+33>: and a9, a9, a10 /* a9 = a10 & a9 */ 0x4008eec0 <rtc_pad_ext_wakeup+36>: memw 0x4008eec3 <rtc_pad_ext_wakeup+39>: s32i.n a9, a8, 0 /* store to RTC_GPIO_ENABLE_REG, disable the output of the RTC_PAD */ 0x4008eec5 <rtc_pad_ext_wakeup+41>: mov.n a10, a2 0x4008eec7 <rtc_pad_ext_wakeup+43>: movi a11, 1 0x4008eeca <rtc_pad_ext_wakeup+46>: call8 0x4008d794 <rtc_pads_slpsel> /* rtc_pads_slpsel (p1, 1) */ 0x4008eecd <rtc_pad_ext_wakeup+49>: mov.n a10, a2 0x4008eecf <rtc_pad_ext_wakeup+51>: movi a11, 0 0x4008eed2 <rtc_pad_ext_wakeup+54>: call8 0x4008d9dc <rtc_pads_slpoe> /* rtc_pads_slpoe (p1, 0) */ 0x4008eed5 <rtc_pad_ext_wakeup+57>: mov.n a10, a2 0x4008eed7 <rtc_pad_ext_wakeup+59>: movi a11, 1 0x4008eeda <rtc_pad_ext_wakeup+62>: call8 0x4008db68 <rtc_pads_slpie> /* rtc_pads_slpie (p1, 1) */ 0x4008eedd <rtc_pad_ext_wakeup+65>: mov.n a10, a2 0x4008eedf <rtc_pad_ext_wakeup+67>: movi a11, 1 0x4008eee2 <rtc_pad_ext_wakeup+70>: call8 0x4008dcf0 <rtc_pads_funie> /* rtc_pads_funie (p1, 1) */ 0x4008eee5 <rtc_pad_ext_wakeup+73>: mov.n a10, a2 0x4008eee7 <rtc_pad_ext_wakeup+75>: movi a11, 0 0x4008eeea <rtc_pad_ext_wakeup+78>: call8 0x4008de78 <rtc_pads_pu> /* rtc_pads_pu (p1, 0) */ 0x4008eeed <rtc_pad_ext_wakeup+81>: mov.n a10, a2 0x4008eeef <rtc_pad_ext_wakeup+83>: movi.n a11, 0 0x4008eef1 <rtc_pad_ext_wakeup+85>: call8 0x4008e000 <rtc_pads_pd> /* rtc_pads_pd (p1, 0) */ 0x4008eef4 <rtc_pad_ext_wakeup+88>: l32r a8, 0x4008ee90 /* a8 = *(0x4008ee90) = 0x3ff484bc, RTC_IO_EXT_WAKEUP0_REG */ 0x4008eef7 <rtc_pad_ext_wakeup+91>: l32r a2, 0x4008ee94 /* a2 = *(0x4008ee94) = 0x07ffffff */ 0x4008eefa <rtc_pad_ext_wakeup+94>: memw 0x4008eefd <rtc_pad_ext_wakeup+97>: l32i.n a9, a8, 0 /* a9 = read RTC_IO_EXT_WAKEUP0_REG */ 0x4008eeff <rtc_pad_ext_wakeup+99>: slli a3, a3, 27 /* a3 = p2 << 27 */ 0x4008ef02 <rtc_pad_ext_wakeup+102>: and a9, a9, a2 /* a9 = RTC_IO_EXT_WAKEUP0_REG & 0x07ff ffff */ 0x4008ef05 <rtc_pad_ext_wakeup+105>: or a3, a3, a9 /* a3 = (p2 << 27) | a9 */ 0x4008ef08 <rtc_pad_ext_wakeup+108>: l32r a2, 0x4008ee98 /* a2 = *(0x4008ee98) = 0x3ff48060, RTC_CNTL_EXT_WAKEUP_CONF_REG */ 0x4008ef0b <rtc_pad_ext_wakeup+111>: memw 0x4008ef0e <rtc_pad_ext_wakeup+114>: s32i.n a3, a8, 0 /* write to RTC_IO_EXT_WAKEUP0_REG */ 0x4008ef10 <rtc_pad_ext_wakeup+116>: memw 0x4008ef13 <rtc_pad_ext_wakeup+119>: l32i.n a8, a2, 0 /* a8 = read RTC_CNTL_EXT_WAKEUP_CONF_REG */ 0x4008ef15 <rtc_pad_ext_wakeup+121>: l32r a3, 0x4008838c /* a3 = *(0x4008838c) = 0xbfffffff */ 0x4008ef18 <rtc_pad_ext_wakeup+124>: extui a4, a4, 0, 1 /* a4 = p3[0] */ 0x4008ef1b <rtc_pad_ext_wakeup+127>: slli a4, a4, 30 /* a4 = a4 << 30 */ 0x4008ef1e <rtc_pad_ext_wakeup+130>: and a3, a8, a3 /* a3 = a8 & a3 = RTC_CNTL_EXT_WAKEUP_CONF_REG & 0xbfff ffff */ 0x4008ef21 <rtc_pad_ext_wakeup+133>: or a4, a4, a3 /* a4 = RTC_CNTL_EXT_WAKEUP_CONF_REG & 0xbfff ffff | (p3[0] << 30) */ 0x4008ef24 <rtc_pad_ext_wakeup+136>: memw 0x4008ef27 <rtc_pad_ext_wakeup+139>: s32i.n a4, a2, 0 /* write to RTC_CNTL_EXT_WAKEUP_CONF_REG */ /* use the EXT_WAKEUP0, 0: external wakeup at low level 1: external wakeup at high level */ 0x4008ef29 <rtc_pad_ext_wakeup+141>: retw.n
So:
typedef enum { RTC_GPIO0 = BIT(0), RTC_GPIO1 = BIT(1), ...... ...... RTC_GPIO17 = BIT(17) } rtc_gpio_num_t; /* * rtc_io_num is the number of rtc_pad. e.g. The number of RTC_GPIO5 is 5 * wakeup_level = 0: external wakeup at low level * wakeup_level = 1: external wakeup at high level */ void rtc_pad_ext_wakeup(rtc_gpio_num_t rtc_pad, uint8_t rtc_io_num, uint8_t wakeup_level);
[编辑] 6.3.12 rtc_cmd_ext_wakeup
0x4008ef2c <rtc_cmd_ext_wakeup>: entry a1, 32 0x4008ef2f <rtc_cmd_ext_wakeup+3>: mov.n a10, a2 0x4008ef31 <rtc_cmd_ext_wakeup+5>: movi.n a11, 1 0x4008ef33 <rtc_cmd_ext_wakeup+7>: call8 0x4008d2f4 <rtc_pads_muxsel> 0x4008ef36 <rtc_cmd_ext_wakeup+10>: mov.n a10, a2 0x4008ef38 <rtc_cmd_ext_wakeup+12>: movi.n a11, 0 0x4008ef3a <rtc_cmd_ext_wakeup+14>: call8 0x4008d54c <rtc_pads_funsel> 0x4008ef3d <rtc_cmd_ext_wakeup+17>: l32r a8, 0x4008edf4 0x4008ef40 <rtc_cmd_ext_wakeup+20>: slli a9, a2, 14 0x4008ef43 <rtc_cmd_ext_wakeup+23>: memw 0x4008ef46 <rtc_cmd_ext_wakeup+26>: l32i.n a10, a8, 0 0x4008ef48 <rtc_cmd_ext_wakeup+28>: movi.n a11, -1 0x4008ef4a <rtc_cmd_ext_wakeup+30>: xor a9, a11, a9 0x4008ef4d <rtc_cmd_ext_wakeup+33>: and a9, a9, a10 0x4008ef50 <rtc_cmd_ext_wakeup+36>: memw 0x4008ef53 <rtc_cmd_ext_wakeup+39>: s32i.n a9, a8, 0 0x4008ef55 <rtc_cmd_ext_wakeup+41>: mov.n a10, a2 0x4008ef57 <rtc_cmd_ext_wakeup+43>: movi a11, 1 0x4008ef5a <rtc_cmd_ext_wakeup+46>: call8 0x4008d794 <rtc_pads_slpsel> 0x4008ef5d <rtc_cmd_ext_wakeup+49>: mov.n a10, a2 0x4008ef5f <rtc_cmd_ext_wakeup+51>: movi a11, 0 0x4008ef62 <rtc_cmd_ext_wakeup+54>: call8 0x4008d9dc <rtc_pads_slpoe> 0x4008ef65 <rtc_cmd_ext_wakeup+57>: mov.n a10, a2 0x4008ef67 <rtc_cmd_ext_wakeup+59>: movi a11, 1 0x4008ef6a <rtc_cmd_ext_wakeup+62>: call8 0x4008db68 <rtc_pads_slpie> 0x4008ef6d <rtc_cmd_ext_wakeup+65>: mov.n a10, a2 0x4008ef6f <rtc_cmd_ext_wakeup+67>: movi a11, 1 0x4008ef72 <rtc_cmd_ext_wakeup+70>: call8 0x4008dcf0 <rtc_pads_funie> 0x4008ef75 <rtc_cmd_ext_wakeup+73>: mov.n a10, a2 0x4008ef77 <rtc_cmd_ext_wakeup+75>: movi a11, 0 0x4008ef7a <rtc_cmd_ext_wakeup+78>: call8 0x4008de78 <rtc_pads_pu> 0x4008ef7d <rtc_cmd_ext_wakeup+81>: mov.n a10, a2 0x4008ef7f <rtc_cmd_ext_wakeup+83>: movi.n a11, 0 0x4008ef81 <rtc_cmd_ext_wakeup+85>: call8 0x4008e000 <rtc_pads_pd> 0x4008ef84 <rtc_cmd_ext_wakeup+88>: l32r a8, 0x4008ee90 0x4008ef87 <rtc_cmd_ext_wakeup+91>: l32r a2, 0x4008ee94 0x4008ef8a <rtc_cmd_ext_wakeup+94>: memw 0x4008ef8d <rtc_cmd_ext_wakeup+97>: l32i.n a9, a8, 0 0x4008ef8f <rtc_cmd_ext_wakeup+99>: slli a3, a3, 27 0x4008ef92 <rtc_cmd_ext_wakeup+102>: and a9, a9, a2 0x4008ef95 <rtc_cmd_ext_wakeup+105>: or a3, a3, a9 0x4008ef98 <rtc_cmd_ext_wakeup+108>: l32r a2, 0x4008ee98 /* a2 = *(0x4008ee98) = 0x3ff48060, RTC_CNTL_EXT_WAKEUP_CONF_REG */ 0x4008ef9b <rtc_cmd_ext_wakeup+111>: memw 0x4008ef9e <rtc_cmd_ext_wakeup+114>: s32i.n a3, a8, 0 0x4008efa0 <rtc_cmd_ext_wakeup+116>: memw /* All above is same as rtc_pad_ext_wakeup ! */ 0x4008efa3 <rtc_cmd_ext_wakeup+119>: l32i.n a8, a2, 0 /* a8 = read RTC_CNTL_EXT_WAKEUP_CONF_REG */ 0x4008efa5 <rtc_cmd_ext_wakeup+121>: l32r a3, 0x400805fc /* a3 = *(0x400805fc) = 0x40000000 */ 0x4008efa8 <rtc_cmd_ext_wakeup+124>: or a3, a8, a3 /* a3 = 0x40000000 | RTC_CNTL_EXT_WAKEUP_CONF_REG, Set BIT(30) to 1 */ /* EXT_WAKEUP0, external wake up at high level */ 0x4008efab <rtc_cmd_ext_wakeup+127>: memw 0x4008efae <rtc_cmd_ext_wakeup+130>: s32i.n a3, a2, 0 0x4008efb0 <rtc_cmd_ext_wakeup+132>: retw.n
So:
typedef enum { RTC_GPIO0 = BIT(0), RTC_GPIO1 = BIT(1), ...... ...... RTC_GPIO17 = BIT(17) } rtc_gpio_num_t; /* * rtc_io_num is the number of rtc_pad. e.g. The number of RTC_GPIO5 is 5 */ void rtc_cmd_ext_wakeup(rtc_gpio_num_t rtc_pad, uint8_t rtc_io_num);
[编辑] 6.3.13 rtc_pad_gpio_wakeup
Only available in light sleep mode
0x4008edfc <rtc_pad_gpio_wakeup>: entry a1, 32 0x4008edff <rtc_pad_gpio_wakeup+3>: mov.n a10, a2 0x4008ee01 <rtc_pad_gpio_wakeup+5>: movi.n a11, 1 0x4008ee03 <rtc_pad_gpio_wakeup+7>: call8 0x4008d2f4 <rtc_pads_muxsel> /* rtc_pads_muxsel(p1, 1) */ 0x4008ee06 <rtc_pad_gpio_wakeup+10>: mov.n a10, a2 0x4008ee08 <rtc_pad_gpio_wakeup+12>: movi.n a11, 0 0x4008ee0a <rtc_pad_gpio_wakeup+14>: call8 0x4008d54c <rtc_pads_funsel> /* rtc_pad_funsel(p1, 0) */ 0x4008ee0d <rtc_pad_gpio_wakeup+17>: l32r a8, 0x4008edf4 /* a8 = 0x3ff4840c, RTC_GPIO_ENABLE_REG */ 0x4008ee10 <rtc_pad_gpio_wakeup+20>: movi.n a9, -1 /* a9 = 0xffff ffff */ 0x4008ee12 <rtc_pad_gpio_wakeup+22>: memw 0x4008ee15 <rtc_pad_gpio_wakeup+25>: l32i.n a10, a8, 0 /* a10 = read RTC_GPIO_ENABLE_REG */ 0x4008ee17 <rtc_pad_gpio_wakeup+27>: xor a9, a9, a2 /* a9 = ~p1 = p1 ^ 0xffff ffff */ 0x4008ee1a <rtc_pad_gpio_wakeup+30>: and a9, a9, a10 /* a9 = a9 & RTC_GPIO_ENABLE_REG */ 0x4008ee1d <rtc_pad_gpio_wakeup+33>: memw 0x4008ee20 <rtc_pad_gpio_wakeup+36>: s32i.n a9, a8, 0 0x4008ee22 <rtc_pad_gpio_wakeup+38>: mov.n a10, a2 0x4008ee24 <rtc_pad_gpio_wakeup+40>: movi a11, 1 0x4008ee27 <rtc_pad_gpio_wakeup+43>: call8 0x4008d794 <rtc_pads_slpsel> /* rtc_pads_slpsel(p1, 1) */ 0x4008ee2a <rtc_pad_gpio_wakeup+46>: mov.n a10, a2 0x4008ee2c <rtc_pad_gpio_wakeup+48>: movi a11, 0 0x4008ee2f <rtc_pad_gpio_wakeup+51>: call8 0x4008d9dc <rtc_pads_slpoe> /* rtc_pads_slpoe(p1, 0) */ 0x4008ee32 <rtc_pad_gpio_wakeup+54>: mov.n a10, a2 0x4008ee34 <rtc_pad_gpio_wakeup+56>: movi a11, 1 0x4008ee37 <rtc_pad_gpio_wakeup+59>: call8 0x4008db68 <rtc_pads_slpie> /* rtc_pads_slpie(p1, 1) */ 0x4008ee3a <rtc_pad_gpio_wakeup+62>: mov.n a10, a2 0x4008ee3c <rtc_pad_gpio_wakeup+64>: movi a11, 1 0x4008ee3f <rtc_pad_gpio_wakeup+67>: call8 0x4008dcf0 <rtc_pads_funie> /* rtc_pads_funie(p1, 1) */ 0x4008ee42 <rtc_pad_gpio_wakeup+70>: mov.n a10, a2 0x4008ee44 <rtc_pad_gpio_wakeup+72>: movi.n a11, 0 0x4008ee46 <rtc_pad_gpio_wakeup+74>: call8 0x4008de78 <rtc_pads_pu> /* rtc_pads_pu(p1, 0) */ 0x4008ee49 <rtc_pad_gpio_wakeup+77>: mov.n a10, a2 0x4008ee4b <rtc_pad_gpio_wakeup+79>: movi.n a11, 0 0x4008ee4d <rtc_pad_gpio_wakeup+81>: call8 0x4008e000 <rtc_pads_pd> /* rtc_pads_pd(p1, 0) */ 0x4008ee50 <rtc_pad_gpio_wakeup+84>: extui a3, a3, 0, 3 /* a3 = p2[2:0] */ 0x4008ee53 <rtc_pad_gpio_wakeup+87>: l32r a8, 0x4008edf0 /* a8 = *(0x4008edf0) = 0x3ff48428, RTC_GPIO_PIN0_REG */ 0x4008ee56 <rtc_pad_gpio_wakeup+90>: l32r a10, 0x4008edf8 /* a10 = *(0x4008edf8) = 0x3ff48470 */ /* RTC_GPIO_PIN17_REG addr is 0x3ff4846c */ 0x4008ee59 <rtc_pad_gpio_wakeup+93>: slli a14, a3, 7 /* a14 = p2[2:0] << 7 */ 0x4008ee5c <rtc_pad_gpio_wakeup+96>: movi.n a9, 1 0x4008ee5e <rtc_pad_gpio_wakeup+98>: movi a13, 0x400 0x4008ee61 <rtc_pad_gpio_wakeup+101>: movi a12, 0xfffffc7f 0x4008ee64 <rtc_pad_gpio_wakeup+104>: bnone a9, a2, 0x4008ee84 <rtc_pad_gpio_wakeup+136> /* branch; if (a9 & a2 == 0); */ 0x4008ee67 <rtc_pad_gpio_wakeup+107>: memw 0x4008ee6a <rtc_pad_gpio_wakeup+110>: l32i.n a11, a8, 0 /* a11 = read RTC_GPIO_PINx_REG */ 0x4008ee6c <rtc_pad_gpio_wakeup+112>: or a11, a11, a13 /* a11 = RTC_GPIO_PINx_REG | 0x400 */ 0x4008ee6f <rtc_pad_gpio_wakeup+115>: memw 0x4008ee72 <rtc_pad_gpio_wakeup+118>: s32i.n a11, a8, 0 /* write to RTC_GPIO_PINx_REG */ 0x4008ee74 <rtc_pad_gpio_wakeup+120>: memw 0x4008ee77 <rtc_pad_gpio_wakeup+123>: l32i.n a11, a8, 0 /* a11 = read RTC_GPIO_PINx_REG */ 0x4008ee79 <rtc_pad_gpio_wakeup+125>: and a11, a11, a12 /* a11 = RTC_GPIO_PINx_REG & 0xfffffc7f */ 0x4008ee7c <rtc_pad_gpio_wakeup+128>: or a11, a11, a14 /* a11 |= (p2[2:0] << 7) */ 0x4008ee7f <rtc_pad_gpio_wakeup+131>: memw 0x4008ee82 <rtc_pad_gpio_wakeup+134>: s32i.n a11, a8, 0 /* write to RTC_GPIO_PIN0_REG */ 0x4008ee84 <rtc_pad_gpio_wakeup+136>: addi.n a8, a8, 4 /* a8 = 0x3ff48428 + i*4, RTC_GPIO_PINx_REG */ 0x4008ee86 <rtc_pad_gpio_wakeup+138>: slli a9, a9, 1 /* a9 <<= 1 */ 0x4008ee89 <rtc_pad_gpio_wakeup+141>: bne a8, a10, 0x4008ee64 <rtc_pad_gpio_wakeup+104> /* branch; if (a8 != a10); */ 0x4008ee8c <rtc_pad_gpio_wakeup+144>: retw.n
So:
typedef enum { RTC_GPIO0 = BIT(0), RTC_GPIO1 = BIT(1), ...... ...... RTC_GPIO17 = BIT(17) } rtc_gpio_num_t; /* * int_type: * 0: GPIO interrupt disable * 1: rising edge * 2: falling edge trigger * 3: any edge trigger * 4: low level trigger * 5: high level trigger */ void rtc_pad_gpio_wakeup(rtc_gpio_num_t rtc_pad, uint8_t int_type);
[编辑] 7 Wakeup
[编辑] 7.1 Timer Expire Wakeup
void esp_deep_sleep(uint64_t time_in_us) { rtc_set_cpu_freq(CPU_XTAL); if (esp_get_deep_sleep_wake_stub() == NULL) { esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep); } uint32_t period = rtc_slowck_cali(CALI_RTC_MUX, 128); uint32_t cycle_l, cycle_h; rtc_usec2rtc(time_in_us >> 32, time_in_us, period, &cycle_h, &cycle_l); rtc_slp_prep_lite(1, 0); rtc_sleep(cycle_h, cycle_l, TIMER_EXPIRE_EN, 0); while (1) { ; } }
[编辑] 7.2 External Wakeup
Please refer to: ESP32 RTC External Wakeup
#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) /* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ /*description: enable control XTAL by external pads*/ #define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) #define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) #define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 #define RTC_CNTL_XTL_EXT_CTR_EN_S 31 /* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ /*description: 0: power down XTAL at high level 1: power down XTAL at low level*/ #define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) #define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) #define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 #define RTC_CNTL_XTL_EXT_CTR_LV_S 30 #define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) /* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ /*description: 0: external wakeup at low level 1: external wakeup at high level*/ #define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) #define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) #define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 #define RTC_CNTL_EXT_WAKEUP1_LV_S 31 /* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ /*description: 0: external wakeup at low level 1: external wakeup at high level*/ #define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) #define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) #define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 #define RTC_CNTL_EXT_WAKEUP0_LV_S 30 #define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) /* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ /*description: clear ext wakeup1 status*/ #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18)) #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(18)) #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18 /* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */ /*description: Bitmap to select RTC pads for ext wakeup1*/ #define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF #define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) #define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFF #define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 #define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) /* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */ /*description: ext wakeup1 status*/ #define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF #define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) #define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFF #define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 #define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc) /* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ /*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/ #define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F #define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S)) #define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F #define RTC_IO_EXT_WAKEUP0_SEL_S 27 #define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0) /* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ /*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/ #define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F #define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S)) #define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F #define RTC_IO_XTL_EXT_CTR_SEL_S 27
- 0x3ff484c0 = 0x0
- 0x3ff484bc = 0x0
- 0x3ff480d0 = 0x0
- 0x3ff480cc = 0x0
- 0x3ff4805c = 0x0
- 0x3ff48060 = 0x0
[编辑] 7.3 Touch Wakeup
[编辑] 7.4 SAR Wakeup
[编辑] 7.5 BT Wakeup
[编辑] 8 ULP
ULP coprocessor is a simple FSM which is designed to perform measurements using ADC, temperature sensor, and external I2C sensors, while main processors are in deep sleep mode.
ULP coprocessor can access RTC_SLOW_MEM memory region, and registers in RTC_CNTL, RTC_IO, and SARADC peripherals.
ULP coprocessor uses fixed-width 32-bit instructions, 32-bit memory addressing, and has 4 general purpose 16-bit registers.
More details, please refer to ESP32 ULP
[编辑] 9 Demo
[编辑] 9.1 Smoke Detector
More details, please refer to: ESP32 Smoke Detector
[编辑] 9.2 Touch Pad
More details, please refer to: ESP32 Touch Pad