ESP32 Smoke Detector
来自Jack's Lab
(版本间的差异)
(→rtc_init) |
(→rtc_init_lite) |
||
第191行: | 第191行: | ||
</source> | </source> | ||
− | + | <pre> | |
− | + | /** | |
+ | * This function must be called to initialize RTC library | ||
+ | * @param xtal_freq Frequency of main crystal | ||
+ | */ | ||
+ | void rtc_init_lite(xtal_freq_t xtal_freq) | ||
+ | { | ||
+ | rtc_init(20, 20, 20, 1, 1, 1); | ||
+ | rtc_init_clk_lite(xtal_freq); | ||
+ | } | ||
<br> | <br> |
2016年12月15日 (四) 18:09的版本
目录 |
1 Overview
0x40090da0 <rtc_smoke_detector_demo>: entry a1, 48 0x40090da3 <rtc_smoke_detector_demo+3>: mov.n a10, a1 0x40090da5 <rtc_smoke_detector_demo+5>: call8 0x40090790 0x40090da8 <rtc_smoke_detector_demo+8>: movi.n a10, 0 0x40090daa <rtc_smoke_detector_demo+10>: l32i.n a4, a1, 0 0x40090dac <rtc_smoke_detector_demo+12>: call8 0x4008eb70 <rtc_init_lite> 0x40090daf <rtc_smoke_detector_demo+15>: call8 0x4008f010 <rtc_sdreg_off> 0x40090db2 <rtc_smoke_detector_demo+18>: l32r a2, 0x40087268 /* a2 = *(0x40087268) = 0x00020000 */ 0x40090db5 <rtc_smoke_detector_demo+21>: mov.n a10, a2 0x40090db7 <rtc_smoke_detector_demo+23>: call8 0x400dcef8 <slp_pad_ctrl> /* slp_pad_ctrl(1<<17) */ 0x40090dba <rtc_smoke_detector_demo+26>: mov.n a10, a2 0x40090dbc <rtc_smoke_detector_demo+28>: movi.n a11, 17 0x40090dbe <rtc_smoke_detector_demo+30>: call8 0x4008ef2c <rtc_cmd_ext_wakeup> /* rtc_cmd_ext_wakeup(1<<17, 17) */ 0x40090dc1 <rtc_smoke_detector_demo+33>: movi.n a11, 5 0x40090dc3 <rtc_smoke_detector_demo+35>: movi.n a10, 1 0x40090dc5 <rtc_smoke_detector_demo+37>: call8 0x400dcf00 <rtc_smoke_detector_in_sleep> /* rtc_smoke_detector_in_sleep(1, 5) */ 0x40090dc8 <rtc_smoke_detector_demo+40>: l32r a8, 0x40090d90 /* a8 = *(0x40090d90) = 0x3ff61774, in RTCMEM0 */ 0x40090dcb <rtc_smoke_detector_demo+43>: l32r a2, 0x40090c14 /* a2 = *(0x40090c14) = 0x00001388 = 5000 */ 0x40090dce <rtc_smoke_detector_demo+46>: l32r a3, 0x40090d94 /* a3 = *(0x40090d94) = 0x3f403de4 */ 0x40090dd1 <rtc_smoke_detector_demo+49>: memw 0x40090dd4 <rtc_smoke_detector_demo+52>: s32i.n a2, a8, 0 /* write 0x00001388 to *(0x3ff61774) */ /* a3 = 0x3f403de4, *a3 = "\n", '=' <repeats 41 times>, "\n" */ 0x40090dd6 <rtc_smoke_detector_demo+54>: mov.n a10, a3 0x40090dd8 <rtc_smoke_detector_demo+56>: call8 0x400d8b7c <rtc_printf> /* a10 = *(40090d98) = 0x3f403e10, *a10 = " Smoke Detector Demo during deep sleep... " */ 0x40090ddb <rtc_smoke_detector_demo+59>: l32r a10, 0x40090d98 0x40090dde <rtc_smoke_detector_demo+62>: call8 0x400d8b7c <rtc_printf> /* a3 = 0x3f403de4, *a3 = "\n", '=' <repeats 41 times>, "\n" */ 0x40090de1 <rtc_smoke_detector_demo+65>: mov.n a10, a3 0x40090de3 <rtc_smoke_detector_demo+67>: call8 0x400d8b7c <rtc_printf> 0x40090de6 <rtc_smoke_detector_demo+70>: l32r a10, 0x40090d9c /* a10 = *(0x40090d9c) = 0x00004e20 = 20000 */ 0x40090de9 <rtc_smoke_detector_demo+73>: l32r a8, 0x40080850 /* a8 = *(0x40080850) = 0x40008534, ets_delay_us() */ 0x40090dec <rtc_smoke_detector_demo+76>: callx8 a8 /* ets_delay_us(20000) */ 0x40090def <rtc_smoke_detector_demo+79>: mov.n a10, a2 /* a10 = 0x00001388 = 5000 */ 0x40090df1 <rtc_smoke_detector_demo+81>: call8 0x40090234 <rtc_sar_sleep_timer_start> /* rtc_sar_sleep_timer_start(5000) */ 0x40090df4 <rtc_smoke_detector_demo+84>: l32r a3, 0x4008f9c0 /* a3 = *(0x4008f9c0) = 0x3ff480b0, RTC_CNTL_STORE4_REG */ 0x40090df7 <rtc_smoke_detector_demo+87>: l32r a2, 0x4008f9e4 /* a2 = *(0x4008f9e4) = 0x3ff480b4, RTC_CNTL_STORE5_REG */ 0x40090dfa <rtc_smoke_detector_demo+90>: memw 0x40090dfd <rtc_smoke_detector_demo+93>: s32i.n a4, a3, 0 /* write a4 into RTC_CNTL_STORE4_REG */ 0x40090dff <rtc_smoke_detector_demo+95>: memw 0x40090e02 <rtc_smoke_detector_demo+98>: l32i.n a4, a2, 0 /* a4 = read RTC_CNTL_STORE5_REG */ 0x40090e04 <rtc_smoke_detector_demo+100>: movi.n a3, 32 0x40090e06 <rtc_smoke_detector_demo+102>: or a3, a4, a3 /* a3 = RTC_CNTL_STORE5_REG | 0x20 */ 0x40090e09 <rtc_smoke_detector_demo+105>: movi.n a10, 1 0x40090e0b <rtc_smoke_detector_demo+107>: or a11, a10, a10 /* a11 = 1 */ 0x40090e0e <rtc_smoke_detector_demo+110>: memw 0x40090e11 <rtc_smoke_detector_demo+113>: s32i a3, a2, 0 /* write (RTC_CNTL_STORE5_REG | 0x20) into RTC_CNTL_STORE5_REG */ 0x40090e14 <rtc_smoke_detector_demo+116>: call8 0x4008f574 <rtc_slp_prep_lite> /* rtc_slp_prep_lite(1, 1) */ 0x40090e17 <rtc_smoke_detector_demo+119>: l32r a8, 0x4008e53c /* a8 = *(0x4008e53c) = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */ 0x40090e1a <rtc_smoke_detector_demo+122>: l32r a2, 0x40087f7c /* a2 = *(0x40087f7c) = 0x00000800 */ 0x40090e1d <rtc_smoke_detector_demo+125>: memw 0x40090e20 <rtc_smoke_detector_demo+128>: l32i.n a3, a8, 0 /* a3 = read RTC_CNTL_CLK_CONF_REG = 0x25580210, DFREQ = 1010 1100 = 172 */ 0x40090e22 <rtc_smoke_detector_demo+130>: l32r a11, 0x40090c28 /* a11 = *(40090c28) = 0x00061a80 = 400000 */ 0x40090e25 <rtc_smoke_detector_demo+133>: or a2, a3, a2 /* a2 = RTC_CNTL_CLK_CONF_REG | 0x800 */ 0x40090e28 <rtc_smoke_detector_demo+136>: memw 0x40090e2b <rtc_smoke_detector_demo+139>: s32i.n a2, a8, 0 /* set BIT(11), CK8M_DFREQ_FORCE */ 0x40090e2d <rtc_smoke_detector_demo+141>: memw 0x40090e30 <rtc_smoke_detector_demo+144>: l32i.n a3, a8, 0 /* a3 = read RTC_CNTL_CLK_CONF_REG */ 0x40090e32 <rtc_smoke_detector_demo+146>: l32r a2, 0x4008fd10 /* a2 = *(0x4008fd10) = 0xfe01ffff */ 0x40090e35 <rtc_smoke_detector_demo+149>: movi.n a10, 0 0x40090e37 <rtc_smoke_detector_demo+151>: and a2, a3, a2 /* a2 = RTC_CNTL_CLK_CONF_REG & 0xfe01ffff, bit[24:17] = DFREQ */ 0x40090e3a <rtc_smoke_detector_demo+154>: l32r a3, 0x40090c24 /* a3 = *(0x40090c24) = 0x01900000 */ 0x40090e3d <rtc_smoke_detector_demo+157>: movi.n a12, 1 0x40090e3f <rtc_smoke_detector_demo+159>: or a2, a2, a3 /* a2 = RTC_CNTL_CLK_CONF_REG & 0xfe01ffff | 0x01900000 */ 0x40090e42 <rtc_smoke_detector_demo+162>: memw /* set bit[24:17] to 1 1001 000, 0xc8, 200 */ 0x40090e45 <rtc_smoke_detector_demo+165>: s32i.n a2, a8, 0 /* set DFREQ to 200 */ 0x40090e47 <rtc_smoke_detector_demo+167>: memw 0x40090e4a <rtc_smoke_detector_demo+170>: l32i.n a3, a8, 0 /* a3 = read RTC_CNTL_CLK_CONF_REG */ 0x40090e4c <rtc_smoke_detector_demo+172>: l32r a2, 0x4008fd14 /* a2 = *(0x4008fd14) = 0xffff8fff */ 0x40090e4f <rtc_smoke_detector_demo+175>: mov.n a13, a10 0x40090e51 <rtc_smoke_detector_demo+177>: and a2, a3, a2 /* a2 = RTC_CNTL_CLK_CONF_REG & 0xffff8fff, bit[14:12], CK8M_DIV_SEL */ 0x40090e54 <rtc_smoke_detector_demo+180>: l32r a3, 0x4008063c /* a3 = *(0x4008063c) = 0x00002000 */ 0x40090e57 <rtc_smoke_detector_demo+183>: or a2, a2, a3 /* a2 = RTC_CNTL_CLK_CONF_REG & 0xffff8fff | 0x00002000 */ 0x40090e5a <rtc_smoke_detector_demo+186>: memw 0x40090e5d <rtc_smoke_detector_demo+189>: s32i.n a2, a8, 0 /* write to RTC_CNTL_CLK_CONF_REG */ /* divider = reg_ck8m_div_sel + 1 */ 0x40090e5f <rtc_smoke_detector_demo+191>: call8 0x40090098 <rtc_sleep> /* rtc_sleep(0, 400000, 1, 0) */ 0x40090e62 <rtc_smoke_detector_demo+194>: retw.n
2 Process
rtc_init_lite(0); rtc_sdreg_off(); slp_pad_ctrl(1<<17); rtc_cmd_ext_wakeup(1<<17, 17); rtc_smoke_detector_in_sleep(1, 5); rtc_printf(); ets_delay_us(20000); rtc_sar_sleep_timer_start(5000); update_RTC_CNTL_STORE4_REG; update_RTC_CNTL_STORE5_REG; rtc_slp_prep_lite(1, 1); setup_RTC_CNTL_CLK_CONF_REG; rtc_sleep(0, 400000, 1, 0)
3 rtc_sdreg_off
0x4008f010 <rtc_sdreg_off>: entry a1, 32 0x4008f013 <rtc_sdreg_off+3>: l32r a8, 0x4008f00c /* a8 = 0x3ff48074, RTC_CNTL_SDIO_CONF_REG */ 0x4008f016 <rtc_sdreg_off+6>: l32r a9, 0x40080604 /* a9 = 0x00400000, BIT[22] */ /* RTC_CNTL_SDIO_FORCE : R/W ;bitpos: [22] ;default: 1'd0 */ /* 1: use SW option to control SDIO_REG 0: use state machine*/ 0x4008f019 <rtc_sdreg_off+9>: memw 0x4008f01c <rtc_sdreg_off+12>: l32i.n a10, a8, 0 /* a10 = read RTC_CNTL_SDIO_CONF_REG */ 0x4008f01e <rtc_sdreg_off+14>: or a9, a10, a9 0x4008f021 <rtc_sdreg_off+17>: memw 0x4008f024 <rtc_sdreg_off+20>: s32i.n a9, a8, 0 /* set the BIT[22] of RTC_CNTL_SDIO_CONF_REG */ 0x4008f026 <rtc_sdreg_off+22>: memw 0x4008f029 <rtc_sdreg_off+25>: l32i.n a10, a8, 0 /* a10 = read RTC_CNTL_SDIO_CONF_REG */ 0x4008f02b <rtc_sdreg_off+27>: l32r a9, 0x40084ce8 /* a9 = 0x00800000, BIT[23] */ /* RTC_CNTL_SDIO_TIEH : R/W ;bitpos: [23] ;default: 1'd1 ; */ /*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ 0x4008f02e <rtc_sdreg_off+30>: or a9, a10, a9 0x4008f031 <rtc_sdreg_off+33>: memw 0x4008f034 <rtc_sdreg_off+36>: s32i.n a9, a8, 0 /* set the BIT[23] of RTC_CNTL_SDIO_CONF_REG */ 0x4008f036 <rtc_sdreg_off+38>: memw 0x4008f039 <rtc_sdreg_off+41>: l32i.n a10, a8, 0 /* a10 = read RTC_CNTL_SDIO_CONF_REG */ 0x4008f03b <rtc_sdreg_off+43>: l32r a9, 0x400804c0 /* a9 = 0x7fffffff, BIT[31] */ /* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos: [31] ;default: 1'd0 ; */ /*description: SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/ 0x4008f03e <rtc_sdreg_off+46>: and a9, a10, a9 /* clear BIT[31] */ 0x4008f041 <rtc_sdreg_off+49>: memw 0x4008f044 <rtc_sdreg_off+52>: s32i.n a9, a8, 0 0x4008f046 <rtc_sdreg_off+54>: retw.n
4 rtc_init_lite
0x4008eb70 <rtc_init_lite>: entry a1, 32 0x4008eb73 <rtc_init_lite+3>: l32r a12, 0x4008eb68 0x4008eb76 <rtc_init_lite+6>: l32r a13, 0x4008eb6c 0x4008eb79 <rtc_init_lite+9>: l32r a10, 0x4008eb64 0x4008eb7c <rtc_init_lite+12>: movi a11, 160 0x4008eb7f <rtc_init_lite+15>: call8 0x400d8b7c <rtc_printf> 0x4008eb82 <rtc_init_lite+18>: movi a10, 20 0x4008eb85 <rtc_init_lite+21>: movi a13, 1 0x4008eb88 <rtc_init_lite+24>: mov.n a11, a10 0x4008eb8a <rtc_init_lite+26>: mov.n a12, a10 0x4008eb8c <rtc_init_lite+28>: mov.n a14, a13 0x4008eb8e <rtc_init_lite+30>: mov.n a15, a13 0x4008eb90 <rtc_init_lite+32>: call8 0x4008e5a0 <rtc_init> 0x4008eb93 <rtc_init_lite+35>: mov.n a10, a2 0x4008eb95 <rtc_init_lite+37>: call8 0x4008fe0c <rtc_init_clk_lite> 0x4008eb98 <rtc_init_lite+40>: retw.n
/** * This function must be called to initialize RTC library * @param xtal_freq Frequency of main crystal */ void rtc_init_lite(xtal_freq_t xtal_freq) { rtc_init(20, 20, 20, 1, 1, 1); rtc_init_clk_lite(xtal_freq); } <br> == rtc_init_clk_lite == <source lang=bash> 0x4008fe0c <rtc_init_clk_lite>: entry a1, 32 0x4008fe0f <rtc_init_clk_lite+3>: movi.n a12, 0 0x4008fe11 <rtc_init_clk_lite+5>: movi.n a11, 1 0x4008fe13 <rtc_init_clk_lite+7>: mov.n a10, a2 0x4008fe15 <rtc_init_clk_lite+9>: mov.n a13, a12 0x4008fe17 <rtc_init_clk_lite+11>: movi a14, 255 0x4008fe1a <rtc_init_clk_lite+14>: movi a15, 172 0x4008fe1d <rtc_init_clk_lite+17>: call8 0x4008fd18 <rtc_init_clk> 0x4008fe20 <rtc_init_clk_lite+20>: call8 0x4008f9ec <rtc_get_xtal> 0x4008fe23 <rtc_init_clk_lite+23>: or a11, a10, a10 0x4008fe26 <rtc_init_clk_lite+26>: l32r a10, 0x4008fe08 0x4008fe29 <rtc_init_clk_lite+29>: call8 0x400d8b7c <rtc_printf> 0x4008fe2c <rtc_init_clk_lite+32>: retw.n </source> rtc_init_clk(0, 1, 0, 0, 255, 172); Using the xtal clk: rtc_init_clk(0, 0, 0, 1, 255, 172); <br> == rtc_init_clk == <source lang=bash> 0x4008fd18 <rtc_init_clk>: entry a1, 32 0x4008fd1b <rtc_init_clk+3>: beqz a2, 0x4008fd30 <rtc_init_clk+24> 0x4008fd1e <rtc_init_clk+6>: slli a8, a2, 16 0x4008fd21 <rtc_init_clk+9>: extui a2, a2, 0, 16 /* p1[15:0], 1st parameter of rtc_init_clk */ 0x4008fd24 <rtc_init_clk+12>: or a2, a8, a2 0x4008fd27 <rtc_init_clk+15>: l32r a8, 0x4008f9c0 /* a8 = 0x3ff480b0, RTC_CNTL_STORE4_REG */ 0x4008fd2a <rtc_init_clk+18>: memw 0x4008fd2d <rtc_init_clk+21>: s32i a2, a8, 0 0x4008fd30 <rtc_init_clk+24>: movi.n a10, 0 0x4008fd32 <rtc_init_clk+26>: call8 0x4008fac4 <rtc_set_cpu_freq> 0x4008fd35 <rtc_init_clk+29>: l32r a2, 0x40084bf0 /* a2 = 0x6000e044 */ 0x4008fd38 <rtc_init_clk+32>: l32r a8, 0x4008fd04 /* a8 = 0x0003ff00 */ 0x4008fd3b <rtc_init_clk+35>: memw 0x4008fd3e <rtc_init_clk+38>: l32i.n a9, a2, 0 /* a9 = *(0x6000e044) = 0x0003e02d */ 0x4008fd40 <rtc_init_clk+40>: extui a6, a6, 0, 8 /* p5[7:0], 5th parameter of rtc_init_clk */ 0x4008fd43 <rtc_init_clk+43>: or a8, a9, a8 0x4008fd46 <rtc_init_clk+46>: memw 0x4008fd49 <rtc_init_clk+49>: s32i.n a8, a2, 0 0x4008fd4b <rtc_init_clk+51>: memw 0x4008fd4e <rtc_init_clk+54>: l32i.n a10, a2, 0 0x4008fd50 <rtc_init_clk+56>: l32r a9, 0x4008fd08 /* a9 = 0xfffdbfff */ 0x4008fd53 <rtc_init_clk+59>: l32r a8, 0x4008e58c /* a8 = 0x3ff4807c, RTC_CNTL_REG */ 0x4008fd56 <rtc_init_clk+62>: and a9, a10, a9 0x4008fd59 <rtc_init_clk+65>: memw 0x4008fd5c <rtc_init_clk+68>: s32i.n a9, a2, 0 0x4008fd5e <rtc_init_clk+70>: memw 0x4008fd61 <rtc_init_clk+73>: l32i.n a9, a8, 0 0x4008fd63 <rtc_init_clk+75>: l32r a2, 0x4008fd0c /* a2 = 0xffc03fff, BIT[21:14], SCK_DCAP */ 0x4008fd66 <rtc_init_clk+78>: slli a6, a6, 14 0x4008fd69 <rtc_init_clk+81>: and a9, a9, a2 0x4008fd6c <rtc_init_clk+84>: or a6, a6, a9 0x4008fd6f <rtc_init_clk+87>: l32r a2, 0x4008e53c /* a2 = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */ 0x4008fd72 <rtc_init_clk+90>: memw 0x4008fd75 <rtc_init_clk+93>: s32i.n a6, a8, 0 0x4008fd77 <rtc_init_clk+95>: memw 0x4008fd7a <rtc_init_clk+98>: l32i.n a8, a2, 0 0x4008fd7c <rtc_init_clk+100>: l32r a6, 0x4008fd10 /* a6 = 0xfe01ffff, BIT[24:17], CK8M_DFREQ */ 0x4008fd7f <rtc_init_clk+103>: extui a7, a7, 0, 8 /* p6[7:0] */ 0x4008fd82 <rtc_init_clk+106>: and a6, a8, a6 0x4008fd85 <rtc_init_clk+109>: slli a7, a7, 17 0x4008fd88 <rtc_init_clk+112>: or a7, a7, a6 0x4008fd8b <rtc_init_clk+115>: memw 0x4008fd8e <rtc_init_clk+118>: s32i.n a7, a2, 0 0x4008fd90 <rtc_init_clk+120>: memw 0x4008fd93 <rtc_init_clk+123>: l32i.n a7, a2, 0 0x4008fd95 <rtc_init_clk+125>: l32r a6, 0x4008fd14 /* a6 = 0xffff8fff, BIT[14:12], CK8M_DIV_SEL */ 0x4008fd98 <rtc_init_clk+128>: extui a4, a4, 0, 3 /* p3[2:0], 3rd parameter of rtc_init_clk */ 0x4008fd9b <rtc_init_clk+131>: and a6, a7, a6 0x4008fd9e <rtc_init_clk+134>: slli a4, a4, 12 0x4008fda1 <rtc_init_clk+137>: or a4, a4, a6 0x4008fda4 <rtc_init_clk+140>: memw 0x4008fda7 <rtc_init_clk+143>: s32i a4, a2, 0 0x4008fdaa <rtc_init_clk+146>: call8 0x4008f5f4 <===== rtc_xtal_32k_enable(); 0x4008fdad <rtc_init_clk+149>: movi.n a11, 1 0x4008fdaf <rtc_init_clk+151>: mov.n a10, a11 0x4008fdb1 <rtc_init_clk+153>: call8 0x4008f688 <rtc_8m_ena> /* rtc_8m_ena(1, 1) */ 0x4008fdb4 <rtc_init_clk+156>: movi.n a10, 50 0x4008fdb6 <rtc_init_clk+158>: l32r a8, 0x40080850 /* a8 = 0x40008534 */ 0x4008fdb9 <rtc_init_clk+161>: callx8 a8 /* ets_delay_us(50) */ 0x4008fdbc <rtc_init_clk+164>: mov.n a10, a3 /* p2, 2nd parameter of rtc_init_clk */ 0x4008fdbe <rtc_init_clk+166>: call8 0x4008f87c <rtc_set_fast_freq> /* rtc_set_fast_freq(p2) */ 0x4008fdc1 <rtc_init_clk+169>: memw /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0; fast_clk_rtc sel. 0: XTAL div 4 1: CK8M */ 0x4008fdc4 <rtc_init_clk+172>: l32i.n a7, a2, 0 /* a7 = read RTC_CNTL_CLK_CONF_REG */ 0x4008fdc6 <rtc_init_clk+174>: l32r a6, 0x4008af18 /* a6 = 0x3fffffff, BIT[31:30], slow_clk_rtc sel */ 0x4008fdc9 <rtc_init_clk+177>: slli a4, a5, 30 /* p4, 4th parameter of rtc_init_clk */ 0x4008fdcc <rtc_init_clk+180>: and a6, a7, a6 0x4008fdcf <rtc_init_clk+183>: or a4, a4, a6 0x4008fdd2 <rtc_init_clk+186>: memw 0x4008fdd5 <rtc_init_clk+189>: s32i.n a4, a2, 0 /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0; 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ 0x4008fdd7 <rtc_init_clk+191>: movi a10, 0x12c 0x4008fdda <rtc_init_clk+194>: l32r a8, 0x40080850 0x4008fddd <rtc_init_clk+197>: callx8 a8 /* ets_delay_us(300) */ 0x4008fde0 <rtc_init_clk+200>: movi.n a11, 0 0x4008fde2 <rtc_init_clk+202>: bne a3, a11, 0x4008fded <rtc_init_clk+213> 0x4008fde5 <rtc_init_clk+205>: beqi a5, 2, 0x4008fded <rtc_init_clk+213> 0x4008fde8 <rtc_init_clk+208>: mov.n a10, a11 0x4008fdea <rtc_init_clk+210>: call8 0x4008f688 <rtc_8m_ena> 0x4008fded <rtc_init_clk+213>: beqi a5, 1, 0x4008fe04 <rtc_init_clk+236> 0x4008fdf0 <rtc_init_clk+216>: l32r a2, 0x4008cb08 /* a2 = 0x3ff4848c, RTC_IO_XTAL_32K_PAD_REG */ 0x4008fdf3 <rtc_init_clk+219>: l32r a3, 0x4008cb04 /* a3 = 0xfff7ffff, BIT[19] */ 0x4008fdf6 <rtc_init_clk+222>: memw 0x4008fdf9 <rtc_init_clk+225>: l32i.n a4, a2, 0 0x4008fdfb <rtc_init_clk+227>: and a3, a4, a3 /* clear BIT[19] of XTAL_32K_PAD_REG */ 0x4008fdfe <rtc_init_clk+230>: memw 0x4008fe01 <rtc_init_clk+233>: s32i a3, a2, 0 /* Power down 32kHz crystal oscillator */ 0x4008fe04 <rtc_init_clk+236>: retw.n </source> So: <source lang=c> void rtc_init_clk(uint32_t st, uint8_t fast_clk_sel, uint8_t ck8m_divider, uint8_t slow_clk_sel,uint8_t sck_dcap,uint8_t ck8_dfreq); </source> <br> == 0x4008f5f4 == <source lang=bash> 0x4008f5f4: entry a1, 32 0x4008f5f7: l32r a8, 0x4008cb08 /* a8 = 0x3ff4848c, RTC_IO_XTAL_32K_PAD_REG */ 0x4008f5fa: l32r a9, 0x4008b7c4 /* a9 = 0x00060000, BIT[18:17] */ /* X32N_MUX_SEL, X32P_MUX_SEL, 1 is select the digital function */ 0x4008f5fd: memw 0x4008f600: l32i.n a10, a8, 0 0x4008f602: or a9, a10, a9 /* set the BIT[18:17] of XTAL_32K_PAD_REG */ 0x4008f605: memw 0x4008f608: s32i.n a9, a8, 0 0x4008f60a: memw 0x4008f60d: l32i.n a10, a8, 0 0x4008f60f: l32r a9, 0x4008f5f0 /* a9 = 0xe73fffff, BIT[28:27] BIT[23:22] */ 0x4008f612: and a9, a10, a9 /* clear the BIT[28:27] and BIT[23:23] */ 0x4008f615: memw 0x4008f618: s32i.n a9, a8, 0 /* disable the pull-up/pull-down of X32N and X32P */ 0x4008f61a: memw 0x4008f61d: l32i.n a10, a8, 0 0x4008f61f: l32r a9, 0x4008c0ec /* a9 = 0xffcfffff, BIT[21:20] */ 0x4008f622: and a9, a10, a9 0x4008f625: l32r a10, 0x4008ada0 /* a10 = 0x00100000, BIT[20] */ 0x4008f628: or a9, a9, a10 0x4008f62b: memw 0x4008f62e: s32i.n a9, a8, 0 0x4008f630: memw 0x4008f633: l32i.n a10, a8, 0 0x4008f635: movi.n a9, 24 /* a9 = 0x18 */ 0x4008f637: or a9, a10, a9 /* set BIT[4:3] of XTAL_32K_PAD_REG */ /* 32K XTAL resistor bias control */ 0x4008f63a: memw 0x4008f63d: s32i.n a9, a8, 0 0x4008f63f: memw 0x4008f642: l32i.n a10, a8, 0 0x4008f644: movi.n a9, -7 /* a9 = 0xffff fff9, BIT[2:1] */ 0x4008f646: and a9, a10, a9 /* clear BIT[2:1] */ /* 32K XTAL self-bias reference control */ 0x4008f649: memw 0x4008f64c: s32i.n a9, a8, 0 0x4008f64e: memw 0x4008f651: l32i.n a10, a8, 0 0x4008f653: l32r a9, 0x40088a9c /* a9 = 0x00080000, BIT[19] */ 0x4008f656: or a9, a10, a9 /* set BIT[19] */ /* Power up 32kHz crystal oscillator */ 0x4008f659: memw 0x4008f65c: s32i.n a9, a8, 0 0x4008f65e: retw.n 0x4008f660 <rtc_xtal_32k_ena>: entry a1, 32 0x4008f663 <rtc_xtal_32k_ena+3>: extui a2, a2, 0, 8 0x4008f666 <rtc_xtal_32k_ena+6>: beqz a2, 0x4008f670 <rtc_xtal_32k_ena+16> 0x4008f669 <rtc_xtal_32k_ena+9>: call8 0x4008f5f4 0x4008f66c <rtc_xtal_32k_ena+12>: retw.n 0x4008f66e 0x0000 0x4008f670 <rtc_xtal_32k_ena+16>: l32r a2, 0x4008cb08 /* a2 = 0x3ff4848c, RTC_IO_XTAL_32K_PAD_REG */ 0x4008f673 <rtc_xtal_32k_ena+19>: l32r a8, 0x4008cb04 /* a8 = 0xfff7ffff */ 0x4008f676 <rtc_xtal_32k_ena+22>: memw 0x4008f679 <rtc_xtal_32k_ena+25>: l32i.n a9, a2, 0 0x4008f67b <rtc_xtal_32k_ena+27>: and a8, a9, a8 /* clear BIT[19] of XTAL_32K_PAD_REG */ 0x4008f67e <rtc_xtal_32k_ena+30>: memw 0x4008f681 <rtc_xtal_32k_ena+33>: s32i.n a8, a2, 0 /* Power down 32kHz crystal oscillator */ 0x4008f683 <rtc_xtal_32k_ena+35>: retw.n </source> So: <source lang=c> void rtc_xtal_32k_ena(uint8_t enabled); </source> <br><br> == rtc_init == void rtc_init(uint8_t p1, uint16_t p2, uint8_t p3, uint8_t p4, uint8_t p5, uint8_t p6); more details please refer to: [[ESP32 RTC Init]] <br><br> <br><br><br><br> <br><br><br><br>