ADC
来自Jack's Lab
(版本间的差异)
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+ | == Overview == | ||
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+ | AD/DA 芯片几乎被模拟巨头 ADI 垄断了。当年因为Wassenaar Arrangement,美国要求最高端的技术要禁售给中国。 | ||
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+ | ADI 有好几百款芯片在禁售单上。其10bit 100MSPS以上的 ADC 芯片都是禁售的,甚至连 AD/DA 研发部门都罕有华人 | ||
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+ | <br> | ||
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== MCP3421 == | == MCP3421 == | ||
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* [http://www.docin.com/p-618373939.html sigma-delta+adc数字滤波器设计与优化] | * [http://www.docin.com/p-618373939.html sigma-delta+adc数字滤波器设计与优化] | ||
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<br><br> | <br><br> |
2018年11月26日 (一) 17:09的版本
目录 |
1 Overview
AD/DA 芯片几乎被模拟巨头 ADI 垄断了。当年因为Wassenaar Arrangement,美国要求最高端的技术要禁售给中国。
ADI 有好几百款芯片在禁售单上。其10bit 100MSPS以上的 ADC 芯片都是禁售的,甚至连 AD/DA 研发部门都罕有华人
2 MCP3421
- 18 bit ADC in a SOT-23-6 package, I²C interface
- Self calibration of internal offset and Gain per each Conversion
- On-board Voltage Reference: 2.048V +-0.05%, 5ppm/C
- On-board PGA (Programmable Gain Amplifier): x1, x2, x4, x8
- Programmable Data Rate Options: 3.75 SPS (18bit), 15 SPS (16bits), 60 SPS (14bits), 240 SPS (12bits)
- Low current consumption: 145 uA (Continuous Conversion) or 39 uA (One-Shot Conversion with 1 SPS)
- 2.7V to 5.5V power supply
- -40 - 125 C
3 CS53L30
- System Features
- Native (no PLL required) support for 6-/12-MHz, 6.144-/12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master clock rates and 8- to 48-kHz audio sample rates
- Master or Slave Mode. Clock dividers can be used to generate common audio clocks from single-master clock input.
- Low power consumption
- Less than 4.5-mW stereo (16 kHz) analog mic record
- Less than 2.5-mW mono (8 kHz) analog mic record
- Selectable mic bias and digital interface logic voltages
- High-speed (400-kHz) I²C control port
https://www.cirrus.com/en/pubs/proDatasheet/CS53L30_F2.pdf
4 ADAS1000
4.1 ADS7844
4.2 ADS7688
5 参考