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=== EFM32ZG110 === * ARM Cortex-M0+ @ 32bit MCU up to 24 MHz * 32/16/8/4 KB Flash, 4/2 KB RAM * 17 GPIOs, USART+UART x2, LEUART x1, I2C x1, ADC x1(2), ACMP x1(2) * Timer(PWM) x2(6), RTC x1, PCNT x1, WATCHDOG x1 * Capacitive touch sensors * AES128 in 54 cycles * Super low-power ** 20 nA @ 3 V Shutoff Mode ** 0.5 μA @ 3V Stop mode (EM3), with brown-out detection and RAM retention ** 0.9 μA @ 3V Deep Sleep mode (EM2) ** 48 μA/MHz @ 3V Sleep mode (EM1) ** 114 μA/MHz @ 3V Run mode (EM0) * Fast wake-up time of 2 µs * Power supply 1.98 to 3.8 V * QFN24 '''Core PinMap:''' * PIN19 --- PF0 --- DBG_SWCLK / BOOT_TX * PIN20 --- PF1 --- DBG_SWDIO / BOOT_RX * PIN23 --- PE12 --- SDA * PIN24 --- PE13 --- SCL [[文件:EFM32ZG110-QFN24-pinmap.png | 550px]] '''最小系统:''' * PIN15 --- VDD 主供电,接 VCC * PIN16 --- DECOUPLE 解耦电容,必须接 1uF 到 GND! 1nF 会导致 erase flash 成功,但写 flash 会失败! * PIN02, PIN22 --- IOVDD 接 VCC * PIN09, PIN12 --- AVDD 接 VCC * PIN07 --- nRST 接 100K 到 VCC '''编程口:''' * VCC (P) ---> 3.3V * GND (G) ---> GND * CLK ('''C''') ---> SWCLK, PIN19 (PF0) * DIO ('''D''') ---> SWDIO, PIN20 (PF1) * RST ('''R''') ---> RST ''' J-Link:''' [[文件:JLink Interface Pinout SWD.jpg]] '''SPI:''' [[文件:AutoECO-LoRa-Pin.png]] * RST --- PIN18 (PC15) * SEL --- PIN6 (PB8) * MOSI --- PIN3 (PC0) * MISO --- PIN4 (PC1) * SCK --- PIN5 (PB7) * RF_DIO0 ---> PIN8 (PB11) '''Digital Pinmap:''' <pre> D00 - PA00 D01 - PB07 D02 - PB08 D03 - PB11 D04 - PB13 D05 - PB14 D06 - PC00 D07 - PC01 D08 - PC14 D09 - PC15 D10 - PD06 D11 - PD07 D12 - PE12 D13 - PE13 D14 - PF00 D15 - PF01 D16 - PF02 </pre> '''TT2:''' * PA0 ---> 10K ---> VBat * PA0 ---> Relay_Always_Open ---> GND * Dev_Power_Ctrl --- PIN17_PC14_D8 (PRS_CH0) ,控制 3V 电源芯片,同时给 PT 供电;PIN13_PD6_D10_PT01 测这个脚的电压 * {PIN17_PC14_D8 --- '''PIN13_PD6_D10 (PT01)''' } ----> 1.1K 0.1% ----> { PIN14_PD7_D11 (PT02) --- T2_J2_T } ------> PT ------> GND * PIN2_IOVDD (Vbat) ---> 10K ---> { T2_J2_IO --- PIN21_PF2_D16_RES } * PIN11_PB14 ---> T2_J8_Rx (LEU0_RX #1) * PIN10_PB13 ---> T2_J8_Tx (LEU0_TX #1) '''4合1:''' <source lang=bash> * Dev_Power_Ctrl <--- PIN17_PC14_D8 (PRS_CH0) * KEY <--- PIN1_PA0_D0, 10K 拉高到 VBat,按下 PIN1_PA0_D0 则接地 * Beep <--- PIN13_PD06_D10 * I2C_SCL <--- PIN24_PE13_D13 * I2C_SDA <--- PIN23_PE12_D12 * SH1106_RESET <--- PIN21_PF2_D16_RES </source> '''UART:''' * '''LEUART0''' * USART1 '''Peripheral:''' <source lang=cpp> #define AES_BASE (0x400E0000UL) /**< AES base address */ #define DMA_BASE (0x400C2000UL) /**< DMA base address */ #define MSC_BASE (0x400C0000UL) /**< MSC base address */ #define EMU_BASE (0x400C6000UL) /**< EMU base address */ #define RMU_BASE (0x400CA000UL) /**< RMU base address */ #define CMU_BASE (0x400C8000UL) /**< CMU base address */ #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */ #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */ #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */ #define USART1_BASE (0x4000C400UL) /**< USART1 base address */ #define PRS_BASE (0x400CC000UL) /**< PRS base address */ #define IDAC0_BASE (0x40004000UL) /**< IDAC0 base address */ #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ #define VCMP_BASE (0x40000000UL) /**< VCMP base address */ #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */ #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */ #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */ #define RTC_BASE (0x40080000UL) /**< RTC base address */ #define WDOG_BASE (0x40088000UL) /**< WDOG base address */ #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */ #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ #define ROMTABLE_BASE (0xF00FFFD0UL) /**< ROMTABLE base address */ #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ </source> '''Flash:''' The size of the main block is device dependent. The largest size available is 32 kB (32 pages). The information block has 1024 bytes available for user data. The information block also contains chip configuration data located in a reserved area. The main block is mapped to address 0x00000000 and the information block is mapped to address 0x0FE00000. All Flash memory is organized into 1024 byte pages. <source lang=cpp> /** Flash and SRAM limits for EFM32ZG110F32 */ #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ #define FLASH_SIZE (0x00008000UL) /**< Available Flash Memory */ #define FLASH_PAGE_SIZE 1024 /**< Flash Memory page size */ #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ #define SRAM_SIZE (0x00001000UL) /**< Available SRAM Memory */ #define __CM0PLUS_REV 0x001 /**< Cortex-M0+ Core revision r0p1 */ #define PRS_CHAN_COUNT 4 /**< Number of PRS channels */ #define DMA_CHAN_COUNT 4 /**< Number of DMA channels */ #define EXT_IRQ_COUNT 19 /**< Number of External (NVIC) interrupts */ </source> '''Memory:''' <source lang=cpp> /** Memory Base addresses and limits */ #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */ #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */ #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */ #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */ #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */ #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */ #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */ #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */ #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */ #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */ #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */ #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */ #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */ #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */ </source> <br>
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