ESP32 ADC
来自Jack's Lab
目录 |
1 Overview
2 Quick Start
3 Hacking
3.1 ibrtc.a
0x4008b84c <adc1_pad_init>: entry a1, 32 0x4008b84f <adc1_pad_init+3>: extui a2, a2, 0, 8 0x4008b852 <adc1_pad_init+6>: movi.n a3, 0 0x4008b854 <adc1_pad_init+8>: bgeui a2, 8, 0x4008b85f <adc1_pad_init+19> 0x4008b857 <adc1_pad_init+11>: l32r a3, 0x4008b848 0x4008b85a <adc1_pad_init+14>: addx4 a2, a2, a3 0x4008b85d <adc1_pad_init+17>: l32i.n a3, a2, 0 0x4008b85f <adc1_pad_init+19>: mov.n a10, a3 0x4008b861 <adc1_pad_init+21>: movi.n a11, 0 0x4008b863 <adc1_pad_init+23>: call8 0x4008cd84 <rtc_pads_pu> 0x4008b866 <adc1_pad_init+26>: mov.n a10, a3 0x4008b868 <adc1_pad_init+28>: movi.n a11, 0 0x4008b86a <adc1_pad_init+30>: call8 0x4008cf0c <rtc_pads_pd> 0x4008b86d <adc1_pad_init+33>: mov.n a10, a3 0x4008b86f <adc1_pad_init+35>: movi.n a11, 0 0x4008b871 <adc1_pad_init+37>: call8 0x4008cbfc <rtc_pads_funie> 0x4008b874 <adc1_pad_init+40>: mov.n a10, a3 0x4008b876 <adc1_pad_init+42>: movi.n a11, 0 0x4008b878 <adc1_pad_init+44>: call8 0x4008ca74 <rtc_pads_slpie> 0x4008b87b <adc1_pad_init+47>: mov.n a10, a3 0x4008b87d <adc1_pad_init+49>: movi.n a11, 0 0x4008b87f <adc1_pad_init+51>: call8 0x4008c8e8 <rtc_pads_slpoe> 0x4008b882 <adc1_pad_init+54>: retw.n 0x4008b884 <adc1_read>: entry a1, 32 0x4008b887 <adc1_read+3>: extui a2, a2, 0, 8 0x4008b88a <adc1_read+6>: or a10, a2, a2 0x4008b88d <adc1_read+9>: call8 0x4008b84c <adc1_pad_init> 0x4008b890 <adc1_read+12>: extui a3, a3, 0, 8 0x4008b893 <adc1_read+15>: mov.n a10, a2 0x4008b895 <adc1_read+17>: mov.n a11, a3 0x4008b897 <adc1_read+19>: movi.n a12, 2 0x4008b899 <adc1_read+21>: call8 0x4008b0b4 <adc1_read_test> 0x4008b89c <adc1_read+24>: mov.n a2, a10 0x4008b89e <adc1_read+26>: retw.n 0x4008b8a0 <adc1_amp_read>: entry a1, 32 0x4008b8a3 <adc1_amp_read+3>: movi.n a10, 0 0x4008b8a5 <adc1_amp_read+5>: call8 0x4008b84c <adc1_pad_init> 0x4008b8a8 <adc1_amp_read+8>: movi.n a10, 0 0x4008b8aa <adc1_amp_read+10>: mov.n a11, a10 0x4008b8ac <adc1_amp_read+12>: movi a12, 0x400 0x4008b8af <adc1_amp_read+15>: movi.n a13, 1 0x4008b8b1 <adc1_amp_read+17>: movi.n a14, 4 0x4008b8b3 <adc1_amp_read+19>: call8 0x4008b220 <adc1_amp_read_full> 0x4008b8b6 <adc1_amp_read+22>: mov.n a2, a10 0x4008b8b8 <adc1_amp_read+24>: retw.n
3.2 SAR ADC
components/esp32/include/soc/saradc_reg.h
#define DR_REG_SARADC_BASE 0x3ff48800 #define SARADC_SAR_READ_STATUS1_REG (DR_REG_SARADC_BASE + 0x0004) /* SARADC_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ #define SARADC_SAR_MEAS_WAIT1_REG (DR_REG_SARADC_BASE + 0x0008) /* SARADC_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ #define SARADC_SAR_MEAS_WAIT2_REG (DR_REG_SARADC_BASE + 0x000c) /* SARADC_SAR2_RSTB_WAIT : R/W ;bitpos:[27:20] ;default: 8'd2 ; */ #define SARADC_SAR_MEAS_CTRL_REG (DR_REG_SARADC_BASE + 0x0010) /* SARADC_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */ #define SARADC_SAR_READ_STATUS2_REG (DR_REG_SARADC_BASE + 0x0014) /* SARADC_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ #define SARADC_ULP_CP_SLEEP_CYC1_REG (DR_REG_SARADC_BASE + 0x001c) /* SARADC_SLEEP_CYCLES_S1 : R/W ;bitpos:[31:0] ;default: 32'd100 ; */ #define SARADC_ULP_CP_SLEEP_CYC2_REG (DR_REG_SARADC_BASE + 0x0020) /* SARADC_SLEEP_CYCLES_S2 : R/W ;bitpos:[31:0] ;default: 32'd50 ; */ #define SARADC_ULP_CP_SLEEP_CYC3_REG (DR_REG_SARADC_BASE + 0x0024) /* SARADC_SLEEP_CYCLES_S3 : R/W ;bitpos:[31:0] ;default: 32'd40 ; */ #define SARADC_ULP_CP_SLEEP_CYC4_REG (DR_REG_SARADC_BASE + 0x0028) /* SARADC_SLEEP_CYCLES_S4 : R/W ;bitpos:[31:0] ;default: 32'd20 ; */ #define SARADC_SAR_START_FORCE_REG (DR_REG_SARADC_BASE + 0x002c) /* SARADC_SAR2_PWDET_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ #define SARADC_SAR_MEM_WR_CTRL_REG (DR_REG_SARADC_BASE + 0x0030) /* SARADC_RTC_MEM_WR_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ #define SARADC_SAR_ATTEN1_REG (DR_REG_SARADC_BASE + 0x0034) /* SARADC_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ /*description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/ #define SARADC_SAR_ATTEN2_REG (DR_REG_SARADC_BASE + 0x0038) /* SARADC_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ /*description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/ #define SARADC_SAR_SLAVE_ADDR1_REG (DR_REG_SARADC_BASE + 0x003c) /* SARADC_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */ #define SARADC_SAR_SLAVE_ADDR2_REG (DR_REG_SARADC_BASE + 0x0040) /* SARADC_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ #define SARADC_SAR_SLAVE_ADDR3_REG (DR_REG_SARADC_BASE + 0x0044) /* SARADC_TSENS_RDY_OUT : RO ;bitpos:[30] ;default: 1'h0 ; */ #define SARADC_SAR_SLAVE_ADDR4_REG (DR_REG_SARADC_BASE + 0x0048) /* SARADC_I2C_DONE : RO ;bitpos:[30] ;default: 1'h0 ; */ /*description: indicate I2C done*/ #define SARADC_SAR_TSENS_CTRL_REG (DR_REG_SARADC_BASE + 0x004c) /* SARADC_TSENS_DUMP_OUT : R/W ;bitpos:[26] ;default: 1'b0 ; */ /*description: temperature sensor dump out only active when reg_tsens_power_up_force = 1*/ /*description: indicate temperature sensor out ready*/ #define SARADC_SAR_TOUCH_CTRL1_REG (DR_REG_SARADC_BASE + 0x0058) /* SARADC_HALL_PHASE_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */ /*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
