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== IO_MUX == You need to make sure that RTC_GPIO0 ~ RTC_GPIO17 are routed to digital IO_MUX before using these IOs as general GPIO. Need to setup the MUX_SEL bit (clear to 0) of the control registers of the RTC_GPIO0 ~ RTC_GPIO17 More details please refer to: http://wiki.jackslab.org/ESP32_RTC#RTC_GPIO <br> === API === <source lang=cpp> /* * @brief Select pad as a gpio function (Function 3) from IOMUX. * @param uint32_t gpio_num : gpio number, 0~0x27 */ void gpio_pad_select_gpio(uint8_t gpio_num); </source> <source lang=cpp> 0x40009fdc: entry a1, 32 0x40009fdf: extui a2, a2, 0, 8 0x40009fe2: movi.n a8, 39 0x40009fe4: bgeu a8, a2, 0x40009fea 0x40009fe7: j 0x4000a0e0 /* gpio_num > 39, invalide gpio num, return */ 0x40009fea: l32r a8, 0x40009f54 /* a8 = 0x3ff9bf3c */ 0x40009fed: addx4 a2, a2, a8 /* a2 = a2*4 + 0x3ff9bf3c */ 0x40009ff0: l32i.n a2, a2, 0 0x40009ff2: jx a2 0x40009ff5: l32r a8, 0x40009f58 /* a8 = 0x3ff49044 */ 0x40009ff8: j 0x4000a0ca 0x40009ffb: l32r a8, 0x40009114 /* a8 = 0x3ff49088 */ 0x40009ffe: j 0x4000a0ca 0x4000a001: l32r a8, 0x40009f5c /* a8 = 0x3ff49040 */ 0x4000a004: j 0x4000a0ca 0x4000a007: l32r a8, 0x40009f60 /* a8 = 0x3ff49084 */ 0x4000a00a: j 0x4000a0ca 0x4000a00d: l32r a8, 0x40009f64 /* a8 = 0x3ff49048 */ 0x4000a010: j 0x4000a0ca 0x4000a013: l32r a8, 0x40009f68 /* a8 = 0x3ff4906c */ 0x4000a016: j 0x4000a0ca 0x4000a019: l32r a8, 0x40009f6c /* a8 = 0x3ff49060 */ 0x4000a01c: j 0x4000a0ca 0x4000a01f: l32r a8, 0x40009f70 /* a8 = 0x3ff49064 */ 0x4000a022: j 0x4000a0ca 0x4000a025: l32r a8, 0x400076b0 /* a8 = 0x3ff49068 */ 0x4000a028: j 0x4000a0ca 0x4000a02b: l32r a8, 0x40009f74 /* a8 = 0x3ff49054 */ 0x4000a02e: j 0x4000a0ca 0x4000a031: l32r a8, 0x4000872c /* a8 = 0x3ff49058 */ 0x4000a034: j 0x4000a0ca 0x4000a037: l32r a8, 0x40009f78 /* a8 = 0x3ff4905c */ 0x4000a03a: j 0x4000a0ca 0x4000a03d: l32r a8, 0x40009f7c /* a8 = 0x3ff49034 */ 0x4000a040: j 0x4000a0ca 0x4000a043: l32r a8, 0x40009f80 /* a8 = 0x3ff49038 */ 0x4000a046: j 0x4000a0ca 0x4000a049: l32r a8, 0x40009f84 /* a8 = 0x3ff49030 */ 0x4000a04c: j 0x4000a0ca 0x4000a04f: l32r a8, 0x40009f88 /* a8 = 0x3ff4903c */ 0x4000a052: j 0x4000a0ca 0x4000a055: l32r a8, 0x40009f8c /* a8 = 0x3ff4904c */ 0x4000a058: j 0x4000a0ca 0x4000a05b: l32r a8, 0x40009f90 /* a8 = 0x3ff49050 */ 0x4000a05e: j 0x4000a0ca 0x4000a061: l32r a8, 0x40009f94 /* a8 = 0x3ff49070 */ 0x4000a064: j 0x4000a0ca 0x4000a067: l32r a8, 0x40009f98 /* a8 = 0x3ff49074 */ 0x4000a06a: j 0x4000a0ca 0x4000a06d: l32r a8, 0x40009f9c /* a8 = 0x3ff49078 */ 0x4000a070: j 0x4000a0ca 0x4000a073: l32r a8, 0x40009fa0 /* a8 = 0x3ff4907c */ 0x4000a076: j 0x4000a0ca 0x4000a079: l32r a8, 0x40009fa4 /* a8 = 0x3ff49080 */ 0x4000a07c: j 0x4000a0ca 0x4000a07f: l32r a8, 0x40009fa8 /* a8 = 0x3ff4908c */ 0x4000a082: j 0x4000a0ca 0x4000a085: l32r a8, 0x40009fac /* a8 = 0x3ff49090 */ 0x4000a088: j 0x4000a0ca 0x4000a08b: l32r a8, 0x40009fb0 /* a8 = 0x3ff49024 */ 0x4000a08e: j 0x4000a0ca 0x4000a091: l32r a8, 0x40009fb4 /* a8 = 0x3ff49028 */ 0x4000a094: j 0x4000a0ca 0x4000a097: l32r a8, 0x40009fb8 /* a8 = 0x3ff4902c */ 0x4000a09a: j 0x4000a0ca 0x4000a09d: l32r a8, 0x40009fbc /* a8 = 0x3ff4901c */ 0x4000a0a0: j 0x4000a0ca 0x4000a0a3: l32r a8, 0x40009fc0 /* a8 = 0x3ff49020 */ 0x4000a0a6: j 0x4000a0ca 0x4000a0a9: l32r a8, 0x40009fc4 /* a8 = 0x3ff49014 */ 0x4000a0ac: j 0x4000a0ca 0x4000a0af: l32r a8, 0x40009fc8 /* a8 = 0x3ff49018 */ 0x4000a0b2: j 0x4000a0ca 0x4000a0b5: l32r a8, 0x40009fcc /* a8 = 0x3ff49004 */ 0x4000a0b8: j 0x4000a0ca 0x4000a0bb: l32r a8, 0x40009fd0 /* a8 = 0x3ff49008 */ 0x4000a0be: j 0x4000a0ca 0x4000a0c1: l32r a8, 0x40009fd4 /* a8 = 0x3ff4900c */ 0x4000a0c4: j 0x4000a0ca 0x4000a0c7: l32r a8, 0x40009fd8 /* a8 = 0x3ff49010 */ >>>> 0x4000a0ca: memw 0x4000a0cd: l32i.n a9, a8, 0 0x4000a0cf: l32r a2, 0x400076b4 /* a2 = 0xffff8fff, BIT[15] */ 0x4000a0d2: and a2, a9, a2 /* clear BIT[14:12] */ 0x4000a0d5: l32r a9, 0x40003794 /* a9 = 0x00002000 */ 0x4000a0d8: or a2, a2, a9 /* set BIT[14:12] = 0x2, MCU_FUN_SEL, function 3 */ 0x4000a0db: memw 0x4000a0de: s32i.n a2, a8, 0 0x4000a0e0: retw.n </source> <br> === Register === include/soc/io_mux_reg.h: <source lang=c> /* Following bits are for sleep mode */ #define SLP_OE (BIT(0)) #define SLP_SEL (BIT(1)) #define SLP_PD (BIT(2)) #define SLP_PU (BIT(3)) #define SLP_IE (BIT(4)) #define SLP_DRV 0x3 /* BIT[6:5] */ #define SLP_DRV_S 5 /* nomal mode related bits */ #define FUN_PD (BIT(7)) #define FUN_PU (BIT(8)) #define FUN_IE (BIT(9)) #define FUN_DRV 0x3 /* BIT[11:10], reset default: 0x2 */ #define FUN_DRV_S 10 #define MCU_SEL 0x7 /* BIT[14:12] */ #define MCU_SEL_S 12 #define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44) #define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88) #define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40) #define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84) #define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48) #define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c) ...... ...... </source> <br><br>
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