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== Clock == The RTC clock has five possible sources: * External low speed (32 KHz) crystal clock * External crystal clock divided by 4 (40MHz/4 ?) * Internal RC oscillator (typically about 150 KHz and adjustable) * Internal 8 MHz oscillator * Internal 31.25KHz clock (derived from the internal 8MHz oscillator divided by 256) <br> === API === ==== rtc_set_fast_freq ==== <source lang=bash> 0x4008f87c <rtc_set_fast_freq>: entry a1, 32 0x4008f87f <rtc_set_fast_freq+3>: l32r a8, 0x4008e53c /* a8 = *(0x4008e53c) = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */ 0x4008f882 <rtc_set_fast_freq+6>: l32r a11, 0x40086318 /* a11 = *(0x40086318) = 0xdfffffff, BIT(29), fast_clk_rtc sel */ 0x4008f885 <rtc_set_fast_freq+9>: memw 0x4008f888 <rtc_set_fast_freq+12>: l32i.n a9, a8, 0 /* a9 = read RTC_CNTL_CLK_CONF_REG */ 0x4008f88a <rtc_set_fast_freq+14>: extui a2, a2, 0, 1 /* a2 = p1[0] */ 0x4008f88d <rtc_set_fast_freq+17>: slli a10, a2, 29 /* a10 = p1[0] << 29 */ 0x4008f890 <rtc_set_fast_freq+20>: and a9, a9, a11 0x4008f893 <rtc_set_fast_freq+23>: or a9, a10, a9 /* a9 = RTC_CNTL_CLK_CONF_REG & 0xdfffffff | (p1[0] << 29) 0x4008f896 <rtc_set_fast_freq+26>: memw 0x4008f899 <rtc_set_fast_freq+29>: s32i.n a9, a8, 0 /* write to RTC_CNTL_CLK_CONF_REG */ /* fast_clk_rtc sel. 0: XTAL div 4 1: CK8M */ 0x4008f89b <rtc_set_fast_freq+31>: movi a10, 3 0x4008f89e <rtc_set_fast_freq+34>: l32r a8, 0x40080850 /* a8 = *(0x40080850) = 0x40008534, ets_delay_us */ 0x4008f8a1 <rtc_set_fast_freq+37>: callx8 a8 /* ets_delay_us(3) */ 0x4008f8a4 <rtc_set_fast_freq+40>: retw.n </source> So: <source lang=c> /* * fast_clk_rtc_sel = 0: XTAL div 4 * fast_clk_rtc_sel = 1: CK8M */ void rtc_set_fast_freq(uint8_t fast_clk_rtc_sel); </source> <br> ==== rtc_set_slow_freq ==== <source lang=bash> 0x4008f854 <rtc_set_slow_freq>: entry a1, 32 0x4008f857 <rtc_set_slow_freq+3>: l32r a8, 0x4008e53c /* a8 = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */ 0x4008f85a <rtc_set_slow_freq+6>: l32r a10, 0x4008af18 /* a10 = 0x3fffffff, BIT[31:30] */ 0x4008f85d <rtc_set_slow_freq+9>: memw 0x4008f860 <rtc_set_slow_freq+12>: l32i.n a9, a8, 0 0x4008f862 <rtc_set_slow_freq+14>: slli a2, a2, 30 0x4008f865 <rtc_set_slow_freq+17>: and a9, a9, a10 0x4008f868 <rtc_set_slow_freq+20>: or a9, a2, a9 0x4008f86b <rtc_set_slow_freq+23>: memw 0x4008f86e <rtc_set_slow_freq+26>: s32i.n a9, a8, 0 0x4008f870 <rtc_set_slow_freq+28>: movi a10, 0x12c /* a10 = 300 */ 0x4008f873 <rtc_set_slow_freq+31>: l32r a8, 0x40080850 0x4008f876 <rtc_set_slow_freq+34>: callx8 a8 /* ets_delay_us(300) */ 0x4008f879 <rtc_set_slow_freq+37>: retw.n </source> So: <source lang=c> /* * slow_clk_rtc_sel = 0: SLOW_CK * slow_clk_rtc_sel = 1: CK_XTAL_32K * slow_clk_rtc_sel = 2: CK8M_D256_OUT */ void rtc_set_slow_freq(uint8_t slow_clk_rtc_sel); </source> <br> ==== rtc_xtal_32k_ena ==== <source lang=c> void rtc_xtal_32k_ena(uint8_t enabled); </source> more details please refer to: [http://wiki.jackslab.org/ESP32_Smoke_Detector#0x4008f5f4 RTC XTAL 32K enable] <br> ==== rtc_init_clk_lite ==== <source lang=c> void rtc_init_clk_lite(uint32_t st) { rtc_init_clk(st, 1, 0, 0, 255, 172); } </source> More details please refer to: [http://wiki.jackslab.org/ESP32_Smoke_Detector#rtc_init_clk_lite RTC Init Clock Lite] <br> ==== rtc_init_clk ==== <source lang=c> void rtc_init_clk(uint32_t st, uint8_t fast_clk_sel, uint8_t ck8m_divider, uint8_t slow_clk_sel,uint8_t sck_dcap,uint8_t ck8_dfreq); rtc_init_clk(0, 1, 0, 0, 255, 172); </source> More details please refer to: [http://wiki.jackslab.org/ESP32_Smoke_Detector#rtc_init_clk RTC Init Clock] <br> === Register === <source lang=cpp> #define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ /*description: slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ #define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ /*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ #define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 /* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ /*description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ #define RTC_CNTL_SOC_CLK_SEL_S 27 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ /*description: CK8M force power up*/ #define RTC_CNTL_CK8M_FORCE_PU_S 26 /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ /*description: CK8M force power down*/ #define RTC_CNTL_CK8M_FORCE_PD_S 25 /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */ /*description: CK8M_DFREQ*/ #define RTC_CNTL_CK8M_DFREQ_S 17 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ /*description: CK8M force no gating during sleep*/ #define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ /*description: XTAL force no gating during sleep*/ #define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */ /*description: divider = reg_ck8m_div_sel + 1*/ #define RTC_CNTL_CK8M_DIV_SEL_S 12 /* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */ /*description: */ #define RTC_CNTL_CK8M_DFREQ_FORCE_S 11 /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ /*description: enable CK8M for digital core (no relationship with RTC core)*/ #define RTC_CNTL_DIG_CLK8M_EN_S 10 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ #define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ #define RTC_CNTL_DIG_XTAL32K_EN_S 8 /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ /*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ #define RTC_CNTL_ENB_CK8M_DIV_S 7 /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ /*description: disable CK8M and CK8M_D256_OUT*/ #define RTC_CNTL_ENB_CK8M_S 6 /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ /*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ #define RTC_CNTL_CK8M_DIV_S 4 #define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) /* e.g. 0x84160018 */ /* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */ /*description: Power up 32kHz crystal oscillator*/ #define RTC_IO_XPD_XTAL_32K_S 19 /* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */ /*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ #define RTC_IO_X32N_MUX_SEL_S 18 /* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ /*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/ #define RTC_IO_X32P_MUX_SEL_S 17 /* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */ /*description: the functional selection signal of the pad*/ #define RTC_IO_X32N_FUN_SEL_S 15 /* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ /*description: the functional selection signal of the pad*/ #define RTC_IO_X32P_FUN_SEL_S 9 </source> <br><br>
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