查看ESP32 RTC的源代码
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ESP32 RTC
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=== rtc_sleep === <source lang=bash> 0x4009011c <rtc_sleep>: entry a1, 32 0x4009011f <rtc_sleep+3>: l32r a9, 0x4008ff08 /* a9 = *(0x4008ff08) = 0x3ff4800c */ 0x40090122 <rtc_sleep+6>: l32r a11, 0x4008073c /* a11 = *(0x4008073c) = 0x80000000 */ 0x40090125 <rtc_sleep+9>: memw 0x40090128 <rtc_sleep+12>: l32i.n a8, a9, 0 /* a8 = *(0x3ff4800c) = 0x40000000 */ 0x4009012a <rtc_sleep+14>: l32r a10, 0x40080630 /* a10 = *(0x40080630) = 0x40000000 */ 0x4009012d <rtc_sleep+17>: or a8, a8, a11 0x40090130 <rtc_sleep+20>: memw 0x40090133 <rtc_sleep+23>: s32i.n a8, a9, 0 /* *(0x3ff4800c) = 0xC0000000 */ 0x40090135 <rtc_sleep+25>: memw 0x40090138 <rtc_sleep+28>: l32i.n a8, a9, 0 /* a8 = 0xC0000000 */ 0x4009013a <rtc_sleep+30>: bnone a8, a10, 0x40090135 /* if (a8 & a19 == 0) branch */ 0x4009013d <rtc_sleep+33>: l32r a10, 0x4008ff0c /* a10 = *(0x4008ff0c) = 0x3ff48048, RTC_CNTL_INT_CLR_REG */ 0x40090140 <rtc_sleep+36>: movi.n a8, 16 /* a8 = 16 = 0x10 */ 0x40090142 <rtc_sleep+38>: memw 0x40090145 <rtc_sleep+41>: l32i.n a9, a10, 0 /* a9 = *(0x3ff48048) = 0x0 */ 0x40090147 <rtc_sleep+43>: or a8, a9, a8 /* Clear RTC time valid interrupt state */ 0x4009014a <rtc_sleep+46>: memw 0x4009014d <rtc_sleep+49>: s32i.n a8, a10, 0 /* update to *(0x3ff48048), RTC_CNTL_INT_CLR_REG */ 0x4009014f <rtc_sleep+51>: l32r a8, 0x4008ff10 /* a8 = *(0x4008ff10) = 0x3ff48010 RTC_CNTL_TIME0_REG */ 0x40090152 <rtc_sleep+54>: l32r a9, 0x4008ff14 /* a9 = *(0x4008ff14) = 0x3ff48014 RTC_CNTL_TIME1_REG */ 0x40090155 <rtc_sleep+57>: memw 0x40090158 <rtc_sleep+60>: l32i.n a8, a8, 0 /* a8 = *(0x3ff48010) = 0x000124ee, time0 value */ 0x4009015a <rtc_sleep+62>: memw 0x4009015d <rtc_sleep+65>: l32i.n a12, a9, 0 /* a12 = *(0x3ff48014) = 0x0, time1 value */ 0x4009015f <rtc_sleep+67>: add.n a8, a3, a8 /* a8 += 2nd_param, 2nd_param is cycles_l */ 0x40090161 <rtc_sleep+69>: movi.n a9, 1 /* a9 = 1 */ 0x40090163 <rtc_sleep+71>: bltu a8, a3, 0x40090169 /* if (a8 < a3); branch */ 0x40090166 <rtc_sleep+74>: movi a9, 0 /* a9 = 0 */ 0x40090169 <rtc_sleep+77>: l32r a3, 0x4008ff64 /* a3 = *(0x4008ff64) = 0x3ff48004, RTC_CNTL_SLP_TIME0_REG */ 0x4009016c <rtc_sleep+80>: add.n a2, a2, a12 /* a2 = 1st_param_cycles_h + a12 */ 0x4009016e <rtc_sleep+82>: memw 0x40090171 <rtc_sleep+85>: s32i.n a8, a3, 0 /* update a8 into RTC_CNTL_SLP_TIME0_REG */ 0x40090173 <rtc_sleep+87>: l32r a8, 0x4008ff68 /* a8 = *(0x4008ff68) = 0x3ff48008, RTC_CNTL_SLP_TIME1_REG */ 0x40090176 <rtc_sleep+90>: l32r a3, 0x4008ff84 /* a3 = *(0x4008ff84) = 0x3ff48038, RTC_CNTL_WAKEUP_STATE_REG */ 0x40090179 <rtc_sleep+93>: add.n a9, a9, a2 /* a9 += a2, time1_val + cycles_h */ 0x4009017b <rtc_sleep+95>: memw 0x4009017e <rtc_sleep+98>: s32i.n a9, a8, 0 /* update a9 into RTC_CNTL_SLP_TIME1_REG */ 0x40090180 <rtc_sleep+100>: memw 0x40090183 <rtc_sleep+103>: l32i.n a8, a3, 0 /* a8 = *(0x3ff48038) = 0x00006000, read RTC_CNTL_WAKEUP_STATE_REG */ 0x40090185 <rtc_sleep+105>: l32r a2, 0x4008d188 /* a2 = *(0x4008d188) = 0xffc007ff */ 0x40090188 <rtc_sleep+108>: extui a4, a4, 0, 11 /* a4 is the 3rd param, extract the low 11 bits */ 0x4009018b <rtc_sleep+111>: and a2, a8, a2 /* a2 = RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff (only bitpos:[21:11]) */ 0x4009018e <rtc_sleep+114>: slli a4, a4, 11 /* a4 <<= 11 */ 0x40090191 <rtc_sleep+117>: or a4, a4, a2 /* a4 = wakeup_opt | (RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff) */ 0x40090194 <rtc_sleep+120>: l32r a2, 0x4008ff88 /* a2 = *(0x4008ff88) = 0x3ff48064, RTC_CNTL_SLP_REJECT_CONF_REG */ 0x40090197 <rtc_sleep+123>: memw 0x4009019a <rtc_sleep+126>: s32i.n a4, a3, 0 /* update the a4 into RTC_CNTL_WAKEUP_STATE_REG */ 0x4009019c <rtc_sleep+128>: l32r a3, 0x4008d1f0 /* a3 = *(0x4008d1f0) = 0x3ff48018, RTC_CNTL_STATE0_REG */ 0x4009019f <rtc_sleep+131>: memw 0x400901a2 <rtc_sleep+134>: s32i.n a5, a2, 0 /* update the a5 (4th param) into RTC_CNTL_SLP_REJECT_CONF_REG directly */ 0x400901a4 <rtc_sleep+136>: memw 0x400901a7 <rtc_sleep+139>: l32i.n a2, a3, 0 /* a2 = *(0x3ff48018) = 0x20300000, read RTC_CNTL_STATE0_REG */ 0x400901a9 <rtc_sleep+141>: l32r a9, 0x4008ffb8 /* a9 = *(0x4008ffb8) = 0x3ff48040, RTC_CNTL_INT_RAW_REG */ 0x400901ac <rtc_sleep+144>: or a11, a2, a11 /* a11 = RTC_CNTL_STATE0_REG | 0x8000 0000 */ 0x400901af <rtc_sleep+147>: memw 0x400901b2 <rtc_sleep+150>: s32i.n a11, a3, 0 /* update a11 into RTC_CNTL_STATE0_REG */ 0x400901b4 <rtc_sleep+152>: memw 0x400901b7 <rtc_sleep+155>: l32i.n a8, a9, 0 /* a8 = *(0x3ff48040) = 0x0000 0014, read RTC_CNTL_INT_RAW_REG */ 0x400901b9 <rtc_sleep+157>: extui a8, a8, 0, 2 /* a8 = extract the low 2 bits of a8 */ 0x400901bc <rtc_sleep+160>: beqz a8, 0x400901b4 /* if (a8 == 0); branch */ 0x400901bf <rtc_sleep+163>: memw 0x400901c2 <rtc_sleep+166>: l32i.n a2, a9, 0 /* a2 = *(0x3ff48040) = 0x0000 0014, read RTC_CNTL_INT_RAW_REG */ 0x400901c4 <rtc_sleep+168>: memw 0x400901c7 <rtc_sleep+171>: l32i.n a4, a10, 0 /* a4 = *(0x3ff48048) = 0x0, read RTC_CNTL_INT_CLR_REG */ 0x400901c9 <rtc_sleep+173>: movi.n a3, 3 /* a3 = 3 */ 0x400901cb <rtc_sleep+175>: or a3, a4, a3 /* a3 |= a4, set the clear bit of the reject_int and wakeup_int */ 0x400901ce <rtc_sleep+178>: memw 0x400901d1 <rtc_sleep+181>: s32i.n a3, a10, 0 /* update the a3 into RTC_CNTL_INT_CLR_REG */ 0x400901d3 <rtc_sleep+183>: extui a2, a2, 1, 1 /* a2 = (a2 >> 1) & 0x1, return a2 */ 0x400901d6 <rtc_sleep+186>: retw.n </source> <br><br>
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ESP32 RTC
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