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== Power Consumption == '''Light Sleep Mode:''' * The CPU is paused * WiFi/BT base-band and radio are Off * The RTC and ULP are running * Any wake-up events (MAC, host, RTC timer, or external interrupts) will wake up the chip * Current consumption is 800uA '''We are care of Deep-Sleep mode:''' * The ULP co-porcessor is powered on: 150uA current consumption * ULP sensor-monitored pattern: 25uA @ 1% duty * RTC timer + RTC memory: 10uA '''And Hibernate Mode:''' * The internal 8MHz oscillator and ULP coprocessor are disabled * The RTC recovery memory are power-down * Only one RTC timer on the slow clock and some RTC GPIOs are active. * The RTC timer or the RTC GPIOs can wake up the chip from the Hibernation mode * Power Consumption: 2.5uA <br> === Registers === <source lang=c> #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ /*description: RTC_REG force power up*/ #define RTC_CNTL_FORCE_PU_S 31 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ /*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ #define RTC_CNTL_FORCE_PD_S 30 /* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ /*description: RTC_DBOOST force power up*/ #define RTC_CNTL_DBOOST_FORCE_PU_S 29 /* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ /*description: RTC_DBOOST force power down*/ #define RTC_CNTL_DBOOST_FORCE_PD_S 28 /* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ /*description: RTC_DBIAS during wakeup*/ #define RTC_CNTL_DBIAS_WAK_S 25 /* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ /*description: RTC_DBIAS during sleep*/ #define RTC_CNTL_DBIAS_SLP_S 22 /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ /*description: SCK_DCAP*/ #define RTC_CNTL_SCK_DCAP_S 14 /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ /*description: DIG_REG_DBIAS during wakeup*/ #define RTC_CNTL_DIG_DBIAS_WAK_S 11 /* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */ /*description: DIG_REG_DBIAS during sleep*/ #define RTC_CNTL_DIG_DBIAS_SLP_S 8 /* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */ /*description: N/A*/ #define RTC_CNTL_SCK_DCAP_FORCE_S 7 #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ /*description: enable power down rtc_peri in sleep*/ #define RTC_CNTL_PD_EN_S 20 /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ /*description: rtc_peri force power up*/ #define RTC_CNTL_PWC_FORCE_PU_S 19 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ /*description: rtc_peri force power down*/ #define RTC_CNTL_PWC_FORCE_PD_S 18 /* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ /*description: enable power down RTC memory in sleep*/ #define RTC_CNTL_SLOWMEM_PD_EN_S 17 /* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ /*description: RTC memory force power up*/ #define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 /* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ /*description: RTC memory force power down*/ #define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 /* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ /*description: enable power down fast RTC memory in sleep*/ #define RTC_CNTL_FASTMEM_PD_EN_S 14 /* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ /*description: Fast RTC memory force power up*/ #define RTC_CNTL_FASTMEM_FORCE_PU_S 13 /* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ /*description: Fast RTC memory force power down*/ #define RTC_CNTL_FASTMEM_FORCE_PD_S 12 /* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ /*description: RTC memory force no PD*/ #define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 /* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ /*description: RTC memory force PD*/ #define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 /* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ /*description: 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ #define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 /* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ /*description: Fast RTC memory force no PD*/ #define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 /* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ /*description: Fast RTC memory force PD*/ #define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 /* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ /*description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC state machine*/ #define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 /* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ /*description: rtc_peri force no ISO*/ #define RTC_CNTL_FORCE_NOISO_S 5 /* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ /*description: rtc_peri force ISO*/ #define RTC_CNTL_FORCE_ISO_S 4 /* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ /*description: RTC memory force ISO*/ #define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 /* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ /*description: RTC memory force no ISO*/ #define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 /* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ /*description: Fast RTC memory force ISO*/ #define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 /* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ /*description: Fast RTC memory force no ISO*/ #define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 </source> <br><br>
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