ESP32 RTC
来自Jack's Lab
目录 |
1 Memory
1.1 FAST Memory
RTC FAST Memory 为 8 KB SRAM，其只能被 PRO_CPU 通过数据总线 0x3FF8_0000 ~ 0x3FF8_1FFF 读写，或被 PRO_CPU 通过指令总线 0x400C_0000~0x400C_1FFF 读写。与其他存储器不同，APP_CPU 不能访问 RTC FAST Memory
PRO_CPU 的这两段地址同序访问 RTC FAST Memory。即地址 0x3FF8_0000 与 0x400C_0000 访问到相同的 word，0x3FF8_0004与0x400C_0004访问到相同的word，0x3FF8_0008与0x400C_0008访问到相同的word， 以此类推。APP_CPU 的这两段地址不能访问到 RTC FAST Memory，也不能访问到其他任何目标
1.2 SLOW Memory
RTC SLOW Memory 为 8 KB SRAM，其可以被两个 CPU 通过数据总线与指令总线共用地址段 0x5000_0000 ~ 0x5000_1FFF 读写。
2 IO Register
components/esp32/include/soc/rtc_io_reg.h
3 Ctrl Register
components/esp32/include/soc/rtc_cntl_reg.h
4 Study
(gdb) x /16i ulp_cp_wr_reg 0x4008f690 <ulp_cp_wr_reg>: entry a1, 32 0x4008f693 <ulp_cp_wr_reg+3>: l32r a8, 0x40085078 0x4008f696 <ulp_cp_wr_reg+6>: slli a5, a5, 10 0x4008f699 <ulp_cp_wr_reg+9>: or a2, a2, a8 0x4008f69c <ulp_cp_wr_reg+12>: or a5, a2, a5 0x4008f69f <ulp_cp_wr_reg+15>: slli a4, a4, 18 0x4008f6a2 <ulp_cp_wr_reg+18>: or a5, a5, a4 0x4008f6a5 <ulp_cp_wr_reg+21>: slli a2, a3, 23 0x4008f6a8 <ulp_cp_wr_reg+24>: or a2, a5, a2 0x4008f6ab <ulp_cp_wr_reg+27>: retw.n 0x4008f6ad: ill 0x4008f6b0 <ulp_cp_rd_reg>: entry a1, 32 0x4008f6b3 <ulp_cp_rd_reg+3>: l32r a8, 0x4008043c 0x4008f6b6 <ulp_cp_rd_reg+6>: slli a4, a4, 18 0x4008f6b9 <ulp_cp_rd_reg+9>: or a2, a2, a8 0x4008f6bc <ulp_cp_rd_reg+12>: or a4, a2, a4 (gdb) x /16i ulp_cp_rd_reg 0x4008f6b0 <ulp_cp_rd_reg>: entry a1, 32 0x4008f6b3 <ulp_cp_rd_reg+3>: l32r a8, 0x4008043c 0x4008f6b6 <ulp_cp_rd_reg+6>: slli a4, a4, 18 0x4008f6b9 <ulp_cp_rd_reg+9>: or a2, a2, a8 0x4008f6bc <ulp_cp_rd_reg+12>: or a4, a2, a4 0x4008f6bf <ulp_cp_rd_reg+15>: slli a2, a3, 23 0x4008f6c2 <ulp_cp_rd_reg+18>: or a2, a4, a2 0x4008f6c5 <ulp_cp_rd_reg+21>: retw.n 0x4008f6c7: srli a3, a0, 6 0x4008f6ca <ulp_cp_wr_i2c+2>: f64norm a8, a1, a0, 1 0x4008f6cd <ulp_cp_wr_i2c+5>: .byte 0xff 0x4008f6ce <ulp_cp_wr_i2c+6>: slli a7, a7, 8 0x4008f6d1 <ulp_cp_wr_i2c+9>: or a4, a4, a8 0x4008f6d4 <ulp_cp_wr_i2c+12>: or a7, a4, a7 0x4008f6d7 <ulp_cp_wr_i2c+15>: slli a6, a6, 16 0x4008f6da <ulp_cp_wr_i2c+18>: or a7, a7, a6 (gdb) x /4x 0x40085078 0x40085078: 0x10000000 0xb100a136 0x5c0cfff1 0x8118c1a2 (gdb) x /4x 0x4008043c 0x4008043c: 0x20000000 0x40080000 0x3ffb29d0 0x3ffb0000 0x4008f6c8 <ulp_cp_wr_i2c>: entry a1, 32 0x4008f6cb <ulp_cp_wr_i2c+3>: l32r a8, 0x4008f3c4 0x4008f6ce <ulp_cp_wr_i2c+6>: slli a7, a7, 8 0x4008f6d1 <ulp_cp_wr_i2c+9>: or a4, a4, a8 0x4008f6d4 <ulp_cp_wr_i2c+12>: or a7, a4, a7 0x4008f6d7 <ulp_cp_wr_i2c+15>: slli a6, a6, 16 0x4008f6da <ulp_cp_wr_i2c+18>: or a7, a7, a6 0x4008f6dd <ulp_cp_wr_i2c+21>: slli a5, a5, 19 0x4008f6e0 <ulp_cp_wr_i2c+24>: or a7, a7, a5 0x4008f6e3 <ulp_cp_wr_i2c+27>: slli a3, a3, 22 0x4008f6e6 <ulp_cp_wr_i2c+30>: or a7, a7, a3 0x4008f6e9 <ulp_cp_wr_i2c+33>: slli a2, a2, 27 0x4008f6ec <ulp_cp_wr_i2c+36>: or a2, a7, a2 0x4008f6ef <ulp_cp_wr_i2c+39>: retw.n 0x4008f6f1: ill 0x4008f6f4 <ulp_cp_wait_delay>: entry a1, 32 0x4008f6f7 <ulp_cp_wait_delay+3>: l32r a8, 0x400805a0 0x4008f6fa <ulp_cp_wait_delay+6>: or a2, a2, a8 0x4008f6fd <ulp_cp_wait_delay+9>: retw.n (gdb) x /4x 0x4008f3c4 0x4008f3c4: 0x30000000 0x81004136 0x7780fffe 0x20448011 (gdb) x /4x 0x400805a0 0x400805a0: 0x40000000 0x3ff42008 0x00400000 0x3ffae270 (gdb) x /32i ulp_cp_meas_tsens 0x4008f700 <ulp_cp_meas_tsens>: entry a1, 32 0x4008f703 <ulp_cp_meas_tsens+3>: l32r a8, 0x4008f404 0x4008f706 <ulp_cp_meas_tsens+6>: slli a2, a2, 2 0x4008f709 <ulp_cp_meas_tsens+9>: or a3, a3, a8 0x4008f70c <ulp_cp_meas_tsens+12>: or a2, a3, a2 0x4008f70f <ulp_cp_meas_tsens+15>: retw.n 0x4008f711: ill 0x4008f714 <ulp_cp_meas_tsens_new>: entry a1, 32 0x4008f717 <ulp_cp_meas_tsens_new+3>: l32r a8, 0x4008f404 0x4008f71a <ulp_cp_meas_tsens_new+6>: slli a3, a3, 2 0x4008f71d <ulp_cp_meas_tsens_new+9>: or a4, a4, a8 0x4008f720 <ulp_cp_meas_tsens_new+12>: or a3, a4, a3 0x4008f723 <ulp_cp_meas_tsens_new+15>: slli a2, a2, 16 0x4008f726 <ulp_cp_meas_tsens_new+18>: or a2, a3, a2 0x4008f729 <ulp_cp_meas_tsens_new+21>: retw.n (gdb) x /4x 0x4008f404 0x4008f404: 0xa0000000 0x81004136 0x2200fffe 0x20338011 0x4008f72c <ulp_cp_meas_sar>: entry a1, 32 0x4008f72f <ulp_cp_meas_sar+3>: l32r a8, 0x4008f41c 0x4008f732 <ulp_cp_meas_sar+6>: slli a4, a4, 2 0x4008f735 <ulp_cp_meas_sar+9>: or a5, a5, a8 0x4008f738 <ulp_cp_meas_sar+12>: or a4, a5, a4 0x4008f73b <ulp_cp_meas_sar+15>: slli a3, a3, 6 0x4008f73e <ulp_cp_meas_sar+18>: or a4, a4, a3 0x4008f741 <ulp_cp_meas_sar+21>: slli a2, a2, 8 0x4008f744 <ulp_cp_meas_sar+24>: or a2, a4, a2 0x4008f747 <ulp_cp_meas_sar+27>: retw.n 0x4008f749: ill 0x4008f74c <ulp_cp_sar_wr_mem>: entry a1, 32 0x4008f74f <ulp_cp_sar_wr_mem+3>: l32r a8, 0x400804d8 0x4008f752 <ulp_cp_sar_wr_mem+6>: slli a3, a3, 2 0x4008f755 <ulp_cp_sar_wr_mem+9>: or a4, a4, a8 0x4008f758 <ulp_cp_sar_wr_mem+12>: or a3, a4, a3 0x4008f75b <ulp_cp_sar_wr_mem+15>: slli a2, a2, 7 0x4008f75e <ulp_cp_sar_wr_mem+18>: or a2, a3, a2 0x4008f761 <ulp_cp_sar_wr_mem+21>: retw.n 0x4008f763: ill (gdb) x /4x 0x4008f41c 0x4008f41c: 0x50000000 0x81004136 0x4040fffe 0x14505034 (gdb) x /4x 0x400804d8 0x400804d8: 0x60000000 0x00040023 0xc0000000 0x3ffb2b48
