ESP32 RTC
来自Jack's Lab
1 Memory
1.1 FAST Memory
RTC FAST Memory 为 8 KB SRAM，其只能被 PRO_CPU 通过数据总线 0x3FF8_0000 ~ 0x3FF8_1FFF 读写，或被 PRO_CPU 通过指令总线 0x400C_0000~0x400C_1FFF 读写。与其他存储器不同，APP_CPU 不能访问 RTC FAST Memory
PRO_CPU 的这两段地址同序访问 RTC FAST Memory。即地址 0x3FF8_0000 与 0x400C_0000 访问到相同的 word，0x3FF8_0004与0x400C_0004访问到相同的word，0x3FF8_0008与0x400C_0008访问到相同的word， 以此类推。APP_CPU 的这两段地址不能访问到 RTC FAST Memory，也不能访问到其他任何目标
1.2 SLOW Memory
RTC SLOW Memory 为 8 KB SRAM，其可以被两个 CPU 通过数据总线与指令总线共用地址段 0x5000_0000 ~ 0x5000_1FFF 读写。
2 Register
2.1 IO
components/esp32/include/soc/rtc_io_reg.h
#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) #define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) #define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) #define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc) #define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) #define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) #define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) #define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c) #define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) #define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) #define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) #define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c) #define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) #define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) #define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) #define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c) #define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) #define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) #define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) #define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c) #define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) #define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) #define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) #define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c) #define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) #define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) #define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) #define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c) #define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x70) #define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74) #define RTC_IO_HALL_SENS_REG (DR_REG_RTCIO_BASE + 0x78) #define RTC_IO_SENSOR_PADS_REG (DR_REG_RTCIO_BASE + 0x7c) #define RTC_IO_ADC_PAD_REG (DR_REG_RTCIO_BASE + 0x80) #define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x84) #define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x88) #define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) #define RTC_IO_TOUCH_CFG_REG (DR_REG_RTCIO_BASE + 0x90) #define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x94) #define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x98) #define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c) #define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0) #define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4) #define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8) #define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac) #define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0) #define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4) #define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xb8) #define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc) #define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0) #define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xc4) #define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0xc8)
2.2 Ctrl
components/esp32/include/soc/rtc_cntl_reg.h
#define DR_REG_RTCCNTL_BASE 0x3ff48000 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) #define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10) #define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14) #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) #define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) #define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) #define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30) #define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x34) #define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) #define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x3c) #define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x40) #define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x44) #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48) #define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x4c) #define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50) #define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x54) #define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x58) #define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) #define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) #define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) #define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) #define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) #define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) #define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) #define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) #define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) #define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) #define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x94) #define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x98) #define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x9c) #define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa0) #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xa4) #define RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0xa8) #define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xac) #define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0) #define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4) #define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xb8) #define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xbc) #define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xc0) #define RTC_CNTL_DIAG1_REG (DR_REG_RTCCNTL_BASE + 0xc4) #define RTC_CNTL_HOLD_FORCE_REG (DR_REG_RTCCNTL_BASE + 0xc8) #define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) #define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) #define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xd4) #define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4) #define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4) #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c)
3 API
#define DEEP_SLEEP_PD_NORMAL BIT(0) /* Base deep sleep mode */ #define DEEP_SLEEP_PD_RTC_PERIPH BIT(1) /* Power down RTC peripherals */ #define DEEP_SLEEP_PD_RTC_SLOW_MEM BIT(2) /* Power down RTC SLOW memory */ #define DEEP_SLEEP_PD_RTC_FAST_MEM BIT(3) /* Power down RTC FAST memory */ /* * @brief Prepare for entering sleep mode * @param deep_slp DEEP_SLEEP_PD_ flags combined with OR (DEEP_SLEEP_PD_NORMAL must be included) * @param cpu_lp_mode for deep sleep, should be 0 */ void rtc_slp_prep_lite(uint32_t deep_slp, uint32_t cpu_lp_mode); #define RTC_EXT_EVENT0_TRIG BIT(0) #define RTC_EXT_EVENT1_TRIG BIT(1) #define RTC_GPIO_TRIG BIT(2) #define RTC_TIMER_EXPIRE BIT(3) #define RTC_SDIO_TRIG BIT(4) #define RTC_MAC_TRIG BIT(5) #define RTC_UART0_TRIG BIT(6) #define RTC_UART1_TRIG BIT(7) #define RTC_TOUCH_TRIG BIT(8) #define RTC_SAR_TRIG BIT(9) #define RTC_BT_TRIG BIT(10) /* * @brief Enter sleep mode for given number of cycles * @param cycles_h higher 32 bit part of number of slow clock cycles * @param cycles_l lower 32 bit part of number of slow clock cycles * @param wakeup_opt wake up reason to enable (RTC_xxx_TRIG flags combined with OR) * @param reject_opt reserved, should be 0 * @return TBD */ uint32_t rtc_sleep(uint32_t cycles_h, uint32_t cycles_l, uint32_t wakeup_opt, uint32_t reject_opt);
4 ULP CP Inst
4.1 ulp_cp_wr_reg
(gdb) x /16i ulp_cp_wr_reg 0x4008f690 <ulp_cp_wr_reg>: entry a1, 32 0x4008f693 <ulp_cp_wr_reg+3>: l32r a8, 0x40085078 0x4008f696 <ulp_cp_wr_reg+6>: slli a5, a5, 10 0x4008f699 <ulp_cp_wr_reg+9>: or a2, a2, a8 0x4008f69c <ulp_cp_wr_reg+12>: or a5, a2, a5 0x4008f69f <ulp_cp_wr_reg+15>: slli a4, a4, 18 0x4008f6a2 <ulp_cp_wr_reg+18>: or a5, a5, a4 0x4008f6a5 <ulp_cp_wr_reg+21>: slli a2, a3, 23 0x4008f6a8 <ulp_cp_wr_reg+24>: or a2, a5, a2 0x4008f6ab <ulp_cp_wr_reg+27>: retw.n 0x4008f6ad: ill (gdb) x /4x 0x40085078 0x40085078: 0x10000000 0xb100a136 0x5c0cfff1 0x8118c1a2
4.2 ulp_cp_rd_reg
0x4008f6b0 <ulp_cp_rd_reg>: entry a1, 32 0x4008f6b3 <ulp_cp_rd_reg+3>: l32r a8, 0x4008043c 0x4008f6b6 <ulp_cp_rd_reg+6>: slli a4, a4, 18 0x4008f6b9 <ulp_cp_rd_reg+9>: or a2, a2, a8 0x4008f6bc <ulp_cp_rd_reg+12>: or a4, a2, a4 0x4008f6bf <ulp_cp_rd_reg+15>: slli a2, a3, 23 0x4008f6c2 <ulp_cp_rd_reg+18>: or a2, a4, a2 0x4008f6c5 <ulp_cp_rd_reg+21>: retw.n (gdb) x /4x 0x4008043c 0x4008043c: 0x20000000 0x40080000 0x3ffb29d0 0x3ffb0000
4.3 ulp_cp_wr_i2c
0x4008f6c8 <ulp_cp_wr_i2c>: entry a1, 32 0x4008f6cb <ulp_cp_wr_i2c+3>: l32r a8, 0x4008f3c4 0x4008f6ce <ulp_cp_wr_i2c+6>: slli a7, a7, 8 0x4008f6d1 <ulp_cp_wr_i2c+9>: or a4, a4, a8 0x4008f6d4 <ulp_cp_wr_i2c+12>: or a7, a4, a7 0x4008f6d7 <ulp_cp_wr_i2c+15>: slli a6, a6, 16 0x4008f6da <ulp_cp_wr_i2c+18>: or a7, a7, a6 0x4008f6dd <ulp_cp_wr_i2c+21>: slli a5, a5, 19 0x4008f6e0 <ulp_cp_wr_i2c+24>: or a7, a7, a5 0x4008f6e3 <ulp_cp_wr_i2c+27>: slli a3, a3, 22 0x4008f6e6 <ulp_cp_wr_i2c+30>: or a7, a7, a3 0x4008f6e9 <ulp_cp_wr_i2c+33>: slli a2, a2, 27 0x4008f6ec <ulp_cp_wr_i2c+36>: or a2, a7, a2 0x4008f6ef <ulp_cp_wr_i2c+39>: retw.n 0x4008f6f1: ill (gdb) x /4x 0x4008f3c4 0x4008f3c4: 0x30000000 0x81004136 0x7780fffe 0x20448011
4.4 ulp_cp_wait_delay
0x4008f6f4 <ulp_cp_wait_delay>: entry a1, 32 0x4008f6f7 <ulp_cp_wait_delay+3>: l32r a8, 0x400805a0 0x4008f6fa <ulp_cp_wait_delay+6>: or a2, a2, a8 0x4008f6fd <ulp_cp_wait_delay+9>: retw.n (gdb) x /4x 0x400805a0 0x400805a0: 0x40000000 0x3ff42008 0x00400000 0x3ffae270
4.5 ulp_cp_meas_tsens
(gdb) x /32i ulp_cp_meas_tsens 0x4008f700 <ulp_cp_meas_tsens>: entry a1, 32 0x4008f703 <ulp_cp_meas_tsens+3>: l32r a8, 0x4008f404 0x4008f706 <ulp_cp_meas_tsens+6>: slli a2, a2, 2 0x4008f709 <ulp_cp_meas_tsens+9>: or a3, a3, a8 0x4008f70c <ulp_cp_meas_tsens+12>: or a2, a3, a2 0x4008f70f <ulp_cp_meas_tsens+15>: retw.n 0x4008f711: ill (gdb) x /4x 0x4008f404 0x4008f404: 0xa0000000 0x81004136 0x2200fffe 0x20338011
4.6 ulp_cp_meas_tsens_new
0x4008f714 <ulp_cp_meas_tsens_new>: entry a1, 32 0x4008f717 <ulp_cp_meas_tsens_new+3>: l32r a8, 0x4008f404 0x4008f71a <ulp_cp_meas_tsens_new+6>: slli a3, a3, 2 0x4008f71d <ulp_cp_meas_tsens_new+9>: or a4, a4, a8 0x4008f720 <ulp_cp_meas_tsens_new+12>: or a3, a4, a3 0x4008f723 <ulp_cp_meas_tsens_new+15>: slli a2, a2, 16 0x4008f726 <ulp_cp_meas_tsens_new+18>: or a2, a3, a2 0x4008f729 <ulp_cp_meas_tsens_new+21>: retw.n (gdb) x /4x 0x4008f404 0x4008f404: 0xa0000000 0x81004136 0x2200fffe 0x20338011
4.7 ulp_cp_meas_sar
0x4008f72c <ulp_cp_meas_sar>: entry a1, 32 0x4008f72f <ulp_cp_meas_sar+3>: l32r a8, 0x4008f41c 0x4008f732 <ulp_cp_meas_sar+6>: slli a4, a4, 2 0x4008f735 <ulp_cp_meas_sar+9>: or a5, a5, a8 0x4008f738 <ulp_cp_meas_sar+12>: or a4, a5, a4 0x4008f73b <ulp_cp_meas_sar+15>: slli a3, a3, 6 0x4008f73e <ulp_cp_meas_sar+18>: or a4, a4, a3 0x4008f741 <ulp_cp_meas_sar+21>: slli a2, a2, 8 0x4008f744 <ulp_cp_meas_sar+24>: or a2, a4, a2 0x4008f747 <ulp_cp_meas_sar+27>: retw.n 0x4008f749: ill (gdb) x /4x 0x4008f41c 0x4008f41c: 0x50000000 0x81004136 0x4040fffe 0x14505034
4.8 ulp_cp_sar_wr_mem
0x4008f74c <ulp_cp_sar_wr_mem>: entry a1, 32 0x4008f74f <ulp_cp_sar_wr_mem+3>: l32r a8, 0x400804d8 0x4008f752 <ulp_cp_sar_wr_mem+6>: slli a3, a3, 2 0x4008f755 <ulp_cp_sar_wr_mem+9>: or a4, a4, a8 0x4008f758 <ulp_cp_sar_wr_mem+12>: or a3, a4, a3 0x4008f75b <ulp_cp_sar_wr_mem+15>: slli a2, a2, 7 0x4008f75e <ulp_cp_sar_wr_mem+18>: or a2, a3, a2 0x4008f761 <ulp_cp_sar_wr_mem+21>: retw.n 0x4008f763: ill (gdb) x /4x 0x400804d8 0x400804d8: 0x60000000 0x00040023 0xc0000000 0x3ffb2b48
4.9 ulp_cp_sar_wr_mem_set_offset
0x4008f768 <ulp_cp_sar_wr_mem_set_offset>: entry a1, 32 0x4008f76b <ulp_cp_sar_wr_mem_set_offset+3>: l32r a8, 0x4008f764 0x4008f76e <ulp_cp_sar_wr_mem_set_offset+6>: slli a2, a2, 10 0x4008f771 <ulp_cp_sar_wr_mem_set_offset+9>: or a2, a2, a8 0x4008f774 <ulp_cp_sar_wr_mem_set_offset+12>: retw.n (gdb) x /1x 0x4008f764 0x4008f764: 0x64000000
4.10 ulp_cp_sar_wr_mem_man2
0x4008f790 <ulp_cp_sar_wr_mem_man2>: entry a1, 32 0x4008f793 <ulp_cp_sar_wr_mem_man2+3>: l32r a8, 0x4008f778 0x4008f796 <ulp_cp_sar_wr_mem_man2+6>: slli a3, a3, 2 0x4008f799 <ulp_cp_sar_wr_mem_man2+9>: or a4, a4, a8 0x4008f79c <ulp_cp_sar_wr_mem_man2+12>: or a3, a4, a3 0x4008f79f <ulp_cp_sar_wr_mem_man2+15>: slli a2, a2, 10 0x4008f7a2 <ulp_cp_sar_wr_mem_man2+18>: or a2, a3, a2 0x4008f7a5 <ulp_cp_sar_wr_mem_man2+21>: retw.n (gdb) x /1x 0x4008f778 0x4008f778: 0x68000000
4.11 ulp_cp_rd_mem
0x4008f7ac <ulp_cp_rd_mem>: entry a1, 32 0x4008f7af <ulp_cp_rd_mem+3>: l32r a8, 0x4008f7a8 0x4008f7b2 <ulp_cp_rd_mem+6>: slli a2, a2, 10 0x4008f7b5 <ulp_cp_rd_mem+9>: or a3, a3, a8 0x4008f7b8 <ulp_cp_rd_mem+12>: or a2, a3, a2 0x4008f7bb <ulp_cp_rd_mem+15>: retw.n 0x4008f7bd: ill 0x4008f7c0 <ulp_cp_rd_mem2>: entry a1, 32 0x4008f7c3 <ulp_cp_rd_mem2+3>: l32r a8, 0x4008f7a8 0x4008f7c6 <ulp_cp_rd_mem2+6>: slli a3, a3, 2 0x4008f7c9 <ulp_cp_rd_mem2+9>: or a4, a4, a8 0x4008f7cc <ulp_cp_rd_mem2+12>: or a3, a4, a3 0x4008f7cf <ulp_cp_rd_mem2+15>: slli a2, a2, 10 0x4008f7d2 <ulp_cp_rd_mem2+18>: or a2, a3, a2 0x4008f7d5 <ulp_cp_rd_mem2+21>: retw.n (gdb) x /1x 0x4008f7a8 0x4008f7a8: 0xd0000000
4.12 ulp_cp_alu_reg
(gdb) x /12i ulp_cp_alu_reg 0x4008f7d8 <ulp_cp_alu_reg>: entry a1, 32 0x4008f7db <ulp_cp_alu_reg+3>: l32r a8, 0x4008f46c 0x4008f7de <ulp_cp_alu_reg+6>: slli a4, a4, 2 0x4008f7e1 <ulp_cp_alu_reg+9>: or a5, a5, a8 0x4008f7e4 <ulp_cp_alu_reg+12>: or a4, a5, a4 0x4008f7e7 <ulp_cp_alu_reg+15>: slli a3, a3, 4 0x4008f7ea <ulp_cp_alu_reg+18>: or a4, a4, a3 0x4008f7ed <ulp_cp_alu_reg+21>: slli a2, a2, 21 0x4008f7f0 <ulp_cp_alu_reg+24>: or a2, a4, a2 0x4008f7f3 <ulp_cp_alu_reg+27>: retw.n 0x4008f7f5: ill (gdb) x /1x 0x4008f46c 0x4008f46c: 0x70000000
4.13 ulp_cp_alu_im
0x4008f7f8 <ulp_cp_alu_im>: entry a1, 32 0x4008f7fb <ulp_cp_alu_im+3>: l32r a8, 0x4008f490 0x4008f7fe <ulp_cp_alu_im+6>: slli a4, a4, 2 0x4008f801 <ulp_cp_alu_im+9>: or a5, a5, a8 0x4008f804 <ulp_cp_alu_im+12>: slli a2, a2, 4 0x4008f807 <ulp_cp_alu_im+15>: or a8, a5, a4 0x4008f80a <ulp_cp_alu_im+18>: or a8, a8, a2 0x4008f80d <ulp_cp_alu_im+21>: slli a2, a3, 21 0x4008f810 <ulp_cp_alu_im+24>: or a2, a8, a2 0x4008f813 <ulp_cp_alu_im+27>: retw.n 0x4008f815: ill 0x4008f818: ill (gdb) x /1x 0x4008f490 0x4008f490: 0x72000000
4.14 ulp_cp_alu_im
0x4008f7f8 <ulp_cp_alu_im>: entry a1, 32 0x4008f7fb <ulp_cp_alu_im+3>: l32r a8, 0x4008f490 0x4008f7fe <ulp_cp_alu_im+6>: slli a4, a4, 2 0x4008f801 <ulp_cp_alu_im+9>: or a5, a5, a8 0x4008f804 <ulp_cp_alu_im+12>: slli a2, a2, 4 0x4008f807 <ulp_cp_alu_im+15>: or a8, a5, a4 0x4008f80a <ulp_cp_alu_im+18>: or a8, a8, a2 0x4008f80d <ulp_cp_alu_im+21>: slli a2, a3, 21 0x4008f810 <ulp_cp_alu_im+24>: or a2, a8, a2 0x4008f813 <ulp_cp_alu_im+27>: retw.n 0x4008f815: ill 0x4008f818: ill
4.15 ulp_cp_stage_cnt_alu
0x4008f81c <ulp_cp_stage_cnt_alu>: entry a1, 32 0x4008f81f <ulp_cp_stage_cnt_alu+3>: l32r a8, 0x4008f818 0x4008f822 <ulp_cp_stage_cnt_alu+6>: slli a2, a2, 4 0x4008f825 <ulp_cp_stage_cnt_alu+9>: or a8, a2, a8 0x4008f828 <ulp_cp_stage_cnt_alu+12>: slli a2, a3, 21 0x4008f82b <ulp_cp_stage_cnt_alu+15>: or a2, a8, a2 0x4008f82e <ulp_cp_stage_cnt_alu+18>: retw.n (gdb) x /1x 0x4008f818 0x4008f818: 0x74000000
4.16 ulp_cp_force_branch
0x4008f830 <ulp_cp_force_branch>: entry a1, 32 0x4008f833 <ulp_cp_force_branch+3>: l32r a8, 0x40080690 0x4008f836 <ulp_cp_force_branch+6>: slli a2, a2, 17 0x4008f839 <ulp_cp_force_branch+9>: or a2, a2, a8 0x4008f83c <ulp_cp_force_branch+12>: retw.n (gdb) x /1x 0x40080690 0x40080690: 0x80000000
4.17 ulp_cp_jump
0x4008f840 <ulp_cp_jump>: entry a1, 32 0x4008f843 <ulp_cp_jump+3>: l32r a8, 0x40080690 0x4008f846 <ulp_cp_jump+6>: slli a4, a4, 2 0x4008f849 <ulp_cp_jump+9>: or a5, a5, a8 0x4008f84c <ulp_cp_jump+12>: or a4, a5, a4 0x4008f84f <ulp_cp_jump+15>: slli a2, a2, 22 0x4008f852 <ulp_cp_jump+18>: or a2, a4, a2 0x4008f855 <ulp_cp_jump+21>: retw.n
4.18 ulp_cp_reg0_branch
0x4008f858 <ulp_cp_reg0_branch>: entry a1, 32 0x4008f85b <ulp_cp_reg0_branch+3>: l32r a8, 0x4008f4c0 0x4008f85e <ulp_cp_reg0_branch+6>: slli a3, a3, 16 0x4008f861 <ulp_cp_reg0_branch+9>: or a4, a4, a8 0x4008f864 <ulp_cp_reg0_branch+12>: or a3, a4, a3 0x4008f867 <ulp_cp_reg0_branch+15>: slli a2, a2, 17 0x4008f86a <ulp_cp_reg0_branch+18>: or a2, a3, a2 0x4008f86d <ulp_cp_reg0_branch+21>: retw.n (gdb) x /1x 0x4008f4c0 0x4008f4c0: 0x82000000
4.19 ulp_cp_stage_cnt_br
0x4008f870 <ulp_cp_stage_cnt_br>: entry a1, 32 0x4008f873 <ulp_cp_stage_cnt_br+3>: l32r a8, 0x400807d0 0x4008f876 <ulp_cp_stage_cnt_br+6>: slli a3, a3, 15 0x4008f879 <ulp_cp_stage_cnt_br+9>: or a4, a4, a8 0x4008f87c <ulp_cp_stage_cnt_br+12>: or a3, a4, a3 0x4008f87f <ulp_cp_stage_cnt_br+15>: slli a2, a2, 17 0x4008f882 <ulp_cp_stage_cnt_br+18>: or a2, a3, a2 0x4008f885 <ulp_cp_stage_cnt_br+21>: retw.n (gdb) x /1x 0x400807d0 0x400807d0: 0x84000000
4.20 ulp_cp_cpu_wakeup
0x4008f888 <ulp_cp_cpu_wakeup>: entry a1, 32 0x4008f88b <ulp_cp_cpu_wakeup+3>: l32r a8, 0x4008f4fc 0x4008f88e <ulp_cp_cpu_wakeup+6>: or a2, a2, a8 0x4008f891 <ulp_cp_cpu_wakeup+9>: retw.n (gdb) x /1x 0x4008f4fc 0x4008f4fc: 0x90000000
4.21 ulp_cp_sleep_cyc_sel
0x4008f894 <ulp_cp_sleep_cyc_sel>: entry a1, 32 0x4008f897 <ulp_cp_sleep_cyc_sel+3>: l32r a8, 0x4008f50c 0x4008f89a <ulp_cp_sleep_cyc_sel+6>: or a2, a2, a8 0x4008f89d <ulp_cp_sleep_cyc_sel+9>: retw.n (gdb) x /1x 0x4008f50c 0x4008f50c: 0x92000000
4.22 ulp_cp_meas_end
0x4008f8a0 <ulp_cp_meas_end>: entry a1, 32 0x4008f8a3 <ulp_cp_meas_end+3>: l32r a2, 0x4008f51c 0x4008f8a6 <ulp_cp_meas_end+6>: retw.n (gdb) x /1x 0x4008f51c 0x4008f51c: 0xb0000000
5 RTC CMD Inst
5.1 rtc_cmd_wr_reg
0x4008f378 <rtc_cmd_wr_reg>: entry a1, 32 0x4008f37b <rtc_cmd_wr_reg+3>: l32r a9, 0x40085078 0x4008f37e <rtc_cmd_wr_reg+6>: extui a5, a5, 0, 8 0x4008f381 <rtc_cmd_wr_reg+9>: slli a8, a5, 10 0x4008f384 <rtc_cmd_wr_reg+12>: extui a4, a4, 0, 5 0x4008f387 <rtc_cmd_wr_reg+15>: or a8, a8, a9 0x4008f38a <rtc_cmd_wr_reg+18>: slli a9, a4, 18 0x4008f38d <rtc_cmd_wr_reg+21>: or a8, a8, a9 0x4008f390 <rtc_cmd_wr_reg+24>: extui a3, a3, 0, 5 0x4008f393 <rtc_cmd_wr_reg+27>: extui a2, a2, 0, 10 0x4008f396 <rtc_cmd_wr_reg+30>: or a2, a8, a2 0x4008f399 <rtc_cmd_wr_reg+33>: slli a4, a3, 23 0x4008f39c <rtc_cmd_wr_reg+36>: or a2, a2, a4 0x4008f39f <rtc_cmd_wr_reg+39>: retw.n 0x4008f3a1: ill (gdb) x /1x 0x40085078 0x40085078: 0x10000000
5.2 rtc_cmd_rd_reg
0x4008f3a4 <rtc_cmd_rd_reg>: entry a1, 32 0x4008f3a7 <rtc_cmd_rd_reg+3>: l32r a9, 0x4008043c 0x4008f3aa <rtc_cmd_rd_reg+6>: extui a4, a4, 0, 5 0x4008f3ad <rtc_cmd_rd_reg+9>: slli a8, a4, 18 0x4008f3b0 <rtc_cmd_rd_reg+12>: or a8, a8, a9 0x4008f3b3 <rtc_cmd_rd_reg+15>: extui a3, a3, 0, 5 0x4008f3b6 <rtc_cmd_rd_reg+18>: extui a2, a2, 0, 10 0x4008f3b9 <rtc_cmd_rd_reg+21>: or a2, a8, a2 0x4008f3bc <rtc_cmd_rd_reg+24>: slli a9, a3, 23 0x4008f3bf <rtc_cmd_rd_reg+27>: or a2, a2, a9 0x4008f3c2 <rtc_cmd_rd_reg+30>: retw.n 0x4008f3c4: ill (gdb) x /1x 0x4008043c 0x4008043c: 0x20000000
5.3 rtc_cmd_wr_i2c
0x4008f3c8 <rtc_cmd_wr_i2c>: entry a1, 32 0x4008f3cb <rtc_cmd_wr_i2c+3>: l32r a8, 0x4008f3c4 0x4008f3ce <rtc_cmd_wr_i2c+6>: slli a7, a7, 8 0x4008f3d1 <rtc_cmd_wr_i2c+9>: or a4, a4, a8 0x4008f3d4 <rtc_cmd_wr_i2c+12>: or a7, a4, a7 0x4008f3d7 <rtc_cmd_wr_i2c+15>: slli a6, a6, 16 0x4008f3da <rtc_cmd_wr_i2c+18>: or a7, a7, a6 0x4008f3dd <rtc_cmd_wr_i2c+21>: slli a5, a5, 19 0x4008f3e0 <rtc_cmd_wr_i2c+24>: or a7, a7, a5 0x4008f3e3 <rtc_cmd_wr_i2c+27>: slli a3, a3, 22 0x4008f3e6 <rtc_cmd_wr_i2c+30>: or a7, a7, a3 0x4008f3e9 <rtc_cmd_wr_i2c+33>: slli a2, a2, 27 0x4008f3ec <rtc_cmd_wr_i2c+36>: or a2, a7, a2 0x4008f3ef <rtc_cmd_wr_i2c+39>: retw.n 0x4008f3f1: ill (gdb) x /1x 0x4008f3c4 0x4008f3c4: 0x30000000
5.4 rtc_cmd_wait_delay
0x4008f3f4 <rtc_cmd_wait_delay>: entry a1, 32 0x4008f3f7 <rtc_cmd_wait_delay+3>: l32r a8, 0x400805a0 0x4008f3fa <rtc_cmd_wait_delay+6>: extui a2, a2, 0, 16 0x4008f3fd <rtc_cmd_wait_delay+9>: or a2, a2, a8 0x4008f400 <rtc_cmd_wait_delay+12>: retw.n 0x4008f402: ill (gdb) x /1x 0x400805a0 0x400805a0: 0x40000000
5.5 rtc_cmd_meas_tsens
0x4008f408 <rtc_cmd_meas_tsens>: entry a1, 32 0x4008f40b <rtc_cmd_meas_tsens+3>: l32r a8, 0x4008f404 0x4008f40e <rtc_cmd_meas_tsens+6>: slli a2, a2, 16 0x4008f411 <rtc_cmd_meas_tsens+9>: or a3, a3, a8 0x4008f414 <rtc_cmd_meas_tsens+12>: or a2, a3, a2 0x4008f417 <rtc_cmd_meas_tsens+15>: retw.n 0x4008f419: ill (gdb) x /1x 0x4008f404 0x4008f404: 0xa0000000
5.6 rtc_cmd_meas_saradc
0x4008f420 <rtc_cmd_meas_saradc>: entry a1, 32 0x4008f423 <rtc_cmd_meas_saradc+3>: l32r a8, 0x4008f41c 0x4008f426 <rtc_cmd_meas_saradc+6>: extui a4, a4, 0, 4 0x4008f429 <rtc_cmd_meas_saradc+9>: extui a5, a5, 0, 2 0x4008f42c <rtc_cmd_meas_saradc+12>: or a5, a5, a8 0x4008f42f <rtc_cmd_meas_saradc+15>: extui a3, a3, 0, 2 0x4008f432 <rtc_cmd_meas_saradc+18>: slli a8, a4, 2 0x4008f435 <rtc_cmd_meas_saradc+21>: or a5, a5, a8 0x4008f438 <rtc_cmd_meas_saradc+24>: slli a3, a3, 6 0x4008f43b <rtc_cmd_meas_saradc+27>: extui a2, a2, 0, 16 0x4008f43e <rtc_cmd_meas_saradc+30>: or a5, a5, a3 0x4008f441 <rtc_cmd_meas_saradc+33>: slli a2, a2, 8 0x4008f444 <rtc_cmd_meas_saradc+36>: or a2, a5, a2 0x4008f447 <rtc_cmd_meas_saradc+39>: retw.n 0x4008f449: ill (gdb) x /1x 0x4008f41c 0x4008f41c: 0x50000000
5.7 rtc_cmd_write_mem
0x4008f44c <rtc_cmd_write_mem>: entry a1, 32 0x4008f44f <rtc_cmd_write_mem+3>: l32r a9, 0x400804d8 0x4008f452 <rtc_cmd_write_mem+6>: extui a4, a4, 0, 2 0x4008f455 <rtc_cmd_write_mem+9>: extui a3, a3, 0, 5 0x4008f458 <rtc_cmd_write_mem+12>: or a4, a4, a9 0x4008f45b <rtc_cmd_write_mem+15>: extui a2, a2, 0, 3 0x4008f45e <rtc_cmd_write_mem+18>: slli a3, a3, 2 0x4008f461 <rtc_cmd_write_mem+21>: or a3, a4, a3 0x4008f464 <rtc_cmd_write_mem+24>: slli a2, a2, 7 0x4008f467 <rtc_cmd_write_mem+27>: or a2, a3, a2 0x4008f46a <rtc_cmd_write_mem+30>: retw.n (gdb) x /1x 0x400804d8 0x400804d8: 0x60000000
5.8 rtc_cmd_reg0_alu
0x4008f470 <rtc_cmd_reg0_alu>: entry a1, 32 0x4008f473 <rtc_cmd_reg0_alu+3>: l32r a9, 0x4008f46c 0x4008f476 <rtc_cmd_reg0_alu+6>: extui a4, a4, 0, 2 0x4008f479 <rtc_cmd_reg0_alu+9>: extui a3, a3, 0, 4 0x4008f47c <rtc_cmd_reg0_alu+12>: or a4, a4, a9 0x4008f47f <rtc_cmd_reg0_alu+15>: extui a2, a2, 0, 8 0x4008f482 <rtc_cmd_reg0_alu+18>: slli a3, a3, 2 0x4008f485 <rtc_cmd_reg0_alu+21>: or a3, a4, a3 0x4008f488 <rtc_cmd_reg0_alu+24>: slli a2, a2, 6 0x4008f48b <rtc_cmd_reg0_alu+27>: or a2, a3, a2 0x4008f48e <rtc_cmd_reg0_alu+30>: retw.n (gdb) x /1x 0x4008f46c 0x4008f46c: 0x70000000
5.9 rtc_cmd_stage_alu
0x4008f494 <rtc_cmd_stage_alu>: entry a1, 32 0x4008f497 <rtc_cmd_stage_alu+3>: l32r a9, 0x4008f490 0x4008f49a <rtc_cmd_stage_alu+6>: extui a3, a3, 0, 4 0x4008f49d <rtc_cmd_stage_alu+9>: extui a2, a2, 0, 4 0x4008f4a0 <rtc_cmd_stage_alu+12>: slli a3, a3, 2 0x4008f4a3 <rtc_cmd_stage_alu+15>: or a3, a3, a9 0x4008f4a6 <rtc_cmd_stage_alu+18>: slli a2, a2, 6 0x4008f4a9 <rtc_cmd_stage_alu+21>: or a2, a3, a2 0x4008f4ac <rtc_cmd_stage_alu+24>: retw.n (gdb) x /1x 0x4008f490 0x4008f490: 0x72000000
5.10 rtc_cmd_force_branch
0x4008f4b0 <rtc_cmd_force_branch>: entry a1, 32 0x4008f4b3 <rtc_cmd_force_branch+3>: l32r a8, 0x40080690 0x4008f4b6 <rtc_cmd_force_branch+6>: slli a2, a2, 17 0x4008f4b9 <rtc_cmd_force_branch+9>: or a2, a2, a8 0x4008f4bc <rtc_cmd_force_branch+12>: retw.n (gdb) x /1x 0x40080690 0x40080690: 0x80000000
5.11 rtc_cmd_reg0_branch
0x4008f4c4 <rtc_cmd_reg0_branch>: entry a1, 32 0x4008f4c7 <rtc_cmd_reg0_branch+3>: l32r a8, 0x4008f4c0 0x4008f4ca <rtc_cmd_reg0_branch+6>: slli a3, a3, 16 0x4008f4cd <rtc_cmd_reg0_branch+9>: or a4, a4, a8 0x4008f4d0 <rtc_cmd_reg0_branch+12>: or a3, a4, a3 0x4008f4d3 <rtc_cmd_reg0_branch+15>: slli a2, a2, 17 0x4008f4d6 <rtc_cmd_reg0_branch+18>: or a2, a3, a2 0x4008f4d9 <rtc_cmd_reg0_branch+21>: retw.n (gdb) x /1x 0x4008f4c0 0x4008f4c0: 0x82000000
5.12 rtc_cmd_stage_branch
0x4008f4dc <rtc_cmd_stage_branch>: entry a1, 32 0x4008f4df <rtc_cmd_stage_branch+3>: l32r a9, 0x400807d0 0x4008f4e2 <rtc_cmd_stage_branch+6>: extui a4, a4, 0, 4 0x4008f4e5 <rtc_cmd_stage_branch+9>: extui a3, a3, 0, 2 0x4008f4e8 <rtc_cmd_stage_branch+12>: or a4, a4, a9 0x4008f4eb <rtc_cmd_stage_branch+15>: extui a2, a2, 0, 8 0x4008f4ee <rtc_cmd_stage_branch+18>: slli a3, a3, 15 0x4008f4f1 <rtc_cmd_stage_branch+21>: or a3, a4, a3 0x4008f4f4 <rtc_cmd_stage_branch+24>: slli a2, a2, 17 0x4008f4f7 <rtc_cmd_stage_branch+27>: or a2, a3, a2 0x4008f4fa <rtc_cmd_stage_branch+30>: retw.n (gdb) x /1x 0x400807d0 0x400807d0: 0x84000000
5.13 rtc_cmd_cpu_wakeup
0x4008f500 <rtc_cmd_cpu_wakeup>: entry a1, 32 0x4008f503 <rtc_cmd_cpu_wakeup+3>: l32r a8, 0x4008f4fc 0x4008f506 <rtc_cmd_cpu_wakeup+6>: or a2, a2, a8 0x4008f509 <rtc_cmd_cpu_wakeup+9>: retw.n (gdb) x /1x 0x4008f4fc 0x4008f4fc: 0x90000000
5.14 rtc_cmd_sleep_cyc_sel
0x4008f510 <rtc_cmd_sleep_cyc_sel>: entry a1, 32 0x4008f513 <rtc_cmd_sleep_cyc_sel+3>: l32r a8, 0x4008f50c 0x4008f516 <rtc_cmd_sleep_cyc_sel+6>: or a2, a2, a8 0x4008f519 <rtc_cmd_sleep_cyc_sel+9>: retw.n (gdb) x /1x 0x4008f50c 0x4008f50c: 0x92000000
5.15 rtc_cmd_meas_end
0x4008f520 <rtc_cmd_meas_end>: entry a1, 32 0x4008f523 <rtc_cmd_meas_end+3>: l32r a2, 0x4008f51c 0x4008f526 <rtc_cmd_meas_end+6>: retw.n (gdb) x /1x 0x4008f51c 0x4008f51c: 0xb0000000
