ESP32 RTC
来自Jack's Lab
1 Memory
1.1 FAST Memory
RTC FAST Memory 为 8 KB SRAM，其只能被 PRO_CPU 通过数据总线 0x3FF8_0000 ~ 0x3FF8_1FFF 读写，或被 PRO_CPU 通过指令总线 0x400C_0000~0x400C_1FFF 读写。与其他存储器不同，APP_CPU 不能访问 RTC FAST Memory
PRO_CPU 的这两段地址同序访问 RTC FAST Memory。即地址 0x3FF8_0000 与 0x400C_0000 访问到相同的 word，0x3FF8_0004与0x400C_0004访问到相同的word，0x3FF8_0008与0x400C_0008访问到相同的word， 以此类推。APP_CPU 的这两段地址不能访问到 RTC FAST Memory，也不能访问到其他任何目标
1.2 SLOW Memory
RTC SLOW Memory 为 8 KB SRAM，其可以被两个 CPU 通过数据总线与指令总线共用地址段 0x5000_0000 ~ 0x5000_1FFF 读写。
2 Register
2.1 RTC IO
components/esp32/include/soc/rtc_io_reg.h
#define DR_REG_RTCIO_BASE 0x3ff48400 #define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) #define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) #define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) #define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc) #define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) #define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) #define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) #define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c) #define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) #define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) #define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) #define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c) #define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) #define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) #define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) #define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c) #define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) #define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) #define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) #define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c) #define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) #define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) #define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) #define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c) #define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) #define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) #define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) #define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c) #define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x70) #define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74) #define RTC_IO_HALL_SENS_REG (DR_REG_RTCIO_BASE + 0x78) #define RTC_IO_SENSOR_PADS_REG (DR_REG_RTCIO_BASE + 0x7c) #define RTC_IO_ADC_PAD_REG (DR_REG_RTCIO_BASE + 0x80) #define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x84) #define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x88) #define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c) #define RTC_IO_TOUCH_CFG_REG (DR_REG_RTCIO_BASE + 0x90) #define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x94) #define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x98) #define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c) #define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0) #define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4) #define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8) #define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac) #define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0) #define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4) #define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xb8) #define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc) #define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0) #define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xc4) #define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0xc8)
2.2 RTC Ctrl
components/esp32/include/soc/rtc_cntl_reg.h
/************************************************************************************** * Note: * * Some Rtc memory and registers are used, in ROM or in internal library. * * Please do not use reserved or used rtc memory or registers. * * * ************************************************************************************* * RTC Memory & Store Register usage ************************************************************************************* * rtc memory addr type size usage * 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry * 0x3ff61000+SIZE_CP Slow 4096-SIZE_CP * 0x3ff62800 Slow 4096 Reserved * * 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code * ************************************************************************************* * Rtc store registers usage * RTC_CNTL_STORE0_REG * RTC_CNTL_STORE1_REG * RTC_CNTL_STORE2_REG * RTC_CNTL_STORE3_REG * RTC_CNTL_STORE4_REG Reserved * RTC_CNTL_STORE5_REG External Xtal Frequency * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC ************************************************************************************* */ #define DR_REG_RTCCNTL_BASE 0x3ff48000 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) #define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10) #define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14) #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) #define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) #define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) #define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30) #define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x34) #define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) #define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x3c) #define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x40) #define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x44) #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48) #define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x4c) #define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50) #define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x54) #define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x58) #define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) #define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) #define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) #define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) #define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) #define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) #define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) #define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) #define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) #define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) #define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x94) #define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x98) #define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x9c) #define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa0) #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xa4) #define RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0xa8) #define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xac) #define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0) #define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4) #define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xb8) #define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xbc) #define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xc0) #define RTC_CNTL_DIAG1_REG (DR_REG_RTCCNTL_BASE + 0xc4) #define RTC_CNTL_HOLD_FORCE_REG (DR_REG_RTCCNTL_BASE + 0xc8) #define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) #define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) #define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xd4) #define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4) #define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4) #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c)
3 Power Consumption
We are care of Deep-Sleep mode:
- The ULP co-porcessor is powered on: 150uA current consumption
- ULP sensor-monitored pattern: 25uA @ 1% duty
- RTC timer + RTC memory: 10uA
And Hibernate Mode:
- The internal 8MHz oscillator and ULP coprocessor are disabled
- The RTC recovery memory are power-down
- Only one RTC timer on the slow clock and some RTC GPIOs are active.
- The RTC timer or the RTC GPIOs can wake up the chip from the Hibernation mode
- Power Consumption: 2.5uA
4 Clock
The RTC clock has five possible sources:
- External low speed (32 KHz) crystal clock
- External crystal clock divided by 4 (40MHz/4 ?)
- Internal RC oscillator (typically about 150 KHz and adjustable)
- Internal 8 MHz oscillator
- Internal 31.25KHz clock (derived from the internal 8MHz oscillator divided by 256)
The related register:
#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ /*description: slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ #define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 #define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) #define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 #define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ /*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ #define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) #define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) #define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 #define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 /* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ /*description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ #define RTC_CNTL_SOC_CLK_SEL 0x00000003 #define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S)) #define RTC_CNTL_SOC_CLK_SEL_V 0x3 #define RTC_CNTL_SOC_CLK_SEL_S 27 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ /*description: CK8M force power up*/ #define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) #define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) #define RTC_CNTL_CK8M_FORCE_PU_V 0x1 #define RTC_CNTL_CK8M_FORCE_PU_S 26 /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ /*description: CK8M force power down*/ #define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) #define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) #define RTC_CNTL_CK8M_FORCE_PD_V 0x1 #define RTC_CNTL_CK8M_FORCE_PD_S 25 /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */ /*description: CK8M_DFREQ*/ #define RTC_CNTL_CK8M_DFREQ 0x000000FF #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) #define RTC_CNTL_CK8M_DFREQ_V 0xFF #define RTC_CNTL_CK8M_DFREQ_S 17 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ /*description: CK8M force no gating during sleep*/ #define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) #define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) #define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 #define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ /*description: XTAL force no gating during sleep*/ #define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) #define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) #define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 #define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */ /*description: divider = reg_ck8m_div_sel + 1*/ #define RTC_CNTL_CK8M_DIV_SEL 0x00000007 #define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) #define RTC_CNTL_CK8M_DIV_SEL_V 0x7 #define RTC_CNTL_CK8M_DIV_SEL_S 12 /* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */ /*description: */ #define RTC_CNTL_CK8M_DFREQ_FORCE (BIT(11)) #define RTC_CNTL_CK8M_DFREQ_FORCE_M (BIT(11)) #define RTC_CNTL_CK8M_DFREQ_FORCE_V 0x1 #define RTC_CNTL_CK8M_DFREQ_FORCE_S 11 /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ /*description: enable CK8M for digital core (no relationship with RTC core)*/ #define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) #define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) #define RTC_CNTL_DIG_CLK8M_EN_V 0x1 #define RTC_CNTL_DIG_CLK8M_EN_S 10 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ #define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) #define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) #define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 #define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ #define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) #define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) #define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 #define RTC_CNTL_DIG_XTAL32K_EN_S 8 /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ /*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ #define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) #define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) #define RTC_CNTL_ENB_CK8M_DIV_V 0x1 #define RTC_CNTL_ENB_CK8M_DIV_S 7 /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ /*description: disable CK8M and CK8M_D256_OUT*/ #define RTC_CNTL_ENB_CK8M (BIT(6)) #define RTC_CNTL_ENB_CK8M_M (BIT(6)) #define RTC_CNTL_ENB_CK8M_V 0x1 #define RTC_CNTL_ENB_CK8M_S 6 /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ /*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ #define RTC_CNTL_CK8M_DIV 0x00000003 #define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) #define RTC_CNTL_CK8M_DIV_V 0x3 #define RTC_CNTL_CK8M_DIV_S 4 #define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c)
5 API
#define DEEP_SLEEP_PD_NORMAL BIT(0) /* Base deep sleep mode */ #define DEEP_SLEEP_PD_RTC_PERIPH BIT(1) /* Power down RTC peripherals */ #define DEEP_SLEEP_PD_RTC_SLOW_MEM BIT(2) /* Power down RTC SLOW memory */ #define DEEP_SLEEP_PD_RTC_FAST_MEM BIT(3) /* Power down RTC FAST memory */ /* * @brief Prepare for entering sleep mode * @param deep_slp DEEP_SLEEP_PD_ flags combined with OR (DEEP_SLEEP_PD_NORMAL must be included) * @param cpu_lp_mode for deep sleep, should be 0 */ void rtc_slp_prep_lite(uint32_t deep_slp, uint32_t cpu_lp_mode); #define RTC_EXT_EVENT0_TRIG BIT(0) #define RTC_EXT_EVENT1_TRIG BIT(1) #define RTC_GPIO_TRIG BIT(2) /* Only available in light sleep */ #define RTC_TIMER_EXPIRE BIT(3) #define RTC_SDIO_TRIG BIT(4) #define RTC_MAC_TRIG BIT(5) #define RTC_UART0_TRIG BIT(6) #define RTC_UART1_TRIG BIT(7) #define RTC_TOUCH_TRIG BIT(8) #define RTC_SAR_TRIG BIT(9) #define RTC_BT_TRIG BIT(10) /* * @brief Enter sleep mode for given number of cycles * @param cycles_h higher 32 bit part of number of slow clock cycles * @param cycles_l lower 32 bit part of number of slow clock cycles * @param wakeup_opt wake up reason to enable (RTC_xxx_TRIG flags combined with OR) * @param reject_opt reserved, should be 0 * @return TBD */ uint32_t rtc_sleep(uint32_t cycles_h, uint32_t cycles_l, uint32_t wakeup_opt, uint32_t reject_opt);
5.1 rtc_sleep
0x4009011c <rtc_sleep>: entry a1, 32 0x4009011f <rtc_sleep+3>: l32r a9, 0x4008ff08 /* a9 = *(0x4008ff08) = 0x3ff4800c */ 0x40090122 <rtc_sleep+6>: l32r a11, 0x4008073c /* a11 = *(0x4008073c) = 0x80000000 */ 0x40090125 <rtc_sleep+9>: memw 0x40090128 <rtc_sleep+12>: l32i.n a8, a9, 0 /* a8 = *(0x3ff4800c) = 0x40000000 */ 0x4009012a <rtc_sleep+14>: l32r a10, 0x40080630 /* a10 = *(0x40080630) = 0x40000000 */ 0x4009012d <rtc_sleep+17>: or a8, a8, a11 0x40090130 <rtc_sleep+20>: memw 0x40090133 <rtc_sleep+23>: s32i.n a8, a9, 0 /* *(0x3ff4800c) = 0xC0000000 */ 0x40090135 <rtc_sleep+25>: memw 0x40090138 <rtc_sleep+28>: l32i.n a8, a9, 0 /* a8 = 0xC0000000 */ 0x4009013a <rtc_sleep+30>: bnone a8, a10, 0x40090135 /* if (a8 & a19 == 0) branch */ 0x4009013d <rtc_sleep+33>: l32r a10, 0x4008ff0c /* a10 = *(0x4008ff0c) = 0x3ff48048, RTC_CNTL_INT_CLR_REG */ 0x40090140 <rtc_sleep+36>: movi.n a8, 16 /* a8 = 16 = 0x10 */ 0x40090142 <rtc_sleep+38>: memw 0x40090145 <rtc_sleep+41>: l32i.n a9, a10, 0 /* a9 = *(0x3ff48048) = 0x0 */ 0x40090147 <rtc_sleep+43>: or a8, a9, a8 /* Clear RTC time valid interrupt state */ 0x4009014a <rtc_sleep+46>: memw 0x4009014d <rtc_sleep+49>: s32i.n a8, a10, 0 /* update to *(0x3ff48048), RTC_CNTL_INT_CLR_REG */ 0x4009014f <rtc_sleep+51>: l32r a8, 0x4008ff10 /* a8 = *(0x4008ff10) = 0x3ff48010 RTC_CNTL_TIME0_REG */ 0x40090152 <rtc_sleep+54>: l32r a9, 0x4008ff14 /* a9 = *(0x4008ff14) = 0x3ff48014 RTC_CNTL_TIME1_REG */ 0x40090155 <rtc_sleep+57>: memw 0x40090158 <rtc_sleep+60>: l32i.n a8, a8, 0 /* a8 = *(0x3ff48010) = 0x000124ee, time0 value */ 0x4009015a <rtc_sleep+62>: memw 0x4009015d <rtc_sleep+65>: l32i.n a12, a9, 0 /* a12 = *(0x3ff48014) = 0x0, time1 value */ 0x4009015f <rtc_sleep+67>: add.n a8, a3, a8 /* a8 += 2nd_param, 2nd_param is cycles_l */ 0x40090161 <rtc_sleep+69>: movi.n a9, 1 /* a9 = 1 */ 0x40090163 <rtc_sleep+71>: bltu a8, a3, 0x40090169 /* if (a8 < a3); branch */ 0x40090166 <rtc_sleep+74>: movi a9, 0 /* a9 = 0 */ 0x40090169 <rtc_sleep+77>: l32r a3, 0x4008ff64 /* a3 = *(0x4008ff64) = 0x3ff48004, RTC_CNTL_SLP_TIME0_REG */ 0x4009016c <rtc_sleep+80>: add.n a2, a2, a12 /* a2 = 1st_param_cycles_h + a12 */ 0x4009016e <rtc_sleep+82>: memw 0x40090171 <rtc_sleep+85>: s32i.n a8, a3, 0 /* update a8 into RTC_CNTL_SLP_TIME0_REG */ 0x40090173 <rtc_sleep+87>: l32r a8, 0x4008ff68 /* a8 = *(0x4008ff68) = 0x3ff48008, RTC_CNTL_SLP_TIME1_REG */ 0x40090176 <rtc_sleep+90>: l32r a3, 0x4008ff84 /* a3 = *(0x4008ff84) = 0x3ff48038, RTC_CNTL_WAKEUP_STATE_REG */ 0x40090179 <rtc_sleep+93>: add.n a9, a9, a2 /* a9 += a2, time1_val + cycles_h */ 0x4009017b <rtc_sleep+95>: memw 0x4009017e <rtc_sleep+98>: s32i.n a9, a8, 0 /* update a9 into RTC_CNTL_SLP_TIME1_REG */ 0x40090180 <rtc_sleep+100>: memw 0x40090183 <rtc_sleep+103>: l32i.n a8, a3, 0 /* a8 = *(0x3ff48038) = 0x00006000, read RTC_CNTL_WAKEUP_STATE_REG */ 0x40090185 <rtc_sleep+105>: l32r a2, 0x4008d188 /* a2 = *(0x4008d188) = 0xffc007ff */ 0x40090188 <rtc_sleep+108>: extui a4, a4, 0, 11 /* a4 is the 3rd param, extract the low 11 bits */ 0x4009018b <rtc_sleep+111>: and a2, a8, a2 /* a2 = RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff (only bitpos:[21:11]) */ 0x4009018e <rtc_sleep+114>: slli a4, a4, 11 /* a4 <<= 11 */ 0x40090191 <rtc_sleep+117>: or a4, a4, a2 /* a4 = wakeup_opt | (RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff) */ 0x40090194 <rtc_sleep+120>: l32r a2, 0x4008ff88 /* a2 = *(0x4008ff88) = 0x3ff48064, RTC_CNTL_SLP_REJECT_CONF_REG */ 0x40090197 <rtc_sleep+123>: memw 0x4009019a <rtc_sleep+126>: s32i.n a4, a3, 0 /* update the a4 into RTC_CNTL_WAKEUP_STATE_REG */ 0x4009019c <rtc_sleep+128>: l32r a3, 0x4008d1f0 /* a3 = *(0x4008d1f0) = 0x3ff48018, RTC_CNTL_STATE0_REG */ 0x4009019f <rtc_sleep+131>: memw 0x400901a2 <rtc_sleep+134>: s32i.n a5, a2, 0 /* update the a5 (4th param) into RTC_CNTL_SLP_REJECT_CONF_REG directly */ 0x400901a4 <rtc_sleep+136>: memw 0x400901a7 <rtc_sleep+139>: l32i.n a2, a3, 0 /* a2 = *(0x3ff48018) = 0x20300000, read RTC_CNTL_STATE0_REG */ 0x400901a9 <rtc_sleep+141>: l32r a9, 0x4008ffb8 /* a9 = *(0x4008ffb8) = 0x3ff48040, RTC_CNTL_INT_RAW_REG */ 0x400901ac <rtc_sleep+144>: or a11, a2, a11 0x400901af <rtc_sleep+147>: memw 0x400901b2 <rtc_sleep+150>: s32i.n a11, a3, 0 0x400901b4 <rtc_sleep+152>: memw 0x400901b7 <rtc_sleep+155>: l32i.n a8, a9, 0 0x400901b9 <rtc_sleep+157>: extui a8, a8, 0, 2 0x400901bc <rtc_sleep+160>: beqz a8, 0x400901b4 <rtc_sleep+152> 0x400901bf <rtc_sleep+163>: memw 0x400901c2 <rtc_sleep+166>: l32i.n a2, a9, 0 0x400901c4 <rtc_sleep+168>: memw 0x400901c7 <rtc_sleep+171>: l32i.n a4, a10, 0 0x400901c9 <rtc_sleep+173>: movi.n a3, 3 0x400901cb <rtc_sleep+175>: or a3, a4, a3 0x400901ce <rtc_sleep+178>: memw 0x400901d1 <rtc_sleep+181>: s32i.n a3, a10, 0 0x400901d3 <rtc_sleep+183>: extui a2, a2, 1, 1 0x400901d6 <rtc_sleep+186>: retw.n
5.2 undocument
rtc_pad_ext_wakeup rtc_pad_gpio_wakeup rtc_cmd_ext_wakeup
5.3 rtc_set_wakeup_opt
0x4008ff8c <rtc_set_wakeup_opt>: entry a1, 32 0x4008ff8f <rtc_set_wakeup_opt+3>: l32r a8, 0x4008ff84 <-- load the address of RTC_CNTL_WAKEUP_STATE_REG 0x4008ff92 <rtc_set_wakeup_opt+6>: l32r a11, 0x4008d188 <-- a11 = 0xffc007ff 0x4008ff95 <rtc_set_wakeup_opt+9>: memw 0x4008ff98 <rtc_set_wakeup_opt+12>: l32i.n a9, a8, 0 <-- Read the RTC_CNTL_WAKEUP_STATE_REG 0x4008ff9a <rtc_set_wakeup_opt+14>: extui a2, a2, 0, 11 <-- Extract the low 11 bits of 1st parameter 0x4008ff9d <rtc_set_wakeup_opt+17>: slli a10, a2, 11 <-- Shift left 11 0x4008ffa0 <rtc_set_wakeup_opt+20>: and a9, a9, a11 <-- RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff (only bitpos:[21:11]) 0x4008ffa3 <rtc_set_wakeup_opt+23>: or a9, a10, a9 <-- (RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff) | wakeup_opt 0x4008ffa6 <rtc_set_wakeup_opt+26>: memw 0x4008ffa9 <rtc_set_wakeup_opt+29>: s32i.n a9, a8, 0 <-- Write to RTC_CNTL_WAKEUP_STATE_REG 0x4008ffab <rtc_set_wakeup_opt+31>: l32r a8, 0x4008ff88 <--- load the address of RTC_CNTL_SLP_REJECT_CONF_REG 0x4008ffae <rtc_set_wakeup_opt+34>: memw 0x4008ffb1 <rtc_set_wakeup_opt+37>: s32i.n a3, a8, 0 <-- store the 2nd parameter into RTC_CNTL_SLP_REJECT_CONF_REG directly 0x4008ffb3 <rtc_set_wakeup_opt+39>: retw.n (gdb) x /1x 0x4008ff84 0x4008ff84: 0x3ff48038 (gdb) x /1x 0x4008d188 0x4008d188: 0xffc007ff (gdb) x /1x 0x4008ff88 0x4008ff88: 0x3ff48064 #define DR_REG_RTCCNTL_BASE 0x3ff48000 #define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) #define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) /* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */ /*description: enable filter for gpio wakeup event*/ #define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22)) #define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(22)) #define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 #define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22 /* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */ /*description: wakeup enable bitmap*/ #define RTC_CNTL_WAKEUP_ENA 0x000007FF #define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) #define RTC_CNTL_WAKEUP_ENA_V 0x7FF #define RTC_CNTL_WAKEUP_ENA_S 11 /* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */ /*description: wakeup cause*/ #define RTC_CNTL_WAKEUP_CAUSE 0x000007FF #define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) #define RTC_CNTL_WAKEUP_CAUSE_V 0x7FF #define RTC_CNTL_WAKEUP_CAUSE_S 0
>>> So the rtc_set_wakeup_opt should be:
void rtc_set_wakeup_opt(uint32_t wakeup_opt, uint32_t sleep_reject_conf);
5.4 Timer Expire Wakeup
void esp_deep_sleep(uint64_t time_in_us)
{
rtc_set_cpu_freq(CPU_XTAL);
if (esp_get_deep_sleep_wake_stub() == NULL) {
esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
}
uint32_t period = rtc_slowck_cali(CALI_RTC_MUX, 128);
uint32_t cycle_l, cycle_h;
rtc_usec2rtc(time_in_us >> 32, time_in_us, period, &cycle_h, &cycle_l);
rtc_slp_prep_lite(1, 0);
rtc_sleep(cycle_h, cycle_l, TIMER_EXPIRE_EN, 0);
while (1) {
;
}
}
5.5 External Wakeup
#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) /* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ /*description: enable control XTAL by external pads*/ #define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) #define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) #define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 #define RTC_CNTL_XTL_EXT_CTR_EN_S 31 /* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ /*description: 0: power down XTAL at high level 1: power down XTAL at low level*/ #define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) #define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) #define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 #define RTC_CNTL_XTL_EXT_CTR_LV_S 30 #define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) /* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ /*description: 0: external wakeup at low level 1: external wakeup at high level*/ #define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) #define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) #define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 #define RTC_CNTL_EXT_WAKEUP1_LV_S 31 /* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ /*description: 0: external wakeup at low level 1: external wakeup at high level*/ #define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) #define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) #define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 #define RTC_CNTL_EXT_WAKEUP0_LV_S 30 #define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) /* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ /*description: clear ext wakeup1 status*/ #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18)) #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(18)) #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18 /* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */ /*description: Bitmap to select RTC pads for ext wakeup1*/ #define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF #define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) #define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFF #define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 #define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) /* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */ /*description: ext wakeup1 status*/ #define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF #define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) #define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFF #define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 #define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc) /* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ /*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/ #define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F #define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S)) #define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F #define RTC_IO_EXT_WAKEUP0_SEL_S 27 #define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0) /* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ /*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/ #define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F #define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S)) #define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F #define RTC_IO_XTL_EXT_CTR_SEL_S 27
5.6 Touch Wakeup
5.7 SAR Wakeup
5.8 BT Wakeup
6 ULP CP Inst
6.1 ulp_cp_wr_reg
(gdb) x /16i ulp_cp_wr_reg 0x4008f690 <ulp_cp_wr_reg>: entry a1, 32 0x4008f693 <ulp_cp_wr_reg+3>: l32r a8, 0x40085078 0x4008f696 <ulp_cp_wr_reg+6>: slli a5, a5, 10 0x4008f699 <ulp_cp_wr_reg+9>: or a2, a2, a8 0x4008f69c <ulp_cp_wr_reg+12>: or a5, a2, a5 0x4008f69f <ulp_cp_wr_reg+15>: slli a4, a4, 18 0x4008f6a2 <ulp_cp_wr_reg+18>: or a5, a5, a4 0x4008f6a5 <ulp_cp_wr_reg+21>: slli a2, a3, 23 0x4008f6a8 <ulp_cp_wr_reg+24>: or a2, a5, a2 0x4008f6ab <ulp_cp_wr_reg+27>: retw.n 0x4008f6ad: ill (gdb) x /4x 0x40085078 0x40085078: 0x10000000 0xb100a136 0x5c0cfff1 0x8118c1a2
6.2 ulp_cp_rd_reg
0x4008f6b0 <ulp_cp_rd_reg>: entry a1, 32 0x4008f6b3 <ulp_cp_rd_reg+3>: l32r a8, 0x4008043c 0x4008f6b6 <ulp_cp_rd_reg+6>: slli a4, a4, 18 0x4008f6b9 <ulp_cp_rd_reg+9>: or a2, a2, a8 0x4008f6bc <ulp_cp_rd_reg+12>: or a4, a2, a4 0x4008f6bf <ulp_cp_rd_reg+15>: slli a2, a3, 23 0x4008f6c2 <ulp_cp_rd_reg+18>: or a2, a4, a2 0x4008f6c5 <ulp_cp_rd_reg+21>: retw.n (gdb) x /4x 0x4008043c 0x4008043c: 0x20000000 0x40080000 0x3ffb29d0 0x3ffb0000
6.3 ulp_cp_wr_i2c
0x4008f6c8 <ulp_cp_wr_i2c>: entry a1, 32 0x4008f6cb <ulp_cp_wr_i2c+3>: l32r a8, 0x4008f3c4 0x4008f6ce <ulp_cp_wr_i2c+6>: slli a7, a7, 8 0x4008f6d1 <ulp_cp_wr_i2c+9>: or a4, a4, a8 0x4008f6d4 <ulp_cp_wr_i2c+12>: or a7, a4, a7 0x4008f6d7 <ulp_cp_wr_i2c+15>: slli a6, a6, 16 0x4008f6da <ulp_cp_wr_i2c+18>: or a7, a7, a6 0x4008f6dd <ulp_cp_wr_i2c+21>: slli a5, a5, 19 0x4008f6e0 <ulp_cp_wr_i2c+24>: or a7, a7, a5 0x4008f6e3 <ulp_cp_wr_i2c+27>: slli a3, a3, 22 0x4008f6e6 <ulp_cp_wr_i2c+30>: or a7, a7, a3 0x4008f6e9 <ulp_cp_wr_i2c+33>: slli a2, a2, 27 0x4008f6ec <ulp_cp_wr_i2c+36>: or a2, a7, a2 0x4008f6ef <ulp_cp_wr_i2c+39>: retw.n 0x4008f6f1: ill (gdb) x /4x 0x4008f3c4 0x4008f3c4: 0x30000000 0x81004136 0x7780fffe 0x20448011
6.4 ulp_cp_wait_delay
0x4008f6f4 <ulp_cp_wait_delay>: entry a1, 32 0x4008f6f7 <ulp_cp_wait_delay+3>: l32r a8, 0x400805a0 0x4008f6fa <ulp_cp_wait_delay+6>: or a2, a2, a8 0x4008f6fd <ulp_cp_wait_delay+9>: retw.n (gdb) x /4x 0x400805a0 0x400805a0: 0x40000000 0x3ff42008 0x00400000 0x3ffae270
6.5 ulp_cp_meas_tsens
(gdb) x /32i ulp_cp_meas_tsens 0x4008f700 <ulp_cp_meas_tsens>: entry a1, 32 0x4008f703 <ulp_cp_meas_tsens+3>: l32r a8, 0x4008f404 0x4008f706 <ulp_cp_meas_tsens+6>: slli a2, a2, 2 0x4008f709 <ulp_cp_meas_tsens+9>: or a3, a3, a8 0x4008f70c <ulp_cp_meas_tsens+12>: or a2, a3, a2 0x4008f70f <ulp_cp_meas_tsens+15>: retw.n 0x4008f711: ill (gdb) x /4x 0x4008f404 0x4008f404: 0xa0000000 0x81004136 0x2200fffe 0x20338011
6.6 ulp_cp_meas_tsens_new
0x4008f714 <ulp_cp_meas_tsens_new>: entry a1, 32 0x4008f717 <ulp_cp_meas_tsens_new+3>: l32r a8, 0x4008f404 0x4008f71a <ulp_cp_meas_tsens_new+6>: slli a3, a3, 2 0x4008f71d <ulp_cp_meas_tsens_new+9>: or a4, a4, a8 0x4008f720 <ulp_cp_meas_tsens_new+12>: or a3, a4, a3 0x4008f723 <ulp_cp_meas_tsens_new+15>: slli a2, a2, 16 0x4008f726 <ulp_cp_meas_tsens_new+18>: or a2, a3, a2 0x4008f729 <ulp_cp_meas_tsens_new+21>: retw.n (gdb) x /4x 0x4008f404 0x4008f404: 0xa0000000 0x81004136 0x2200fffe 0x20338011
6.7 ulp_cp_meas_sar
0x4008f72c <ulp_cp_meas_sar>: entry a1, 32 0x4008f72f <ulp_cp_meas_sar+3>: l32r a8, 0x4008f41c 0x4008f732 <ulp_cp_meas_sar+6>: slli a4, a4, 2 0x4008f735 <ulp_cp_meas_sar+9>: or a5, a5, a8 0x4008f738 <ulp_cp_meas_sar+12>: or a4, a5, a4 0x4008f73b <ulp_cp_meas_sar+15>: slli a3, a3, 6 0x4008f73e <ulp_cp_meas_sar+18>: or a4, a4, a3 0x4008f741 <ulp_cp_meas_sar+21>: slli a2, a2, 8 0x4008f744 <ulp_cp_meas_sar+24>: or a2, a4, a2 0x4008f747 <ulp_cp_meas_sar+27>: retw.n 0x4008f749: ill (gdb) x /4x 0x4008f41c 0x4008f41c: 0x50000000 0x81004136 0x4040fffe 0x14505034
6.8 ulp_cp_sar_wr_mem
0x4008f74c <ulp_cp_sar_wr_mem>: entry a1, 32 0x4008f74f <ulp_cp_sar_wr_mem+3>: l32r a8, 0x400804d8 0x4008f752 <ulp_cp_sar_wr_mem+6>: slli a3, a3, 2 0x4008f755 <ulp_cp_sar_wr_mem+9>: or a4, a4, a8 0x4008f758 <ulp_cp_sar_wr_mem+12>: or a3, a4, a3 0x4008f75b <ulp_cp_sar_wr_mem+15>: slli a2, a2, 7 0x4008f75e <ulp_cp_sar_wr_mem+18>: or a2, a3, a2 0x4008f761 <ulp_cp_sar_wr_mem+21>: retw.n 0x4008f763: ill (gdb) x /4x 0x400804d8 0x400804d8: 0x60000000 0x00040023 0xc0000000 0x3ffb2b48
6.9 ulp_cp_sar_wr_mem_set_offset
0x4008f768 <ulp_cp_sar_wr_mem_set_offset>: entry a1, 32 0x4008f76b <ulp_cp_sar_wr_mem_set_offset+3>: l32r a8, 0x4008f764 0x4008f76e <ulp_cp_sar_wr_mem_set_offset+6>: slli a2, a2, 10 0x4008f771 <ulp_cp_sar_wr_mem_set_offset+9>: or a2, a2, a8 0x4008f774 <ulp_cp_sar_wr_mem_set_offset+12>: retw.n (gdb) x /1x 0x4008f764 0x4008f764: 0x64000000
6.10 ulp_cp_sar_wr_mem_man2
0x4008f790 <ulp_cp_sar_wr_mem_man2>: entry a1, 32 0x4008f793 <ulp_cp_sar_wr_mem_man2+3>: l32r a8, 0x4008f778 0x4008f796 <ulp_cp_sar_wr_mem_man2+6>: slli a3, a3, 2 0x4008f799 <ulp_cp_sar_wr_mem_man2+9>: or a4, a4, a8 0x4008f79c <ulp_cp_sar_wr_mem_man2+12>: or a3, a4, a3 0x4008f79f <ulp_cp_sar_wr_mem_man2+15>: slli a2, a2, 10 0x4008f7a2 <ulp_cp_sar_wr_mem_man2+18>: or a2, a3, a2 0x4008f7a5 <ulp_cp_sar_wr_mem_man2+21>: retw.n (gdb) x /1x 0x4008f778 0x4008f778: 0x68000000
6.11 ulp_cp_rd_mem
0x4008f7ac <ulp_cp_rd_mem>: entry a1, 32 0x4008f7af <ulp_cp_rd_mem+3>: l32r a8, 0x4008f7a8 0x4008f7b2 <ulp_cp_rd_mem+6>: slli a2, a2, 10 0x4008f7b5 <ulp_cp_rd_mem+9>: or a3, a3, a8 0x4008f7b8 <ulp_cp_rd_mem+12>: or a2, a3, a2 0x4008f7bb <ulp_cp_rd_mem+15>: retw.n 0x4008f7bd: ill 0x4008f7c0 <ulp_cp_rd_mem2>: entry a1, 32 0x4008f7c3 <ulp_cp_rd_mem2+3>: l32r a8, 0x4008f7a8 0x4008f7c6 <ulp_cp_rd_mem2+6>: slli a3, a3, 2 0x4008f7c9 <ulp_cp_rd_mem2+9>: or a4, a4, a8 0x4008f7cc <ulp_cp_rd_mem2+12>: or a3, a4, a3 0x4008f7cf <ulp_cp_rd_mem2+15>: slli a2, a2, 10 0x4008f7d2 <ulp_cp_rd_mem2+18>: or a2, a3, a2 0x4008f7d5 <ulp_cp_rd_mem2+21>: retw.n (gdb) x /1x 0x4008f7a8 0x4008f7a8: 0xd0000000
6.12 ulp_cp_alu_reg
(gdb) x /12i ulp_cp_alu_reg 0x4008f7d8 <ulp_cp_alu_reg>: entry a1, 32 0x4008f7db <ulp_cp_alu_reg+3>: l32r a8, 0x4008f46c 0x4008f7de <ulp_cp_alu_reg+6>: slli a4, a4, 2 0x4008f7e1 <ulp_cp_alu_reg+9>: or a5, a5, a8 0x4008f7e4 <ulp_cp_alu_reg+12>: or a4, a5, a4 0x4008f7e7 <ulp_cp_alu_reg+15>: slli a3, a3, 4 0x4008f7ea <ulp_cp_alu_reg+18>: or a4, a4, a3 0x4008f7ed <ulp_cp_alu_reg+21>: slli a2, a2, 21 0x4008f7f0 <ulp_cp_alu_reg+24>: or a2, a4, a2 0x4008f7f3 <ulp_cp_alu_reg+27>: retw.n 0x4008f7f5: ill (gdb) x /1x 0x4008f46c 0x4008f46c: 0x70000000
6.13 ulp_cp_alu_im
0x4008f7f8 <ulp_cp_alu_im>: entry a1, 32 0x4008f7fb <ulp_cp_alu_im+3>: l32r a8, 0x4008f490 0x4008f7fe <ulp_cp_alu_im+6>: slli a4, a4, 2 0x4008f801 <ulp_cp_alu_im+9>: or a5, a5, a8 0x4008f804 <ulp_cp_alu_im+12>: slli a2, a2, 4 0x4008f807 <ulp_cp_alu_im+15>: or a8, a5, a4 0x4008f80a <ulp_cp_alu_im+18>: or a8, a8, a2 0x4008f80d <ulp_cp_alu_im+21>: slli a2, a3, 21 0x4008f810 <ulp_cp_alu_im+24>: or a2, a8, a2 0x4008f813 <ulp_cp_alu_im+27>: retw.n 0x4008f815: ill 0x4008f818: ill (gdb) x /1x 0x4008f490 0x4008f490: 0x72000000
6.14 ulp_cp_alu_im
0x4008f7f8 <ulp_cp_alu_im>: entry a1, 32 0x4008f7fb <ulp_cp_alu_im+3>: l32r a8, 0x4008f490 0x4008f7fe <ulp_cp_alu_im+6>: slli a4, a4, 2 0x4008f801 <ulp_cp_alu_im+9>: or a5, a5, a8 0x4008f804 <ulp_cp_alu_im+12>: slli a2, a2, 4 0x4008f807 <ulp_cp_alu_im+15>: or a8, a5, a4 0x4008f80a <ulp_cp_alu_im+18>: or a8, a8, a2 0x4008f80d <ulp_cp_alu_im+21>: slli a2, a3, 21 0x4008f810 <ulp_cp_alu_im+24>: or a2, a8, a2 0x4008f813 <ulp_cp_alu_im+27>: retw.n 0x4008f815: ill 0x4008f818: ill
6.15 ulp_cp_stage_cnt_alu
0x4008f81c <ulp_cp_stage_cnt_alu>: entry a1, 32 0x4008f81f <ulp_cp_stage_cnt_alu+3>: l32r a8, 0x4008f818 0x4008f822 <ulp_cp_stage_cnt_alu+6>: slli a2, a2, 4 0x4008f825 <ulp_cp_stage_cnt_alu+9>: or a8, a2, a8 0x4008f828 <ulp_cp_stage_cnt_alu+12>: slli a2, a3, 21 0x4008f82b <ulp_cp_stage_cnt_alu+15>: or a2, a8, a2 0x4008f82e <ulp_cp_stage_cnt_alu+18>: retw.n (gdb) x /1x 0x4008f818 0x4008f818: 0x74000000
6.16 ulp_cp_force_branch
0x4008f830 <ulp_cp_force_branch>: entry a1, 32 0x4008f833 <ulp_cp_force_branch+3>: l32r a8, 0x40080690 0x4008f836 <ulp_cp_force_branch+6>: slli a2, a2, 17 0x4008f839 <ulp_cp_force_branch+9>: or a2, a2, a8 0x4008f83c <ulp_cp_force_branch+12>: retw.n (gdb) x /1x 0x40080690 0x40080690: 0x80000000
6.17 ulp_cp_jump
0x4008f840 <ulp_cp_jump>: entry a1, 32 0x4008f843 <ulp_cp_jump+3>: l32r a8, 0x40080690 0x4008f846 <ulp_cp_jump+6>: slli a4, a4, 2 0x4008f849 <ulp_cp_jump+9>: or a5, a5, a8 0x4008f84c <ulp_cp_jump+12>: or a4, a5, a4 0x4008f84f <ulp_cp_jump+15>: slli a2, a2, 22 0x4008f852 <ulp_cp_jump+18>: or a2, a4, a2 0x4008f855 <ulp_cp_jump+21>: retw.n
6.18 ulp_cp_reg0_branch
0x4008f858 <ulp_cp_reg0_branch>: entry a1, 32 0x4008f85b <ulp_cp_reg0_branch+3>: l32r a8, 0x4008f4c0 0x4008f85e <ulp_cp_reg0_branch+6>: slli a3, a3, 16 0x4008f861 <ulp_cp_reg0_branch+9>: or a4, a4, a8 0x4008f864 <ulp_cp_reg0_branch+12>: or a3, a4, a3 0x4008f867 <ulp_cp_reg0_branch+15>: slli a2, a2, 17 0x4008f86a <ulp_cp_reg0_branch+18>: or a2, a3, a2 0x4008f86d <ulp_cp_reg0_branch+21>: retw.n (gdb) x /1x 0x4008f4c0 0x4008f4c0: 0x82000000
6.19 ulp_cp_stage_cnt_br
0x4008f870 <ulp_cp_stage_cnt_br>: entry a1, 32 0x4008f873 <ulp_cp_stage_cnt_br+3>: l32r a8, 0x400807d0 0x4008f876 <ulp_cp_stage_cnt_br+6>: slli a3, a3, 15 0x4008f879 <ulp_cp_stage_cnt_br+9>: or a4, a4, a8 0x4008f87c <ulp_cp_stage_cnt_br+12>: or a3, a4, a3 0x4008f87f <ulp_cp_stage_cnt_br+15>: slli a2, a2, 17 0x4008f882 <ulp_cp_stage_cnt_br+18>: or a2, a3, a2 0x4008f885 <ulp_cp_stage_cnt_br+21>: retw.n (gdb) x /1x 0x400807d0 0x400807d0: 0x84000000
6.20 ulp_cp_cpu_wakeup
0x4008f888 <ulp_cp_cpu_wakeup>: entry a1, 32 0x4008f88b <ulp_cp_cpu_wakeup+3>: l32r a8, 0x4008f4fc 0x4008f88e <ulp_cp_cpu_wakeup+6>: or a2, a2, a8 0x4008f891 <ulp_cp_cpu_wakeup+9>: retw.n (gdb) x /1x 0x4008f4fc 0x4008f4fc: 0x90000000
6.21 ulp_cp_sleep_cyc_sel
0x4008f894 <ulp_cp_sleep_cyc_sel>: entry a1, 32 0x4008f897 <ulp_cp_sleep_cyc_sel+3>: l32r a8, 0x4008f50c 0x4008f89a <ulp_cp_sleep_cyc_sel+6>: or a2, a2, a8 0x4008f89d <ulp_cp_sleep_cyc_sel+9>: retw.n (gdb) x /1x 0x4008f50c 0x4008f50c: 0x92000000
6.22 ulp_cp_meas_end
0x4008f8a0 <ulp_cp_meas_end>: entry a1, 32 0x4008f8a3 <ulp_cp_meas_end+3>: l32r a2, 0x4008f51c 0x4008f8a6 <ulp_cp_meas_end+6>: retw.n (gdb) x /1x 0x4008f51c 0x4008f51c: 0xb0000000
7 RTC CMD Inst
7.1 rtc_cmd_wr_reg
0x4008f378 <rtc_cmd_wr_reg>: entry a1, 32 0x4008f37b <rtc_cmd_wr_reg+3>: l32r a9, 0x40085078 0x4008f37e <rtc_cmd_wr_reg+6>: extui a5, a5, 0, 8 0x4008f381 <rtc_cmd_wr_reg+9>: slli a8, a5, 10 0x4008f384 <rtc_cmd_wr_reg+12>: extui a4, a4, 0, 5 0x4008f387 <rtc_cmd_wr_reg+15>: or a8, a8, a9 0x4008f38a <rtc_cmd_wr_reg+18>: slli a9, a4, 18 0x4008f38d <rtc_cmd_wr_reg+21>: or a8, a8, a9 0x4008f390 <rtc_cmd_wr_reg+24>: extui a3, a3, 0, 5 0x4008f393 <rtc_cmd_wr_reg+27>: extui a2, a2, 0, 10 0x4008f396 <rtc_cmd_wr_reg+30>: or a2, a8, a2 0x4008f399 <rtc_cmd_wr_reg+33>: slli a4, a3, 23 0x4008f39c <rtc_cmd_wr_reg+36>: or a2, a2, a4 0x4008f39f <rtc_cmd_wr_reg+39>: retw.n 0x4008f3a1: ill (gdb) x /1x 0x40085078 0x40085078: 0x10000000
7.2 rtc_cmd_rd_reg
0x4008f3a4 <rtc_cmd_rd_reg>: entry a1, 32 0x4008f3a7 <rtc_cmd_rd_reg+3>: l32r a9, 0x4008043c 0x4008f3aa <rtc_cmd_rd_reg+6>: extui a4, a4, 0, 5 0x4008f3ad <rtc_cmd_rd_reg+9>: slli a8, a4, 18 0x4008f3b0 <rtc_cmd_rd_reg+12>: or a8, a8, a9 0x4008f3b3 <rtc_cmd_rd_reg+15>: extui a3, a3, 0, 5 0x4008f3b6 <rtc_cmd_rd_reg+18>: extui a2, a2, 0, 10 0x4008f3b9 <rtc_cmd_rd_reg+21>: or a2, a8, a2 0x4008f3bc <rtc_cmd_rd_reg+24>: slli a9, a3, 23 0x4008f3bf <rtc_cmd_rd_reg+27>: or a2, a2, a9 0x4008f3c2 <rtc_cmd_rd_reg+30>: retw.n 0x4008f3c4: ill (gdb) x /1x 0x4008043c 0x4008043c: 0x20000000
7.3 rtc_cmd_wr_i2c
0x4008f3c8 <rtc_cmd_wr_i2c>: entry a1, 32 0x4008f3cb <rtc_cmd_wr_i2c+3>: l32r a8, 0x4008f3c4 0x4008f3ce <rtc_cmd_wr_i2c+6>: slli a7, a7, 8 0x4008f3d1 <rtc_cmd_wr_i2c+9>: or a4, a4, a8 0x4008f3d4 <rtc_cmd_wr_i2c+12>: or a7, a4, a7 0x4008f3d7 <rtc_cmd_wr_i2c+15>: slli a6, a6, 16 0x4008f3da <rtc_cmd_wr_i2c+18>: or a7, a7, a6 0x4008f3dd <rtc_cmd_wr_i2c+21>: slli a5, a5, 19 0x4008f3e0 <rtc_cmd_wr_i2c+24>: or a7, a7, a5 0x4008f3e3 <rtc_cmd_wr_i2c+27>: slli a3, a3, 22 0x4008f3e6 <rtc_cmd_wr_i2c+30>: or a7, a7, a3 0x4008f3e9 <rtc_cmd_wr_i2c+33>: slli a2, a2, 27 0x4008f3ec <rtc_cmd_wr_i2c+36>: or a2, a7, a2 0x4008f3ef <rtc_cmd_wr_i2c+39>: retw.n 0x4008f3f1: ill (gdb) x /1x 0x4008f3c4 0x4008f3c4: 0x30000000
7.4 rtc_cmd_wait_delay
0x4008f3f4 <rtc_cmd_wait_delay>: entry a1, 32 0x4008f3f7 <rtc_cmd_wait_delay+3>: l32r a8, 0x400805a0 0x4008f3fa <rtc_cmd_wait_delay+6>: extui a2, a2, 0, 16 0x4008f3fd <rtc_cmd_wait_delay+9>: or a2, a2, a8 0x4008f400 <rtc_cmd_wait_delay+12>: retw.n 0x4008f402: ill (gdb) x /1x 0x400805a0 0x400805a0: 0x40000000
7.5 rtc_cmd_meas_tsens
0x4008f408 <rtc_cmd_meas_tsens>: entry a1, 32 0x4008f40b <rtc_cmd_meas_tsens+3>: l32r a8, 0x4008f404 0x4008f40e <rtc_cmd_meas_tsens+6>: slli a2, a2, 16 0x4008f411 <rtc_cmd_meas_tsens+9>: or a3, a3, a8 0x4008f414 <rtc_cmd_meas_tsens+12>: or a2, a3, a2 0x4008f417 <rtc_cmd_meas_tsens+15>: retw.n 0x4008f419: ill (gdb) x /1x 0x4008f404 0x4008f404: 0xa0000000
7.6 rtc_cmd_meas_saradc
0x4008f420 <rtc_cmd_meas_saradc>: entry a1, 32 0x4008f423 <rtc_cmd_meas_saradc+3>: l32r a8, 0x4008f41c 0x4008f426 <rtc_cmd_meas_saradc+6>: extui a4, a4, 0, 4 0x4008f429 <rtc_cmd_meas_saradc+9>: extui a5, a5, 0, 2 0x4008f42c <rtc_cmd_meas_saradc+12>: or a5, a5, a8 0x4008f42f <rtc_cmd_meas_saradc+15>: extui a3, a3, 0, 2 0x4008f432 <rtc_cmd_meas_saradc+18>: slli a8, a4, 2 0x4008f435 <rtc_cmd_meas_saradc+21>: or a5, a5, a8 0x4008f438 <rtc_cmd_meas_saradc+24>: slli a3, a3, 6 0x4008f43b <rtc_cmd_meas_saradc+27>: extui a2, a2, 0, 16 0x4008f43e <rtc_cmd_meas_saradc+30>: or a5, a5, a3 0x4008f441 <rtc_cmd_meas_saradc+33>: slli a2, a2, 8 0x4008f444 <rtc_cmd_meas_saradc+36>: or a2, a5, a2 0x4008f447 <rtc_cmd_meas_saradc+39>: retw.n 0x4008f449: ill (gdb) x /1x 0x4008f41c 0x4008f41c: 0x50000000
7.7 rtc_cmd_write_mem
0x4008f44c <rtc_cmd_write_mem>: entry a1, 32 0x4008f44f <rtc_cmd_write_mem+3>: l32r a9, 0x400804d8 0x4008f452 <rtc_cmd_write_mem+6>: extui a4, a4, 0, 2 0x4008f455 <rtc_cmd_write_mem+9>: extui a3, a3, 0, 5 0x4008f458 <rtc_cmd_write_mem+12>: or a4, a4, a9 0x4008f45b <rtc_cmd_write_mem+15>: extui a2, a2, 0, 3 0x4008f45e <rtc_cmd_write_mem+18>: slli a3, a3, 2 0x4008f461 <rtc_cmd_write_mem+21>: or a3, a4, a3 0x4008f464 <rtc_cmd_write_mem+24>: slli a2, a2, 7 0x4008f467 <rtc_cmd_write_mem+27>: or a2, a3, a2 0x4008f46a <rtc_cmd_write_mem+30>: retw.n (gdb) x /1x 0x400804d8 0x400804d8: 0x60000000
7.8 rtc_cmd_reg0_alu
0x4008f470 <rtc_cmd_reg0_alu>: entry a1, 32 0x4008f473 <rtc_cmd_reg0_alu+3>: l32r a9, 0x4008f46c 0x4008f476 <rtc_cmd_reg0_alu+6>: extui a4, a4, 0, 2 0x4008f479 <rtc_cmd_reg0_alu+9>: extui a3, a3, 0, 4 0x4008f47c <rtc_cmd_reg0_alu+12>: or a4, a4, a9 0x4008f47f <rtc_cmd_reg0_alu+15>: extui a2, a2, 0, 8 0x4008f482 <rtc_cmd_reg0_alu+18>: slli a3, a3, 2 0x4008f485 <rtc_cmd_reg0_alu+21>: or a3, a4, a3 0x4008f488 <rtc_cmd_reg0_alu+24>: slli a2, a2, 6 0x4008f48b <rtc_cmd_reg0_alu+27>: or a2, a3, a2 0x4008f48e <rtc_cmd_reg0_alu+30>: retw.n (gdb) x /1x 0x4008f46c 0x4008f46c: 0x70000000
7.9 rtc_cmd_stage_alu
0x4008f494 <rtc_cmd_stage_alu>: entry a1, 32 0x4008f497 <rtc_cmd_stage_alu+3>: l32r a9, 0x4008f490 0x4008f49a <rtc_cmd_stage_alu+6>: extui a3, a3, 0, 4 0x4008f49d <rtc_cmd_stage_alu+9>: extui a2, a2, 0, 4 0x4008f4a0 <rtc_cmd_stage_alu+12>: slli a3, a3, 2 0x4008f4a3 <rtc_cmd_stage_alu+15>: or a3, a3, a9 0x4008f4a6 <rtc_cmd_stage_alu+18>: slli a2, a2, 6 0x4008f4a9 <rtc_cmd_stage_alu+21>: or a2, a3, a2 0x4008f4ac <rtc_cmd_stage_alu+24>: retw.n (gdb) x /1x 0x4008f490 0x4008f490: 0x72000000
7.10 rtc_cmd_force_branch
0x4008f4b0 <rtc_cmd_force_branch>: entry a1, 32 0x4008f4b3 <rtc_cmd_force_branch+3>: l32r a8, 0x40080690 0x4008f4b6 <rtc_cmd_force_branch+6>: slli a2, a2, 17 0x4008f4b9 <rtc_cmd_force_branch+9>: or a2, a2, a8 0x4008f4bc <rtc_cmd_force_branch+12>: retw.n (gdb) x /1x 0x40080690 0x40080690: 0x80000000
7.11 rtc_cmd_reg0_branch
0x4008f4c4 <rtc_cmd_reg0_branch>: entry a1, 32 0x4008f4c7 <rtc_cmd_reg0_branch+3>: l32r a8, 0x4008f4c0 0x4008f4ca <rtc_cmd_reg0_branch+6>: slli a3, a3, 16 0x4008f4cd <rtc_cmd_reg0_branch+9>: or a4, a4, a8 0x4008f4d0 <rtc_cmd_reg0_branch+12>: or a3, a4, a3 0x4008f4d3 <rtc_cmd_reg0_branch+15>: slli a2, a2, 17 0x4008f4d6 <rtc_cmd_reg0_branch+18>: or a2, a3, a2 0x4008f4d9 <rtc_cmd_reg0_branch+21>: retw.n (gdb) x /1x 0x4008f4c0 0x4008f4c0: 0x82000000
7.12 rtc_cmd_stage_branch
0x4008f4dc <rtc_cmd_stage_branch>: entry a1, 32 0x4008f4df <rtc_cmd_stage_branch+3>: l32r a9, 0x400807d0 0x4008f4e2 <rtc_cmd_stage_branch+6>: extui a4, a4, 0, 4 0x4008f4e5 <rtc_cmd_stage_branch+9>: extui a3, a3, 0, 2 0x4008f4e8 <rtc_cmd_stage_branch+12>: or a4, a4, a9 0x4008f4eb <rtc_cmd_stage_branch+15>: extui a2, a2, 0, 8 0x4008f4ee <rtc_cmd_stage_branch+18>: slli a3, a3, 15 0x4008f4f1 <rtc_cmd_stage_branch+21>: or a3, a4, a3 0x4008f4f4 <rtc_cmd_stage_branch+24>: slli a2, a2, 17 0x4008f4f7 <rtc_cmd_stage_branch+27>: or a2, a3, a2 0x4008f4fa <rtc_cmd_stage_branch+30>: retw.n (gdb) x /1x 0x400807d0 0x400807d0: 0x84000000
7.13 rtc_cmd_cpu_wakeup
0x4008f500 <rtc_cmd_cpu_wakeup>: entry a1, 32 0x4008f503 <rtc_cmd_cpu_wakeup+3>: l32r a8, 0x4008f4fc 0x4008f506 <rtc_cmd_cpu_wakeup+6>: or a2, a2, a8 0x4008f509 <rtc_cmd_cpu_wakeup+9>: retw.n (gdb) x /1x 0x4008f4fc 0x4008f4fc: 0x90000000
7.14 rtc_cmd_sleep_cyc_sel
0x4008f510 <rtc_cmd_sleep_cyc_sel>: entry a1, 32 0x4008f513 <rtc_cmd_sleep_cyc_sel+3>: l32r a8, 0x4008f50c 0x4008f516 <rtc_cmd_sleep_cyc_sel+6>: or a2, a2, a8 0x4008f519 <rtc_cmd_sleep_cyc_sel+9>: retw.n (gdb) x /1x 0x4008f50c 0x4008f50c: 0x92000000
7.15 rtc_cmd_meas_end
0x4008f520 <rtc_cmd_meas_end>: entry a1, 32 0x4008f523 <rtc_cmd_meas_end+3>: l32r a2, 0x4008f51c 0x4008f526 <rtc_cmd_meas_end+6>: retw.n (gdb) x /1x 0x4008f51c 0x4008f51c: 0xb0000000
