ESP32 RTC

1 Memory

1.1 FAST Memory

RTC FAST Memory 为 8 KB SRAM，其只能被 PRO_CPU 通过数据总线 0x3FF8_0000 ~ 0x3FF8_1FFF 读写，或被 PRO_CPU 通过指令总线 0x400C_0000~0x400C_1FFF 读写。与其他存储器不同，APP_CPU 不能访问 RTC FAST Memory

PRO_CPU 的这两段地址同序访问 RTC FAST Memory。即地址 0x3FF8_0000 与 0x400C_0000 访问到相同的 word，0x3FF8_0004与0x400C_0004访问到相同的word，0x3FF8_0008与0x400C_0008访问到相同的word， 以此类推。APP_CPU 的这两段地址不能访问到 RTC FAST Memory，也不能访问到其他任何目标

1.2 SLOW Memory

RTC SLOW Memory 为 8 KB SRAM，其可以被两个 CPU 通过数据总线与指令总线共用地址段 0x5000_0000 ~ 0x5000_1FFF 读写。

2 Register

2.1 RTC IO

components/esp32/include/soc/rtc_io_reg.h

#define DR_REG_RTCIO_BASE                       0x3ff48400

#define RTC_GPIO_OUT_REG           (DR_REG_RTCIO_BASE + 0x0)
#define RTC_GPIO_OUT_W1TS_REG      (DR_REG_RTCIO_BASE + 0x4)
#define RTC_GPIO_OUT_W1TC_REG      (DR_REG_RTCIO_BASE + 0x8)
#define RTC_GPIO_ENABLE_REG        (DR_REG_RTCIO_BASE + 0xc)
#define RTC_GPIO_ENABLE_W1TS_REG   (DR_REG_RTCIO_BASE + 0x10)
#define RTC_GPIO_ENABLE_W1TC_REG   (DR_REG_RTCIO_BASE + 0x14)
#define RTC_GPIO_STATUS_REG        (DR_REG_RTCIO_BASE + 0x18)
#define RTC_GPIO_STATUS_W1TS_REG   (DR_REG_RTCIO_BASE + 0x1c)
#define RTC_GPIO_STATUS_W1TC_REG   (DR_REG_RTCIO_BASE + 0x20)
#define RTC_GPIO_IN_REG            (DR_REG_RTCIO_BASE + 0x24)
#define RTC_GPIO_PIN0_REG          (DR_REG_RTCIO_BASE + 0x28)
#define RTC_GPIO_PIN1_REG          (DR_REG_RTCIO_BASE + 0x2c)
#define RTC_GPIO_PIN2_REG          (DR_REG_RTCIO_BASE + 0x30)
#define RTC_GPIO_PIN3_REG          (DR_REG_RTCIO_BASE + 0x34)
#define RTC_GPIO_PIN4_REG          (DR_REG_RTCIO_BASE + 0x38)
#define RTC_GPIO_PIN5_REG          (DR_REG_RTCIO_BASE + 0x3c)
#define RTC_GPIO_PIN6_REG          (DR_REG_RTCIO_BASE + 0x40)
#define RTC_GPIO_PIN7_REG          (DR_REG_RTCIO_BASE + 0x44)
#define RTC_GPIO_PIN8_REG          (DR_REG_RTCIO_BASE + 0x48)
#define RTC_GPIO_PIN9_REG          (DR_REG_RTCIO_BASE + 0x4c)
#define RTC_GPIO_PIN10_REG          (DR_REG_RTCIO_BASE + 0x50)
#define RTC_GPIO_PIN11_REG          (DR_REG_RTCIO_BASE + 0x54)
#define RTC_GPIO_PIN12_REG          (DR_REG_RTCIO_BASE + 0x58)
#define RTC_GPIO_PIN13_REG          (DR_REG_RTCIO_BASE + 0x5c)
#define RTC_GPIO_PIN14_REG          (DR_REG_RTCIO_BASE + 0x60)
#define RTC_GPIO_PIN15_REG          (DR_REG_RTCIO_BASE + 0x64)
#define RTC_GPIO_PIN16_REG          (DR_REG_RTCIO_BASE + 0x68)
#define RTC_GPIO_PIN17_REG          (DR_REG_RTCIO_BASE + 0x6c)
#define RTC_IO_RTC_DEBUG_SEL_REG    (DR_REG_RTCIO_BASE + 0x70)
#define RTC_IO_DIG_PAD_HOLD_REG     (DR_REG_RTCIO_BASE + 0x74)

#define RTC_IO_HALL_SENS_REG        (DR_REG_RTCIO_BASE + 0x78)

#define RTC_IO_SENSOR_PADS_REG      (DR_REG_RTCIO_BASE + 0x7c)
#define RTC_IO_ADC_PAD_REG          (DR_REG_RTCIO_BASE + 0x80)
#define RTC_IO_PAD_DAC1_REG         (DR_REG_RTCIO_BASE + 0x84)
#define RTC_IO_PAD_DAC2_REG         (DR_REG_RTCIO_BASE + 0x88)
#define RTC_IO_XTAL_32K_PAD_REG        (DR_REG_RTCIO_BASE + 0x8c)
#define RTC_IO_TOUCH_CFG_REG           (DR_REG_RTCIO_BASE + 0x90)
#define RTC_IO_TOUCH_PAD0_REG          (DR_REG_RTCIO_BASE + 0x94)
#define RTC_IO_TOUCH_PAD1_REG          (DR_REG_RTCIO_BASE + 0x98)
#define RTC_IO_TOUCH_PAD2_REG          (DR_REG_RTCIO_BASE + 0x9c)
#define RTC_IO_TOUCH_PAD3_REG          (DR_REG_RTCIO_BASE + 0xa0)
#define RTC_IO_TOUCH_PAD4_REG          (DR_REG_RTCIO_BASE + 0xa4)
#define RTC_IO_TOUCH_PAD5_REG          (DR_REG_RTCIO_BASE + 0xa8)
#define RTC_IO_TOUCH_PAD6_REG          (DR_REG_RTCIO_BASE + 0xac)
#define RTC_IO_TOUCH_PAD7_REG          (DR_REG_RTCIO_BASE + 0xb0)

#define RTC_IO_TOUCH_PAD8_REG          (DR_REG_RTCIO_BASE + 0xb4)
#define RTC_IO_TOUCH_PAD9_REG          (DR_REG_RTCIO_BASE + 0xb8)

#define RTC_IO_EXT_WAKEUP0_REG         (DR_REG_RTCIO_BASE + 0xbc)
#define RTC_IO_XTL_EXT_CTR_REG         (DR_REG_RTCIO_BASE + 0xc0)
#define RTC_IO_SAR_I2C_IO_REG          (DR_REG_RTCIO_BASE + 0xc4)
#define RTC_IO_DATE_REG                (DR_REG_RTCIO_BASE + 0xc8)

2.2 RTC Ctrl

components/esp32/include/soc/rtc_cntl_reg.h

/**************************************************************************************
  *                                       Note:                                       *
  *       Some Rtc memory and registers are used, in ROM or in internal library.      *
  *          Please do not use reserved or used rtc memory or registers.              *
  *                                                                                   *
  *************************************************************************************
  *                          RTC  Memory & Store Register usage
  *************************************************************************************
  *     rtc memory addr         type    size            usage
  *     0x3ff61000(0x50000000)  Slow    SIZE_CP         Co-Processor code/Reset Entry
  *     0x3ff61000+SIZE_CP      Slow    4096-SIZE_CP
  *     0x3ff62800              Slow    4096            Reserved
  *
  *     0x3ff80000(0x400c0000)  Fast    8192            deep sleep entry code
  *
  *************************************************************************************
  *     Rtc store registers     usage
  *     RTC_CNTL_STORE0_REG
  *     RTC_CNTL_STORE1_REG
  *     RTC_CNTL_STORE2_REG
  *     RTC_CNTL_STORE3_REG
  *     RTC_CNTL_STORE4_REG     Reserved
  *     RTC_CNTL_STORE5_REG     External Xtal Frequency
  *     RTC_CNTL_STORE6_REG     FAST_RTC_MEMORY_ENTRY
  *     RTC_CNTL_STORE7_REG     FAST_RTC_MEMORY_CRC
  *************************************************************************************
*/
#define DR_REG_RTCCNTL_BASE                     0x3ff48000

#define RTC_CNTL_OPTIONS0_REG        (DR_REG_RTCCNTL_BASE + 0x0)
#define RTC_CNTL_SLP_TIMER0_REG      (DR_REG_RTCCNTL_BASE + 0x4)
#define RTC_CNTL_SLP_TIMER1_REG      (DR_REG_RTCCNTL_BASE + 0x8)
#define RTC_CNTL_TIME_UPDATE_REG     (DR_REG_RTCCNTL_BASE + 0xc)
#define RTC_CNTL_TIME0_REG           (DR_REG_RTCCNTL_BASE + 0x10)
#define RTC_CNTL_TIME1_REG           (DR_REG_RTCCNTL_BASE + 0x14)
#define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x18)
#define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x1c)
#define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x20)
#define RTC_CNTL_TIMER3_REG          (DR_REG_RTCCNTL_BASE + 0x24)
#define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x28)
#define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x2c)
#define RTC_CNTL_ANA_CONF_REG        (DR_REG_RTCCNTL_BASE + 0x30)
#define RTC_CNTL_RESET_STATE_REG     (DR_REG_RTCCNTL_BASE + 0x34)
#define RTC_CNTL_WAKEUP_STATE_REG    (DR_REG_RTCCNTL_BASE + 0x38)
#define RTC_CNTL_INT_ENA_REG         (DR_REG_RTCCNTL_BASE + 0x3c)
#define RTC_CNTL_INT_RAW_REG         (DR_REG_RTCCNTL_BASE + 0x40)
#define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x44)
#define RTC_CNTL_INT_CLR_REG         (DR_REG_RTCCNTL_BASE + 0x48)
#define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x4c)
#define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x50)
#define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x54)
#define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x58)
#define RTC_CNTL_EXT_XTL_CONF_REG        (DR_REG_RTCCNTL_BASE + 0x5c)
#define RTC_CNTL_EXT_WAKEUP_CONF_REG     (DR_REG_RTCCNTL_BASE + 0x60)
#define RTC_CNTL_SLP_REJECT_CONF_REG     (DR_REG_RTCCNTL_BASE + 0x64)
#define RTC_CNTL_CPU_PERIOD_CONF_REG     (DR_REG_RTCCNTL_BASE + 0x68)
#define RTC_CNTL_SDIO_ACT_CONF_REG       (DR_REG_RTCCNTL_BASE + 0x6c)
#define RTC_CNTL_CLK_CONF_REG            (DR_REG_RTCCNTL_BASE + 0x70)
#define RTC_CNTL_SDIO_CONF_REG           (DR_REG_RTCCNTL_BASE + 0x74)
#define RTC_CNTL_BIAS_CONF_REG           (DR_REG_RTCCNTL_BASE + 0x78)
#define RTC_CNTL_REG                     (DR_REG_RTCCNTL_BASE + 0x7c)
#define RTC_CNTL_PWC_REG                 (DR_REG_RTCCNTL_BASE + 0x80)
#define RTC_CNTL_DIG_PWC_REG             (DR_REG_RTCCNTL_BASE + 0x84)
#define RTC_CNTL_DIG_ISO_REG             (DR_REG_RTCCNTL_BASE + 0x88)
#define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x8c)
#define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x90)
#define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0x94)
#define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0x98)
#define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0x9c)
#define RTC_CNTL_WDTFEED_REG             (DR_REG_RTCCNTL_BASE + 0xa0)
#define RTC_CNTL_WDTWPROTECT_REG         (DR_REG_RTCCNTL_BASE + 0xa4)
#define RTC_CNTL_TEST_MUX_REG            (DR_REG_RTCCNTL_BASE + 0xa8)
#define RTC_CNTL_SW_CPU_STALL_REG        (DR_REG_RTCCNTL_BASE + 0xac)
#define RTC_CNTL_STORE4_REG              (DR_REG_RTCCNTL_BASE + 0xb0)
#define RTC_CNTL_STORE5_REG              (DR_REG_RTCCNTL_BASE + 0xb4)
#define RTC_CNTL_STORE6_REG              (DR_REG_RTCCNTL_BASE + 0xb8)
#define RTC_CNTL_STORE7_REG              (DR_REG_RTCCNTL_BASE + 0xbc)
#define RTC_CNTL_DIAG0_REG               (DR_REG_RTCCNTL_BASE + 0xc0)
#define RTC_CNTL_DIAG1_REG               (DR_REG_RTCCNTL_BASE + 0xc4)
#define RTC_CNTL_HOLD_FORCE_REG          (DR_REG_RTCCNTL_BASE + 0xc8)
#define RTC_CNTL_EXT_WAKEUP1_REG         (DR_REG_RTCCNTL_BASE + 0xcc)
#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG  (DR_REG_RTCCNTL_BASE + 0xd0)
#define RTC_CNTL_BROWN_OUT_REG           (DR_REG_RTCCNTL_BASE + 0xd4)
#define RTC_MEM_CONF                     (DR_REG_RTCCNTL_BASE + 0x40 * 4)
#define RTC_MEM_CRC_RES                  (DR_REG_RTCCNTL_BASE + 0x41 * 4)
#define RTC_CNTL_DATE_REG                (DR_REG_RTCCNTL_BASE + 0x13c)

3 Power Consumption

We are care of Deep-Sleep mode:

• The ULP co-porcessor is powered on: 150uA current consumption
• ULP sensor-monitored pattern: 25uA @ 1% duty
• RTC timer + RTC memory: 10uA

And Hibernate Mode:

• The internal 8MHz oscillator and ULP coprocessor are disabled
• The RTC recovery memory are power-down
• Only one RTC timer on the slow clock and some RTC GPIOs are active.
• The RTC timer or the RTC GPIOs can wake up the chip from the Hibernation mode

• Power Consumption: 2.5uA

4 Clock

The RTC clock has five possible sources:

• External low speed (32 KHz) crystal clock
• External crystal clock divided by 4 (40MHz/4 ?)
• Internal RC oscillator (typically about 150 KHz and adjustable)
• Internal 8 MHz oscillator
• Internal 31.25KHz clock (derived from the internal 8MHz oscillator divided by 256)

The related register:

#define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x70)
/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
/*description: slow_clk_rtc sel. 0: SLOW_CK  1: CK_XTAL_32K  2: CK8M_D256_OUT*/
#define RTC_CNTL_ANA_CLK_RTC_SEL  0x00000003
#define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
#define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
#define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: fast_clk_rtc sel. 0: XTAL div 4  1: CK8M*/
#define RTC_CNTL_FAST_CLK_RTC_SEL  (BIT(29))
#define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
#define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
#define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: SOC clock sel. 0: XTAL  1: PLL  2: CK8M  3: APLL*/
#define RTC_CNTL_SOC_CLK_SEL  0x00000003
#define RTC_CNTL_SOC_CLK_SEL_M  ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S))
#define RTC_CNTL_SOC_CLK_SEL_V  0x3
#define RTC_CNTL_SOC_CLK_SEL_S  27
/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
/*description: CK8M force power up*/
#define RTC_CNTL_CK8M_FORCE_PU  (BIT(26))
#define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
#define RTC_CNTL_CK8M_FORCE_PU_V  0x1
#define RTC_CNTL_CK8M_FORCE_PU_S  26
/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */
/*description: CK8M force power down*/
#define RTC_CNTL_CK8M_FORCE_PD  (BIT(25))
#define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
#define RTC_CNTL_CK8M_FORCE_PD_V  0x1
#define RTC_CNTL_CK8M_FORCE_PD_S  25
/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */
/*description: CK8M_DFREQ*/
#define RTC_CNTL_CK8M_DFREQ  0x000000FF
#define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
#define RTC_CNTL_CK8M_DFREQ_V  0xFF
#define RTC_CNTL_CK8M_DFREQ_S  17
/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
/*description: CK8M force no gating during sleep*/
#define RTC_CNTL_CK8M_FORCE_NOGATING  (BIT(16))
#define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
#define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
#define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */
/*description: XTAL force no gating during sleep*/
#define RTC_CNTL_XTAL_FORCE_NOGATING  (BIT(15))
#define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
#define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
#define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */
/*description: divider = reg_ck8m_div_sel + 1*/
#define RTC_CNTL_CK8M_DIV_SEL  0x00000007
#define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
#define RTC_CNTL_CK8M_DIV_SEL_V  0x7
#define RTC_CNTL_CK8M_DIV_SEL_S  12
/* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */
/*description: */
#define RTC_CNTL_CK8M_DFREQ_FORCE  (BIT(11))
#define RTC_CNTL_CK8M_DFREQ_FORCE_M  (BIT(11))
#define RTC_CNTL_CK8M_DFREQ_FORCE_V  0x1
#define RTC_CNTL_CK8M_DFREQ_FORCE_S  11
/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
/*description: enable CK8M for digital core (no relationship with RTC core)*/
#define RTC_CNTL_DIG_CLK8M_EN  (BIT(10))
#define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
#define RTC_CNTL_DIG_CLK8M_EN_V  0x1
#define RTC_CNTL_DIG_CLK8M_EN_S  10
/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
#define RTC_CNTL_DIG_CLK8M_D256_EN  (BIT(9))
#define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
#define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
#define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
#define RTC_CNTL_DIG_XTAL32K_EN  (BIT(8))
#define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
#define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
#define RTC_CNTL_DIG_XTAL32K_EN_S  8
/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */
/*description: 1: CK8M_D256_OUT is actually CK8M  0: CK8M_D256_OUT is CK8M divided by 256*/
#define RTC_CNTL_ENB_CK8M_DIV  (BIT(7))
#define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
#define RTC_CNTL_ENB_CK8M_DIV_V  0x1
#define RTC_CNTL_ENB_CK8M_DIV_S  7
/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */
/*description: disable CK8M and CK8M_D256_OUT*/
#define RTC_CNTL_ENB_CK8M  (BIT(6))
#define RTC_CNTL_ENB_CK8M_M  (BIT(6))
#define RTC_CNTL_ENB_CK8M_V  0x1
#define RTC_CNTL_ENB_CK8M_S  6
/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */
/*description: CK8M_D256_OUT divider. 00: div128  01: div256  10: div512  11: div1024.*/
#define RTC_CNTL_CK8M_DIV  0x00000003
#define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
#define RTC_CNTL_CK8M_DIV_V  0x3
#define RTC_CNTL_CK8M_DIV_S  4


#define RTC_IO_XTAL_32K_PAD_REG          (DR_REG_RTCIO_BASE + 0x8c)

5 API

#define DEEP_SLEEP_PD_NORMAL         BIT(0)   /* Base deep sleep mode */
#define DEEP_SLEEP_PD_RTC_PERIPH     BIT(1)   /* Power down RTC peripherals */
#define DEEP_SLEEP_PD_RTC_SLOW_MEM   BIT(2)   /* Power down RTC SLOW memory */
#define DEEP_SLEEP_PD_RTC_FAST_MEM   BIT(3)   /* Power down RTC FAST memory */

/*
 * @brief Prepare for entering sleep mode
 * @param deep_slp   DEEP_SLEEP_PD_ flags combined with OR (DEEP_SLEEP_PD_NORMAL must be included)
 * @param cpu_lp_mode  for deep sleep, should be 0
 */
void rtc_slp_prep_lite(uint32_t deep_slp, uint32_t cpu_lp_mode);

#define RTC_EXT_EVENT0_TRIG     BIT(0)
#define RTC_EXT_EVENT1_TRIG     BIT(1)
#define RTC_GPIO_TRIG           BIT(2)          /* Only available in light sleep */
#define RTC_TIMER_EXPIRE        BIT(3)
#define RTC_SDIO_TRIG           BIT(4)
#define RTC_MAC_TRIG            BIT(5)
#define RTC_UART0_TRIG          BIT(6)
#define RTC_UART1_TRIG          BIT(7)
#define RTC_TOUCH_TRIG          BIT(8)                                 
#define RTC_SAR_TRIG            BIT(9)                                 
#define RTC_BT_TRIG             BIT(10)                                

/*
 * @brief Enter sleep mode for given number of cycles
 * @param cycles_h  higher 32 bit part of number of slow clock cycles
 * @param cycles_l  lower 32 bit part of number of slow clock cycles
 * @param wakeup_opt  wake up reason to enable (RTC_xxx_TRIG flags combined with OR)
 * @param reject_opt  reserved, should be 0
 * @return TBD
 */
uint32_t rtc_sleep(uint32_t cycles_h, uint32_t cycles_l, uint32_t wakeup_opt, uint32_t reject_opt);

5.1 rtc_sleep_prep

(gdb) x /345i  rtc_slp_prep

More details: ESP32 RTC Sleep Prepare

5.2 rtc_sleep

   0x4009011c <rtc_sleep>:	entry	a1, 32
   0x4009011f <rtc_sleep+3>:	l32r	a9, 0x4008ff08   /* a9 = *(0x4008ff08) = 0x3ff4800c */
   0x40090122 <rtc_sleep+6>:	l32r	a11, 0x4008073c  /* a11 = *(0x4008073c) = 0x80000000 */
   0x40090125 <rtc_sleep+9>:	memw
   0x40090128 <rtc_sleep+12>:	l32i.n	a8, a9, 0        /* a8 = *(0x3ff4800c) = 0x40000000 */
   0x4009012a <rtc_sleep+14>:	l32r	a10, 0x40080630  /* a10 = *(0x40080630) = 0x40000000 */
   0x4009012d <rtc_sleep+17>:	or	a8, a8, a11
   0x40090130 <rtc_sleep+20>:	memw
   0x40090133 <rtc_sleep+23>:	s32i.n	a8, a9, 0        /* *(0x3ff4800c) = 0xC0000000 */
   0x40090135 <rtc_sleep+25>:	memw
   0x40090138 <rtc_sleep+28>:	l32i.n	a8, a9, 0        /* a8 = 0xC0000000 */
   0x4009013a <rtc_sleep+30>:	bnone	a8, a10, 0x40090135  /* if (a8 & a19 == 0)  branch */
   0x4009013d <rtc_sleep+33>:	l32r	a10, 0x4008ff0c  /* a10 = *(0x4008ff0c) = 0x3ff48048, RTC_CNTL_INT_CLR_REG */
   0x40090140 <rtc_sleep+36>:	movi.n	a8, 16           /* a8 = 16 = 0x10 */
   0x40090142 <rtc_sleep+38>:	memw
   0x40090145 <rtc_sleep+41>:	l32i.n	a9, a10, 0       /* a9 = *(0x3ff48048) = 0x0 */
   0x40090147 <rtc_sleep+43>:	or	a8, a9, a8           /* Clear RTC time valid interrupt state */
   0x4009014a <rtc_sleep+46>:	memw
   0x4009014d <rtc_sleep+49>:	s32i.n	a8, a10, 0      /* update to *(0x3ff48048), RTC_CNTL_INT_CLR_REG */
   0x4009014f <rtc_sleep+51>:	l32r	a8, 0x4008ff10  /* a8 = *(0x4008ff10) = 0x3ff48010 RTC_CNTL_TIME0_REG */
   0x40090152 <rtc_sleep+54>:	l32r	a9, 0x4008ff14  /* a9 = *(0x4008ff14) = 0x3ff48014 RTC_CNTL_TIME1_REG */
   0x40090155 <rtc_sleep+57>:	memw
   0x40090158 <rtc_sleep+60>:	l32i.n	a8, a8, 0       /* a8 = *(0x3ff48010) = 0x000124ee, time0 value */
   0x4009015a <rtc_sleep+62>:	memw
   0x4009015d <rtc_sleep+65>:	l32i.n	a12, a9, 0      /* a12 = *(0x3ff48014) = 0x0, time1 value */
   0x4009015f <rtc_sleep+67>:	add.n	a8, a3, a8      /* a8 += 2nd_param, 2nd_param is cycles_l */
   0x40090161 <rtc_sleep+69>:	movi.n	a9, 1           /* a9 = 1 */
   0x40090163 <rtc_sleep+71>:	bltu	a8, a3, 0x40090169  /* if (a8 < a3); branch */
   0x40090166 <rtc_sleep+74>:	movi	a9, 0           /* a9 = 0 */
   0x40090169 <rtc_sleep+77>:	l32r	a3, 0x4008ff64  /* a3 = *(0x4008ff64) = 0x3ff48004, RTC_CNTL_SLP_TIME0_REG */
   0x4009016c <rtc_sleep+80>:	add.n	a2, a2, a12     /* a2 = 1st_param_cycles_h + a12 */
   0x4009016e <rtc_sleep+82>:	memw
   0x40090171 <rtc_sleep+85>:	s32i.n	a8, a3, 0       /* update a8 into RTC_CNTL_SLP_TIME0_REG */
   0x40090173 <rtc_sleep+87>:	l32r	a8, 0x4008ff68  /* a8 = *(0x4008ff68) = 0x3ff48008, RTC_CNTL_SLP_TIME1_REG */
   0x40090176 <rtc_sleep+90>:	l32r	a3, 0x4008ff84  /* a3 = *(0x4008ff84) = 0x3ff48038, RTC_CNTL_WAKEUP_STATE_REG */
   0x40090179 <rtc_sleep+93>:	add.n	a9, a9, a2      /* a9 += a2, time1_val + cycles_h */
   0x4009017b <rtc_sleep+95>:	memw
   0x4009017e <rtc_sleep+98>:	s32i.n	a9, a8, 0       /* update a9 into RTC_CNTL_SLP_TIME1_REG */
   0x40090180 <rtc_sleep+100>:	memw

   0x40090183 <rtc_sleep+103>:	l32i.n	a8, a3, 0      /* a8 = *(0x3ff48038) = 0x00006000, read RTC_CNTL_WAKEUP_STATE_REG */
   0x40090185 <rtc_sleep+105>:	l32r	a2, 0x4008d188 /* a2 = *(0x4008d188) = 0xffc007ff */
   0x40090188 <rtc_sleep+108>:	extui	a4, a4, 0, 11  /* a4 is the 3rd param, extract the low 11 bits */
   0x4009018b <rtc_sleep+111>:	and	a2, a8, a2         /* a2 = RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff (only bitpos:[21:11]) */
   0x4009018e <rtc_sleep+114>:	slli	a4, a4, 11     /* a4 <<= 11 */
   0x40090191 <rtc_sleep+117>:	or	a4, a4, a2         /* a4 = wakeup_opt | (RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff) */
   0x40090194 <rtc_sleep+120>:	l32r	a2, 0x4008ff88 /* a2 = *(0x4008ff88) = 0x3ff48064, RTC_CNTL_SLP_REJECT_CONF_REG */
   0x40090197 <rtc_sleep+123>:	memw
   0x4009019a <rtc_sleep+126>:	s32i.n	a4, a3, 0      /* update the a4 into RTC_CNTL_WAKEUP_STATE_REG */
   0x4009019c <rtc_sleep+128>:	l32r	a3, 0x4008d1f0 /* a3 = *(0x4008d1f0) = 0x3ff48018, RTC_CNTL_STATE0_REG */
   0x4009019f <rtc_sleep+131>:	memw
   0x400901a2 <rtc_sleep+134>:	s32i.n	a5, a2, 0  /* update the a5 (4th param) into RTC_CNTL_SLP_REJECT_CONF_REG directly */
   0x400901a4 <rtc_sleep+136>:	memw

   0x400901a7 <rtc_sleep+139>:	l32i.n	a2, a3, 0      /* a2 = *(0x3ff48018) = 0x20300000, read RTC_CNTL_STATE0_REG */
   0x400901a9 <rtc_sleep+141>:	l32r	a9, 0x4008ffb8 /* a9 = *(0x4008ffb8) = 0x3ff48040, RTC_CNTL_INT_RAW_REG */
   0x400901ac <rtc_sleep+144>:	or	a11, a2, a11       /* a11 = RTC_CNTL_STATE0_REG | 0x8000 0000 */
   0x400901af <rtc_sleep+147>:	memw
   0x400901b2 <rtc_sleep+150>:	s32i.n	a11, a3, 0     /* update a11 into RTC_CNTL_STATE0_REG */
   0x400901b4 <rtc_sleep+152>:	memw
   0x400901b7 <rtc_sleep+155>:	l32i.n	a8, a9, 0      /* a8 = *(0x3ff48040) = 0x0000 0014, read RTC_CNTL_INT_RAW_REG */
   0x400901b9 <rtc_sleep+157>:	extui	a8, a8, 0, 2   /* a8 = extract the low 2 bits of a8 */
   0x400901bc <rtc_sleep+160>:	beqz	a8, 0x400901b4 /* if (a8 == 0); branch */
   0x400901bf <rtc_sleep+163>:	memw
   0x400901c2 <rtc_sleep+166>:	l32i.n	a2, a9, 0      /* a2 = *(0x3ff48040) = 0x0000 0014, read RTC_CNTL_INT_RAW_REG */
   0x400901c4 <rtc_sleep+168>:	memw
   0x400901c7 <rtc_sleep+171>:	l32i.n	a4, a10, 0     /* a4 = *(0x3ff48048) = 0x0, read RTC_CNTL_INT_CLR_REG */
   0x400901c9 <rtc_sleep+173>:	movi.n	a3, 3          /* a3 = 3 */
   0x400901cb <rtc_sleep+175>:	or	a3, a4, a3         /* a3 |= a4, set the clear bit of the reject_int and wakeup_int */
   0x400901ce <rtc_sleep+178>:	memw
   0x400901d1 <rtc_sleep+181>:	s32i.n	a3, a10, 0     /* update the a3 into RTC_CNTL_INT_CLR_REG */
   0x400901d3 <rtc_sleep+183>:	extui	a2, a2, 1, 1   /* a2 = (a2 >> 1) & 0x1, return a2 */
   0x400901d6 <rtc_sleep+186>:	retw.n

5.3 Undocumented

5.3.1 rtc_pads_muxsel

Set the pad route to the digital IO_MUX (1) or RTC block (0)

   0x4008d1a8 <rtc_pads_muxsel>:	entry	a1, 32
   0x4008d1ab <rtc_pads_muxsel+3>:	bbci	a2, 0, 0x4008d1cc <rtc_pads_muxsel+36>
   0x4008d1ae <rtc_pads_muxsel+6>:	l32r	a8, 0x4008c9b4
   0x4008d1b1 <rtc_pads_muxsel+9>:	l32r	a9, 0x40084bc0  /* a9 = *(0x40084bc0) = 0xf7ffffff, BIT(27) */
   0x4008d1b4 <rtc_pads_muxsel+12>:	memw
   0x4008d1b7 <rtc_pads_muxsel+15>:	l32i	a11, a8, 0
   0x4008d1ba <rtc_pads_muxsel+18>:	extui	a10, a3, 0, 1
   0x4008d1bd <rtc_pads_muxsel+21>:	slli	a10, a10, 27
   0x4008d1c0 <rtc_pads_muxsel+24>:	and	a9, a11, a9
   0x4008d1c3 <rtc_pads_muxsel+27>:	or	a9, a10, a9
   0x4008d1c6 <rtc_pads_muxsel+30>:	memw
   0x4008d1c9 <rtc_pads_muxsel+33>:	s32i	a9, a8, 0
   0x4008d1cc <rtc_pads_muxsel+36>:	bbci	a2, 1, 0x4008d1ed <rtc_pads_muxsel+69>
   0x4008d1cf <rtc_pads_muxsel+39>:	l32r	a8, 0x4008c9b4
   0x4008d1d2 <rtc_pads_muxsel+42>:	l32r	a9, 0x4008bebc
   0x4008d1d5 <rtc_pads_muxsel+45>:	memw
   0x4008d1d8 <rtc_pads_muxsel+48>:	l32i	a11, a8, 0
   0x4008d1db <rtc_pads_muxsel+51>:	extui	a10, a3, 0, 1
   0x4008d1de <rtc_pads_muxsel+54>:	slli	a10, a10, 26
   0x4008d1e1 <rtc_pads_muxsel+57>:	and	a9, a11, a9
   0x4008d1e4 <rtc_pads_muxsel+60>:	or	a9, a10, a9
   0x4008d1e7 <rtc_pads_muxsel+63>:	memw
   0x4008d1ea <rtc_pads_muxsel+66>:	s32i	a9, a8, 0
   0x4008d1ed <rtc_pads_muxsel+69>:	bbci	a2, 2, 0x4008d20d <rtc_pads_muxsel+101>
   0x4008d1f0 <rtc_pads_muxsel+72>:	l32r	a8, 0x4008c9b4
   0x4008d1f3 <rtc_pads_muxsel+75>:	l32r	a9, 0x40085f20
   0x4008d1f6 <rtc_pads_muxsel+78>:	memw
   0x4008d1f9 <rtc_pads_muxsel+81>:	l32i.n	a11, a8, 0
   0x4008d1fb <rtc_pads_muxsel+83>:	extui	a10, a3, 0, 1
   0x4008d1fe <rtc_pads_muxsel+86>:	slli	a10, a10, 25
   0x4008d201 <rtc_pads_muxsel+89>:	and	a9, a11, a9
   0x4008d204 <rtc_pads_muxsel+92>:	or	a9, a10, a9
   0x4008d207 <rtc_pads_muxsel+95>:	memw
   0x4008d20a <rtc_pads_muxsel+98>:	s32i	a9, a8, 0
   0x4008d20d <rtc_pads_muxsel+101>:	bbci	a2, 3, 0x4008d22d <rtc_pads_muxsel+133>
   0x4008d210 <rtc_pads_muxsel+104>:	l32r	a8, 0x4008c9b4
   0x4008d213 <rtc_pads_muxsel+107>:	l32r	a9, 0x4008beb4
   0x4008d216 <rtc_pads_muxsel+110>:	memw
   0x4008d219 <rtc_pads_muxsel+113>:	l32i.n	a11, a8, 0
   0x4008d21b <rtc_pads_muxsel+115>:	extui	a10, a3, 0, 1
   0x4008d21e <rtc_pads_muxsel+118>:	slli	a10, a10, 24
   0x4008d221 <rtc_pads_muxsel+121>:	and	a9, a11, a9
   0x4008d224 <rtc_pads_muxsel+124>:	or	a9, a10, a9
   0x4008d227 <rtc_pads_muxsel+127>:	memw
   0x4008d22a <rtc_pads_muxsel+130>:	s32i	a9, a8, 0
   0x4008d22d <rtc_pads_muxsel+133>:	bbci	a2, 4, 0x4008d24d <rtc_pads_muxsel+165>
   0x4008d230 <rtc_pads_muxsel+136>:	l32r	a8, 0x4008c9c8
   0x4008d233 <rtc_pads_muxsel+139>:	l32r	a9, 0x4008620c
   0x4008d236 <rtc_pads_muxsel+142>:	memw
   0x4008d239 <rtc_pads_muxsel+145>:	l32i.n	a11, a8, 0
   0x4008d23b <rtc_pads_muxsel+147>:	extui	a10, a3, 0, 1
   0x4008d23e <rtc_pads_muxsel+150>:	slli	a10, a10, 29
   0x4008d241 <rtc_pads_muxsel+153>:	and	a9, a11, a9
   0x4008d244 <rtc_pads_muxsel+156>:	or	a9, a10, a9
   0x4008d247 <rtc_pads_muxsel+159>:	memw
   0x4008d24a <rtc_pads_muxsel+162>:	s32i	a9, a8, 0
   0x4008d24d <rtc_pads_muxsel+165>:	bbci	a2, 5, 0x4008d26d <rtc_pads_muxsel+197>
   0x4008d250 <rtc_pads_muxsel+168>:	l32r	a8, 0x4008c9c8
   0x4008d253 <rtc_pads_muxsel+171>:	l32r	a9, 0x40087110
   0x4008d256 <rtc_pads_muxsel+174>:	memw
   0x4008d259 <rtc_pads_muxsel+177>:	l32i.n	a11, a8, 0
   0x4008d25b <rtc_pads_muxsel+179>:	extui	a10, a3, 0, 1
   0x4008d25e <rtc_pads_muxsel+182>:	slli	a10, a10, 28
   0x4008d261 <rtc_pads_muxsel+185>:	and	a9, a11, a9
   0x4008d264 <rtc_pads_muxsel+188>:	or	a9, a10, a9
   0x4008d267 <rtc_pads_muxsel+191>:	memw
   0x4008d26a <rtc_pads_muxsel+194>:	s32i	a9, a8, 0
   0x4008d26d <rtc_pads_muxsel+197>:	bbci	a2, 6, 0x4008d28d <rtc_pads_muxsel+229>
   0x4008d270 <rtc_pads_muxsel+200>:	l32r	a8, 0x4008bfa4
   0x4008d273 <rtc_pads_muxsel+203>:	l32r	a9, 0x400854d4
   0x4008d276 <rtc_pads_muxsel+206>:	memw
   0x4008d279 <rtc_pads_muxsel+209>:	l32i.n	a11, a8, 0
   0x4008d27b <rtc_pads_muxsel+211>:	extui	a10, a3, 0, 1
   0x4008d27e <rtc_pads_muxsel+214>:	slli	a10, a10, 17
   0x4008d281 <rtc_pads_muxsel+217>:	and	a9, a11, a9
   0x4008d284 <rtc_pads_muxsel+220>:	or	a9, a10, a9
   0x4008d287 <rtc_pads_muxsel+223>:	memw
   0x4008d28a <rtc_pads_muxsel+226>:	s32i	a9, a8, 0
   0x4008d28d <rtc_pads_muxsel+229>:	bbci	a2, 7, 0x4008d2ad <rtc_pads_muxsel+261>
   0x4008d290 <rtc_pads_muxsel+232>:	l32r	a8, 0x4008bfb0
......
......

typedef enum {
    RTC_GPIO0 = BIT(0),
    RTC_GPIO1 = BIT(1),
    ......
    ......
    RTC_GPIO17 = BIT(17)
} rtc_gpio_num_t;

/*
 * set == 1, route to digital IO_MUX
 * set == 0, route to RTC block
 */
void rtc_pads_muxsel(rtc_gpio_num_t rtc_gpio_num, uint8_t sel);

5.3.2 rtc_pads_funsel

Select the RTC function for this pad.

   0x4008d400 <rtc_pads_funsel>:	entry	a1, 32
   0x4008d403 <rtc_pads_funsel+3>:	bbci	a2, 0, 0x4008d424 <rtc_pads_funsel+36>
   0x4008d406 <rtc_pads_funsel+6>:	l32r	a8, 0x4008c9b4
   0x4008d409 <rtc_pads_funsel+9>:	l32r	a9, 0x4008bfac
   0x4008d40c <rtc_pads_funsel+12>:	memw
   0x4008d40f <rtc_pads_funsel+15>:	l32i	a11, a8, 0
   0x4008d412 <rtc_pads_funsel+18>:	extui	a10, a3, 0, 2
   0x4008d415 <rtc_pads_funsel+21>:	slli	a10, a10, 22
   0x4008d418 <rtc_pads_funsel+24>:	and	a9, a11, a9
   0x4008d41b <rtc_pads_funsel+27>:	or	a9, a10, a9
   0x4008d41e <rtc_pads_funsel+30>:	memw
   0x4008d421 <rtc_pads_funsel+33>:	s32i	a9, a8, 0
   0x4008d424 <rtc_pads_funsel+36>:	bbci	a2, 1, 0x4008d445 <rtc_pads_funsel+69>
   0x4008d427 <rtc_pads_funsel+39>:	l32r	a8, 0x4008c9b4
   0x4008d42a <rtc_pads_funsel+42>:	l32r	a9, 0x4008d3f0
   0x4008d42d <rtc_pads_funsel+45>:	memw
   0x4008d430 <rtc_pads_funsel+48>:	l32i	a11, a8, 0
   0x4008d433 <rtc_pads_funsel+51>:	extui	a10, a3, 0, 2
   0x4008d436 <rtc_pads_funsel+54>:	slli	a10, a10, 17
   0x4008d439 <rtc_pads_funsel+57>:	and	a9, a11, a9
   0x4008d43c <rtc_pads_funsel+60>:	or	a9, a10, a9
   0x4008d43f <rtc_pads_funsel+63>:	memw
   0x4008d442 <rtc_pads_funsel+66>:	s32i	a9, a8, 0
   0x4008d445 <rtc_pads_funsel+69>:	bbci	a2, 2, 0x4008d465 <rtc_pads_funsel+101>
   0x4008d448 <rtc_pads_funsel+72>:	l32r	a8, 0x4008c9b4
   0x4008d44b <rtc_pads_funsel+75>:	l32r	a9, 0x4008c274
   0x4008d44e <rtc_pads_funsel+78>:	memw
   0x4008d451 <rtc_pads_funsel+81>:	l32i.n	a11, a8, 0
   0x4008d453 <rtc_pads_funsel+83>:	extui	a10, a3, 0, 2
   0x4008d456 <rtc_pads_funsel+86>:	slli	a10, a10, 12
   0x4008d459 <rtc_pads_funsel+89>:	and	a9, a11, a9
   0x4008d45c <rtc_pads_funsel+92>:	or	a9, a10, a9
   0x4008d45f <rtc_pads_funsel+95>:	memw
   0x4008d462 <rtc_pads_funsel+98>:	s32i	a9, a8, 0
   0x4008d465 <rtc_pads_funsel+101>:	bbci	a2, 3, 0x4008d485 <rtc_pads_funsel+133>
   0x4008d468 <rtc_pads_funsel+104>:	l32r	a8, 0x4008c9b4
   0x4008d46b <rtc_pads_funsel+107>:	extui	a10, a3, 0, 2
   0x4008d46e <rtc_pads_funsel+110>:	memw
   0x4008d471 <rtc_pads_funsel+113>:	l32i.n	a11, a8, 0
   0x4008d473 <rtc_pads_funsel+115>:	movi	a9, 0xfffffe7f
   0x4008d476 <rtc_pads_funsel+118>:	slli	a10, a10, 7
   0x4008d479 <rtc_pads_funsel+121>:	and	a9, a11, a9
   0x4008d47c <rtc_pads_funsel+124>:	or	a9, a10, a9
   0x4008d47f <rtc_pads_funsel+127>:	memw
   0x4008d482 <rtc_pads_funsel+130>:	s32i	a9, a8, 0
   0x4008d485 <rtc_pads_funsel+133>:	bbci	a2, 4, 0x4008d4a5 <rtc_pads_funsel+165>
   0x4008d488 <rtc_pads_funsel+136>:	l32r	a8, 0x4008c9c8
......
......

typedef enum {
    RTC_GPIO0 = BIT(0),
    RTC_GPIO1 = BIT(1),
    ......
    ......
    RTC_GPIO17 = BIT(17)
} rtc_gpio_num_t;

/*
 * sel == 0, select the function 0 of rtc
 * sel == 1, select the function 1 of rtc
 * sel == 2, select the function 2 of rtc
 * sel == 3, select the function 3 of rtc
 */
void rtc_pads_funsel(rtc_gpio_num_t rtc_gpio_num, uint8_t sel);

5.3.3 rtc_pads_slpsel

Sleep mode selection signal of the pad, Set to 1 to put the pad in sleep mode

   0x4008d648 <rtc_pads_slpsel>:	entry	a1, 32
   0x4008d64b <rtc_pads_slpsel+3>:	bbci	a2, 0, 0x4008d66c <rtc_pads_slpsel+36>
   0x4008d64e <rtc_pads_slpsel+6>:	l32r	a8, 0x4008c9b4
   0x4008d651 <rtc_pads_slpsel+9>:	l32r	a9, 0x4008add4
   0x4008d654 <rtc_pads_slpsel+12>:	memw
   0x4008d657 <rtc_pads_slpsel+15>:	l32i	a11, a8, 0
   0x4008d65a <rtc_pads_slpsel+18>:	extui	a10, a3, 0, 1
   0x4008d65d <rtc_pads_slpsel+21>:	slli	a10, a10, 21
   0x4008d660 <rtc_pads_slpsel+24>:	and	a9, a11, a9
   0x4008d663 <rtc_pads_slpsel+27>:	or	a9, a10, a9
   0x4008d666 <rtc_pads_slpsel+30>:	memw
   0x4008d669 <rtc_pads_slpsel+33>:	s32i	a9, a8, 0
   0x4008d66c <rtc_pads_slpsel+36>:	bbci	a2, 1, 0x4008d68d <rtc_pads_slpsel+69>
   0x4008d66f <rtc_pads_slpsel+39>:	l32r	a8, 0x4008c9b4
   0x4008d672 <rtc_pads_slpsel+42>:	l32r	a9, 0x4008bf98
   0x4008d675 <rtc_pads_slpsel+45>:	memw
   0x4008d678 <rtc_pads_slpsel+48>:	l32i	a11, a8, 0
   0x4008d67b <rtc_pads_slpsel+51>:	extui	a10, a3, 0, 1
   0x4008d67e <rtc_pads_slpsel+54>:	slli	a10, a10, 16
   0x4008d681 <rtc_pads_slpsel+57>:	and	a9, a11, a9
   0x4008d684 <rtc_pads_slpsel+60>:	or	a9, a10, a9
   0x4008d687 <rtc_pads_slpsel+63>:	memw
   0x4008d68a <rtc_pads_slpsel+66>:	s32i	a9, a8, 0
   0x4008d68d <rtc_pads_slpsel+69>:	bbci	a2, 2, 0x4008d6ad <rtc_pads_slpsel+101>
   0x4008d690 <rtc_pads_slpsel+72>:	l32r	a8, 0x4008c9b4
   0x4008d693 <rtc_pads_slpsel+75>:	l32r	a9, 0x400888dc
   0x4008d696 <rtc_pads_slpsel+78>:	memw
   0x4008d699 <rtc_pads_slpsel+81>:	l32i.n	a11, a8, 0
   0x4008d69b <rtc_pads_slpsel+83>:	extui	a10, a3, 0, 1
   0x4008d69e <rtc_pads_slpsel+86>:	slli	a10, a10, 11
   0x4008d6a1 <rtc_pads_slpsel+89>:	and	a9, a11, a9
   0x4008d6a4 <rtc_pads_slpsel+92>:	or	a9, a10, a9
   0x4008d6a7 <rtc_pads_slpsel+95>:	memw
   0x4008d6aa <rtc_pads_slpsel+98>:	s32i	a9, a8, 0
   0x4008d6ad <rtc_pads_slpsel+101>:	bbci	a2, 3, 0x4008d6cd <rtc_pads_slpsel+133>
   0x4008d6b0 <rtc_pads_slpsel+104>:	l32r	a8, 0x4008c9b4
......
......

typedef enum {
    RTC_GPIO0 = BIT(0),
    RTC_GPIO1 = BIT(1),
    ......
    ......
    RTC_GPIO17 = BIT(17)
} rtc_gpio_num_t;

/*
 * sel == 1, put the pad in sleep mode
 */
void rtc_pads_slpsel(rtc_gpio_num_t rtc_gpio_num, uint8_t sel);

5.3.4 rtc_pads_slpie

   0x4008da1c <rtc_pads_slpie>:	entry	a1, 32
   0x4008da1f <rtc_pads_slpie+3>:	bbci	a2, 6, 0x4008da40 <rtc_pads_slpie+36>
   0x4008da22 <rtc_pads_slpie+6>:	l32r	a8, 0x4008bfa4
   0x4008da25 <rtc_pads_slpie+9>:	l32r	a9, 0x4008da18
   0x4008da28 <rtc_pads_slpie+12>:	memw
   0x4008da2b <rtc_pads_slpie+15>:	l32i	a11, a8, 0
   0x4008da2e <rtc_pads_slpie+18>:	extui	a10, a3, 0, 1
   0x4008da31 <rtc_pads_slpie+21>:	slli	a10, a10, 13
   0x4008da34 <rtc_pads_slpie+24>:	and	a9, a11, a9
   0x4008da37 <rtc_pads_slpie+27>:	or	a9, a10, a9
   0x4008da3a <rtc_pads_slpie+30>:	memw
   0x4008da3d <rtc_pads_slpie+33>:	s32i	a9, a8, 0
   0x4008da40 <rtc_pads_slpie+36>:	bbci	a2, 7, 0x4008da61 <rtc_pads_slpie+69>
   0x4008da43 <rtc_pads_slpie+39>:	l32r	a8, 0x4008bfb0
   0x4008da46 <rtc_pads_slpie+42>:	l32r	a9, 0x4008da18
   0x4008da49 <rtc_pads_slpie+45>:	memw
   0x4008da4c <rtc_pads_slpie+48>:	l32i	a11, a8, 0
   0x4008da4f <rtc_pads_slpie+51>:	extui	a10, a3, 0, 1
   0x4008da52 <rtc_pads_slpie+54>:	slli	a10, a10, 13
   0x4008da55 <rtc_pads_slpie+57>:	and	a9, a11, a9
   0x4008da58 <rtc_pads_slpie+60>:	or	a9, a10, a9
   0x4008da5b <rtc_pads_slpie+63>:	memw
   0x4008da5e <rtc_pads_slpie+66>:	s32i	a9, a8, 0
   0x4008da61 <rtc_pads_slpie+69>:	bbci	a2, 8, 0x4008da81 <rtc_pads_slpie+101>
   0x4008da64 <rtc_pads_slpie+72>:	l32r	a8, 0x4008c9bc
   0x4008da67 <rtc_pads_slpie+75>:	l32r	a9, 0x4008da18
   0x4008da6a <rtc_pads_slpie+78>:	memw
   0x4008da6d <rtc_pads_slpie+81>:	l32i.n	a11, a8, 0
   0x4008da6f <rtc_pads_slpie+83>:	extui	a10, a3, 0, 1
   0x4008da72 <rtc_pads_slpie+86>:	slli	a10, a10, 13
   0x4008da75 <rtc_pads_slpie+89>:	and	a9, a11, a9
   0x4008da78 <rtc_pads_slpie+92>:	or	a9, a10, a9
   0x4008da7b <rtc_pads_slpie+95>:	memw
   0x4008da7e <rtc_pads_slpie+98>:	s32i	a9, a8, 0
   0x4008da81 <rtc_pads_slpie+101>:	bbci	a2, 9, 0x4008daa1 <rtc_pads_slpie+133>
   0x4008da84 <rtc_pads_slpie+104>:	l32r	a8, 0x4008c9bc
......
......

typedef enum {
    RTC_GPIO0 = BIT(0),
    RTC_GPIO1 = BIT(1),
    ......
    ......
    RTC_GPIO17 = BIT(17)
} rtc_gpio_num_t;

/*
 * sel == 1, put the pad in sleep mode
 *
 * Only valide for RTC_GPIO6 - RTC_GPIO17
 */
void rtc_pads_slpie(rtc_gpio_num_t rtc_gpio_num, uint8_t enable);

5.3.5 rtc_pads_funie

Input enable of the pad.

   0x4008dba4 <rtc_pads_funie>:	entry	a1, 32
   0x4008dba7 <rtc_pads_funie+3>:	bbci	a2, 6, 0x4008dbc8 <rtc_pads_funie+36>
   0x4008dbaa <rtc_pads_funie+6>:	l32r	a8, 0x4008bfa4
   0x4008dbad <rtc_pads_funie+9>:	l32r	a9, 0x400888dc
   0x4008dbb0 <rtc_pads_funie+12>:	memw
   0x4008dbb3 <rtc_pads_funie+15>:	l32i	a11, a8, 0
   0x4008dbb6 <rtc_pads_funie+18>:	extui	a10, a3, 0, 1
   0x4008dbb9 <rtc_pads_funie+21>:	slli	a10, a10, 11
   0x4008dbbc <rtc_pads_funie+24>:	and	a9, a11, a9
   0x4008dbbf <rtc_pads_funie+27>:	or	a9, a10, a9
   0x4008dbc2 <rtc_pads_funie+30>:	memw
   0x4008dbc5 <rtc_pads_funie+33>:	s32i	a9, a8, 0
   0x4008dbc8 <rtc_pads_funie+36>:	bbci	a2, 7, 0x4008dbe9 <rtc_pads_funie+69>
   0x4008dbcb <rtc_pads_funie+39>:	l32r	a8, 0x4008bfb0
   0x4008dbce <rtc_pads_funie+42>:	l32r	a9, 0x400888dc
   0x4008dbd1 <rtc_pads_funie+45>:	memw
   0x4008dbd4 <rtc_pads_funie+48>:	l32i	a11, a8, 0
   0x4008dbd7 <rtc_pads_funie+51>:	extui	a10, a3, 0, 1
   0x4008dbda <rtc_pads_funie+54>:	slli	a10, a10, 11
   0x4008dbdd <rtc_pads_funie+57>:	and	a9, a11, a9
   0x4008dbe0 <rtc_pads_funie+60>:	or	a9, a10, a9
   0x4008dbe3 <rtc_pads_funie+63>:	memw
   0x4008dbe6 <rtc_pads_funie+66>:	s32i	a9, a8, 0
   0x4008dbe9 <rtc_pads_funie+69>:	bbci	a2, 8, 0x4008dc09 <rtc_pads_funie+101>
   0x4008dbec <rtc_pads_funie+72>:	l32r	a8, 0x4008c9bc
......
......

typedef enum {
    RTC_GPIO0 = BIT(0),
    RTC_GPIO1 = BIT(1),
    ......
    ......
    RTC_GPIO17 = BIT(17)
} rtc_gpio_num_t;

/*
 * enable == 1, input enable
 * enable == 0, input disable
 *
 * Only the RTC_GPIO6 - RTC_GPIO17 are valide
 */
void rtc_pads_funie (rtc_gpio_num_t rtc_gpio_num, uint8_t enable);

5.3.6 rtc_pads_slpoe

Output enable of the pad.

   0x4008d890 <rtc_pads_slpoe>:	entry	a1, 32
   0x4008d893 <rtc_pads_slpoe+3>:	bbci	a2, 6, 0x4008d8b4 <rtc_pads_slpoe+36>
   0x4008d896 <rtc_pads_slpoe+6>:	l32r	a8, 0x4008bfa4
   0x4008d899 <rtc_pads_slpoe+9>:	l32r	a9, 0x40087114
   0x4008d89c <rtc_pads_slpoe+12>:	memw
   0x4008d89f <rtc_pads_slpoe+15>:	l32i	a11, a8, 0
   0x4008d8a2 <rtc_pads_slpoe+18>:	extui	a10, a3, 0, 1
   0x4008d8a5 <rtc_pads_slpoe+21>:	slli	a10, a10, 12
   0x4008d8a8 <rtc_pads_slpoe+24>:	and	a9, a11, a9
   0x4008d8ab <rtc_pads_slpoe+27>:	or	a9, a10, a9
   0x4008d8ae <rtc_pads_slpoe+30>:	memw
   0x4008d8b1 <rtc_pads_slpoe+33>:	s32i	a9, a8, 0
   0x4008d8b4 <rtc_pads_slpoe+36>:	bbci	a2, 7, 0x4008d8d5 <rtc_pads_slpoe+69>
   0x4008d8b7 <rtc_pads_slpoe+39>:	l32r	a8, 0x4008bfb0
   0x4008d8ba <rtc_pads_slpoe+42>:	l32r	a9, 0x40087114
   0x4008d8bd <rtc_pads_slpoe+45>:	memw
   0x4008d8c0 <rtc_pads_slpoe+48>:	l32i	a11, a8, 0
   0x4008d8c3 <rtc_pads_slpoe+51>:	extui	a10, a3, 0, 1
   0x4008d8c6 <rtc_pads_slpoe+54>:	slli	a10, a10, 12
   0x4008d8c9 <rtc_pads_slpoe+57>:	and	a9, a11, a9
   0x4008d8cc <rtc_pads_slpoe+60>:	or	a9, a10, a9
   0x4008d8cf <rtc_pads_slpoe+63>:	memw
   0x4008d8d2 <rtc_pads_slpoe+66>:	s32i	a9, a8, 0
   0x4008d8d5 <rtc_pads_slpoe+69>:	bbci	a2, 8, 0x4008d8f5 <rtc_pads_slpoe+101>
   0x4008d8d8 <rtc_pads_slpoe+72>:	l32r	a8, 0x4008c9bc
......
......

typedef enum {
    RTC_GPIO0 = BIT(0),
    RTC_GPIO1 = BIT(1),
    ......
    ......
    RTC_GPIO17 = BIT(17)
} rtc_gpio_num_t;

/*
 * enable == 1, Output enable
 * enable == 0, Output disable
 * Only RTC_GPIO6 - RTC_GPIO17 are valide
 */
void rtc_pads_slpoe(rtc_gpio_num_t rtc_gpio_num, uint8_t enable);

5.3.7 rtc_pads_hold

   0x4008e03c <rtc_pads_hold>:	entry	a1, 32
   0x4008e03f <rtc_pads_hold+3>:	bbci	a2, 6, 0x4008e060 <rtc_pads_hold+36>
   0x4008e042 <rtc_pads_hold+6>:	l32r	a8, 0x4008bfa4
   0x4008e045 <rtc_pads_hold+9>:	l32r	a9, 0x4008620c
   0x4008e048 <rtc_pads_hold+12>:	memw
   0x4008e04b <rtc_pads_hold+15>:	l32i	a11, a8, 0
   0x4008e04e <rtc_pads_hold+18>:	extui	a10, a3, 0, 1
   0x4008e051 <rtc_pads_hold+21>:	slli	a10, a10, 29
   0x4008e054 <rtc_pads_hold+24>:	and	a9, a11, a9
   0x4008e057 <rtc_pads_hold+27>:	or	a9, a10, a9
   0x4008e05a <rtc_pads_hold+30>:	memw
   0x4008e05d <rtc_pads_hold+33>:	s32i	a9, a8, 0
   0x4008e060 <rtc_pads_hold+36>:	bbci	a2, 7, 0x4008e081 <rtc_pads_hold+69>
   0x4008e063 <rtc_pads_hold+39>:	l32r	a8, 0x4008bfb0
   0x4008e066 <rtc_pads_hold+42>:	l32r	a9, 0x4008620c
   0x4008e069 <rtc_pads_hold+45>:	memw
   0x4008e06c <rtc_pads_hold+48>:	l32i	a11, a8, 0
   0x4008e06f <rtc_pads_hold+51>:	extui	a10, a3, 0, 1
   0x4008e072 <rtc_pads_hold+54>:	slli	a10, a10, 29
   0x4008e075 <rtc_pads_hold+57>:	and	a9, a11, a9
   0x4008e078 <rtc_pads_hold+60>:	or	a9, a10, a9
   0x4008e07b <rtc_pads_hold+63>:	memw
   0x4008e07e <rtc_pads_hold+66>:	s32i	a9, a8, 0
   0x4008e081 <rtc_pads_hold+69>:	bbci	a2, 8, 0x4008e0a1 <rtc_pads_hold+101>
   0x4008e084 <rtc_pads_hold+72>:	l32r	a8, 0x4008c9bc
   0x4008e087 <rtc_pads_hold+75>:	l32r	a9, 0x4008620c
......
......

typedef enum {
    RTC_GPIO0 = BIT(0),
    RTC_GPIO1 = BIT(1),
    ......
    ......
    RTC_GPIO17 = BIT(17)
} rtc_gpio_num_t;

/*
 * hold == 1, Hold output value
 * hold == 0, normal operation
 * Only RTC_GPIO6 - RTC_GPIO17 are valide
 */
void rtc_pads_hold(rtc_gpio_num_t rtc_gpio_num, uint8_t hold);

5.3.8 rtc_pads_pu

   0x4008dd2c <rtc_pads_pu>:	entry	a1, 32
   0x4008dd2f <rtc_pads_pu+3>:	bbci	a2, 6, 0x4008dd50 <rtc_pads_pu+36>
   0x4008dd32 <rtc_pads_pu+6>:	l32r	a8, 0x4008bfa4
   0x4008dd35 <rtc_pads_pu+9>:	l32r	a9, 0x40084bc0
   0x4008dd38 <rtc_pads_pu+12>:	memw
   0x4008dd3b <rtc_pads_pu+15>:	l32i	a11, a8, 0
   0x4008dd3e <rtc_pads_pu+18>:	extui	a10, a3, 0, 1
   0x4008dd41 <rtc_pads_pu+21>:	slli	a10, a10, 27
   0x4008dd44 <rtc_pads_pu+24>:	and	a9, a11, a9
   0x4008dd47 <rtc_pads_pu+27>:	or	a9, a10, a9
   0x4008dd4a <rtc_pads_pu+30>:	memw
   0x4008dd4d <rtc_pads_pu+33>:	s32i	a9, a8, 0
   0x4008dd50 <rtc_pads_pu+36>:	bbci	a2, 7, 0x4008dd71 <rtc_pads_pu+69>
   0x4008dd53 <rtc_pads_pu+39>:	l32r	a8, 0x4008bfb0
   0x4008dd56 <rtc_pads_pu+42>:	l32r	a9, 0x40084bc0
   0x4008dd59 <rtc_pads_pu+45>:	memw
   0x4008dd5c <rtc_pads_pu+48>:	l32i	a11, a8, 0
   0x4008dd5f <rtc_pads_pu+51>:	extui	a10, a3, 0, 1
   0x4008dd62 <rtc_pads_pu+54>:	slli	a10, a10, 27
   0x4008dd65 <rtc_pads_pu+57>:	and	a9, a11, a9
   0x4008dd68 <rtc_pads_pu+60>:	or	a9, a10, a9
   0x4008dd6b <rtc_pads_pu+63>:	memw
   0x4008dd6e <rtc_pads_pu+66>:	s32i	a9, a8, 0
   0x4008dd71 <rtc_pads_pu+69>:	bbci	a2, 8, 0x4008dd91 <rtc_pads_pu+101>
   0x4008dd74 <rtc_pads_pu+72>:	l32r	a8, 0x4008c9bc
   0x4008dd77 <rtc_pads_pu+75>:	l32r	a9, 0x40084bc0
......
......

typedef enum {
    RTC_GPIO0 = BIT(0),
    RTC_GPIO1 = BIT(1),
    ......
    ......
    RTC_GPIO17 = BIT(17)
} rtc_gpio_num_t;

/*
 * pu == 1, pull-up enable
 * pu == 0, pull-up disable
 * Only RTC_GPIO6 - RTC_GPIO17 are valide
 */
void rtc_pads_pu(rtc_gpio_num_t rtc_gpio_num, uint8_t pu);

5.3.9 rtc_pads_pd

   0x4008deb4 <rtc_pads_pd>:	entry	a1, 32
   0x4008deb7 <rtc_pads_pd+3>:	bbci	a2, 6, 0x4008ded8 <rtc_pads_pd+36>
   0x4008deba <rtc_pads_pd+6>:	l32r	a8, 0x4008bfa4
   0x4008debd <rtc_pads_pd+9>:	l32r	a9, 0x40087110
   0x4008dec0 <rtc_pads_pd+12>:	memw
   0x4008dec3 <rtc_pads_pd+15>:	l32i	a11, a8, 0
   0x4008dec6 <rtc_pads_pd+18>:	extui	a10, a3, 0, 1
   0x4008dec9 <rtc_pads_pd+21>:	slli	a10, a10, 28
   0x4008decc <rtc_pads_pd+24>:	and	a9, a11, a9
   0x4008decf <rtc_pads_pd+27>:	or	a9, a10, a9
   0x4008ded2 <rtc_pads_pd+30>:	memw
   0x4008ded5 <rtc_pads_pd+33>:	s32i	a9, a8, 0
   0x4008ded8 <rtc_pads_pd+36>:	bbci	a2, 7, 0x4008def9 <rtc_pads_pd+69>
   0x4008dedb <rtc_pads_pd+39>:	l32r	a8, 0x4008bfb0
   0x4008dede <rtc_pads_pd+42>:	l32r	a9, 0x40087110
   0x4008dee1 <rtc_pads_pd+45>:	memw
   0x4008dee4 <rtc_pads_pd+48>:	l32i	a11, a8, 0
   0x4008dee7 <rtc_pads_pd+51>:	extui	a10, a3, 0, 1
   0x4008deea <rtc_pads_pd+54>:	slli	a10, a10, 28
   0x4008deed <rtc_pads_pd+57>:	and	a9, a11, a9
   0x4008def0 <rtc_pads_pd+60>:	or	a9, a10, a9
   0x4008def3 <rtc_pads_pd+63>:	memw
   0x4008def6 <rtc_pads_pd+66>:	s32i	a9, a8, 0
   0x4008def9 <rtc_pads_pd+69>:	bbci	a2, 8, 0x4008df19 <rtc_pads_pd+101>
   0x4008defc <rtc_pads_pd+72>:	l32r	a8, 0x4008c9bc
   0x4008deff <rtc_pads_pd+75>:	l32r	a9, 0x40087110
......
......

typedef enum {
    RTC_GPIO0 = BIT(0),
    RTC_GPIO1 = BIT(1),
    ......
    ......
    RTC_GPIO17 = BIT(17)
} rtc_gpio_num_t;

/*
 * pd == 1, pull-down enable
 * pd == 0, pull-down disable
 * Only RTC_GPIO6 - RTC_GPIO17 are valide
 */
void rtc_pads_pd(rtc_gpio_num_t rtc_gpio_num, uint8_t pd);

5.3.10 rtc_set_wakeup_opt

0x4008ff8c <rtc_set_wakeup_opt>:	entry	a1, 32
0x4008ff8f <rtc_set_wakeup_opt+3>: l32r	a8, 0x4008ff84      <-- load the address of RTC_CNTL_WAKEUP_STATE_REG
0x4008ff92 <rtc_set_wakeup_opt+6>: l32r	a11, 0x4008d188     <-- a11 = 0xffc007ff
0x4008ff95 <rtc_set_wakeup_opt+9>: memw
0x4008ff98 <rtc_set_wakeup_opt+12>: l32i.n	a9, a8, 0       <-- Read the RTC_CNTL_WAKEUP_STATE_REG
0x4008ff9a <rtc_set_wakeup_opt+14>: extui	a2, a2, 0, 11   <-- Extract the low 11 bits of 1st parameter
0x4008ff9d <rtc_set_wakeup_opt+17>: slli	a10, a2, 11     <-- Shift left 11
0x4008ffa0 <rtc_set_wakeup_opt+20>: and	a9, a9, a11     <-- RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff (only bitpos:[21:11])
0x4008ffa3 <rtc_set_wakeup_opt+23>: or	a9, a10, a9     <-- (RTC_CNTL_WAKEUP_STATE_REG & 0xffc007ff) | wakeup_opt
0x4008ffa6 <rtc_set_wakeup_opt+26>: memw
0x4008ffa9 <rtc_set_wakeup_opt+29>: s32i.n	a9, a8, 0   <-- Write to RTC_CNTL_WAKEUP_STATE_REG
0x4008ffab <rtc_set_wakeup_opt+31>: l32r   a8, 0x4008ff88  <--- load the address of RTC_CNTL_SLP_REJECT_CONF_REG
0x4008ffae <rtc_set_wakeup_opt+34>: memw
0x4008ffb1 <rtc_set_wakeup_opt+37>: s32i.n a3, a8, 0   <-- store the 2nd parameter into RTC_CNTL_SLP_REJECT_CONF_REG directly
0x4008ffb3 <rtc_set_wakeup_opt+39>: retw.n
(gdb) x /1x 0x4008ff84
0x4008ff84:	0x3ff48038
(gdb) x /1x 0x4008d188
0x4008d188:	0xffc007ff
(gdb) x /1x 0x4008ff88
0x4008ff88:	0x3ff48064


#define DR_REG_RTCCNTL_BASE                     0x3ff48000
#define RTC_CNTL_SLP_REJECT_CONF_REG     (DR_REG_RTCCNTL_BASE + 0x64)
#define RTC_CNTL_WAKEUP_STATE_REG    (DR_REG_RTCCNTL_BASE + 0x38)

/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */
/*description: enable filter for gpio wakeup event*/
#define RTC_CNTL_GPIO_WAKEUP_FILTER  (BIT(22))
#define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(22))
#define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
#define RTC_CNTL_GPIO_WAKEUP_FILTER_S  22
/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */
/*description: wakeup enable bitmap*/
#define RTC_CNTL_WAKEUP_ENA  0x000007FF
#define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
#define RTC_CNTL_WAKEUP_ENA_V  0x7FF
#define RTC_CNTL_WAKEUP_ENA_S  11
/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */
/*description: wakeup cause*/
#define RTC_CNTL_WAKEUP_CAUSE  0x000007FF
#define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
#define RTC_CNTL_WAKEUP_CAUSE_V  0x7FF
#define RTC_CNTL_WAKEUP_CAUSE_S  0

>>> So the rtc_set_wakeup_opt should be:

 void rtc_set_wakeup_opt(uint32_t wakeup_opt, uint32_t sleep_reject_conf);

5.3.11 rtc_pad_ext_wakeup

   0x4008ee9c <rtc_pad_ext_wakeup>:	entry	a1, 32
   0x4008ee9f <rtc_pad_ext_wakeup+3>:	mov.n	a10, a2
   0x4008eea1 <rtc_pad_ext_wakeup+5>:	movi.n	a11, 1
   0x4008eea3 <rtc_pad_ext_wakeup+7>:	call8	0x4008d2f4 <rtc_pads_muxsel>
   0x4008eea6 <rtc_pad_ext_wakeup+10>:	mov.n	a10, a2
   0x4008eea8 <rtc_pad_ext_wakeup+12>:	movi.n	a11, 0
   0x4008eeaa <rtc_pad_ext_wakeup+14>:	call8	0x4008d54c <rtc_pads_funsel>
   0x4008eead <rtc_pad_ext_wakeup+17>:	l32r	a8, 0x4008edf4
   0x4008eeb0 <rtc_pad_ext_wakeup+20>:	slli	a9, a2, 14
   0x4008eeb3 <rtc_pad_ext_wakeup+23>:	memw
   0x4008eeb6 <rtc_pad_ext_wakeup+26>:	l32i.n	a10, a8, 0
   0x4008eeb8 <rtc_pad_ext_wakeup+28>:	movi.n	a11, -1
   0x4008eeba <rtc_pad_ext_wakeup+30>:	xor	a9, a11, a9
   0x4008eebd <rtc_pad_ext_wakeup+33>:	and	a9, a9, a10
   0x4008eec0 <rtc_pad_ext_wakeup+36>:	memw
   0x4008eec3 <rtc_pad_ext_wakeup+39>:	s32i.n	a9, a8, 0
   0x4008eec5 <rtc_pad_ext_wakeup+41>:	mov.n	a10, a2
   0x4008eec7 <rtc_pad_ext_wakeup+43>:	movi	a11, 1
   0x4008eeca <rtc_pad_ext_wakeup+46>:	call8	0x4008d794 <rtc_pads_slpsel>
   0x4008eecd <rtc_pad_ext_wakeup+49>:	mov.n	a10, a2
   0x4008eecf <rtc_pad_ext_wakeup+51>:	movi	a11, 0
   0x4008eed2 <rtc_pad_ext_wakeup+54>:	call8	0x4008d9dc <rtc_pads_slpoe>
   0x4008eed5 <rtc_pad_ext_wakeup+57>:	mov.n	a10, a2
   0x4008eed7 <rtc_pad_ext_wakeup+59>:	movi	a11, 1
   0x4008eeda <rtc_pad_ext_wakeup+62>:	call8	0x4008db68 <rtc_pads_slpie>
   0x4008eedd <rtc_pad_ext_wakeup+65>:	mov.n	a10, a2
   0x4008eedf <rtc_pad_ext_wakeup+67>:	movi	a11, 1
   0x4008eee2 <rtc_pad_ext_wakeup+70>:	call8	0x4008dcf0 <rtc_pads_funie>
   0x4008eee5 <rtc_pad_ext_wakeup+73>:	mov.n	a10, a2
   0x4008eee7 <rtc_pad_ext_wakeup+75>:	movi	a11, 0
   0x4008eeea <rtc_pad_ext_wakeup+78>:	call8	0x4008de78 <rtc_pads_pu>
   0x4008eeed <rtc_pad_ext_wakeup+81>:	mov.n	a10, a2
   0x4008eeef <rtc_pad_ext_wakeup+83>:	movi.n	a11, 0
   0x4008eef1 <rtc_pad_ext_wakeup+85>:	call8	0x4008e000 <rtc_pads_pd>
   0x4008eef4 <rtc_pad_ext_wakeup+88>:	l32r	a8, 0x4008ee90
   0x4008eef7 <rtc_pad_ext_wakeup+91>:	l32r	a2, 0x4008ee94
   0x4008eefa <rtc_pad_ext_wakeup+94>:	memw
   0x4008eefd <rtc_pad_ext_wakeup+97>:	l32i.n	a9, a8, 0
   0x4008eeff <rtc_pad_ext_wakeup+99>:	slli	a3, a3, 27
   0x4008ef02 <rtc_pad_ext_wakeup+102>:	and	a9, a9, a2
   0x4008ef05 <rtc_pad_ext_wakeup+105>:	or	a3, a3, a9
   0x4008ef08 <rtc_pad_ext_wakeup+108>:	l32r	a2, 0x4008ee98
   0x4008ef0b <rtc_pad_ext_wakeup+111>:	memw
   0x4008ef0e <rtc_pad_ext_wakeup+114>:	s32i.n	a3, a8, 0
   0x4008ef10 <rtc_pad_ext_wakeup+116>:	memw
   0x4008ef13 <rtc_pad_ext_wakeup+119>:	l32i.n	a8, a2, 0
   0x4008ef15 <rtc_pad_ext_wakeup+121>:	l32r	a3, 0x4008838c
   0x4008ef18 <rtc_pad_ext_wakeup+124>:	extui	a4, a4, 0, 1
   0x4008ef1b <rtc_pad_ext_wakeup+127>:	slli	a4, a4, 30
   0x4008ef1e <rtc_pad_ext_wakeup+130>:	and	a3, a8, a3
   0x4008ef21 <rtc_pad_ext_wakeup+133>:	or	a4, a4, a3
   0x4008ef24 <rtc_pad_ext_wakeup+136>:	memw
   0x4008ef27 <rtc_pad_ext_wakeup+139>:	s32i.n	a4, a2, 0
   0x4008ef29 <rtc_pad_ext_wakeup+141>:	retw.n

6 Wakeup

6.1 Timer Expire Wakeup

void esp_deep_sleep(uint64_t time_in_us)
{
    rtc_set_cpu_freq(CPU_XTAL);
    if (esp_get_deep_sleep_wake_stub() == NULL) {
        esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
    }
    uint32_t period = rtc_slowck_cali(CALI_RTC_MUX, 128);
    uint32_t cycle_l, cycle_h;
    rtc_usec2rtc(time_in_us >> 32, time_in_us, period, &cycle_h, &cycle_l);
    rtc_slp_prep_lite(1, 0);
    rtc_sleep(cycle_h, cycle_l, TIMER_EXPIRE_EN, 0);
    while (1) {
        ;
    }
}

6.2 External Wakeup

#define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x5c)
/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: enable control XTAL by external pads*/
#define RTC_CNTL_XTL_EXT_CTR_EN  (BIT(31))
#define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
#define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
#define RTC_CNTL_XTL_EXT_CTR_EN_S  31
/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: 0: power down XTAL at high level  1: power down XTAL at low level*/
#define RTC_CNTL_XTL_EXT_CTR_LV  (BIT(30))
#define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
#define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
#define RTC_CNTL_XTL_EXT_CTR_LV_S  30

#define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x60)
/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: 0: external wakeup at low level  1: external wakeup at high level*/
#define RTC_CNTL_EXT_WAKEUP1_LV  (BIT(31))
#define RTC_CNTL_EXT_WAKEUP1_LV_M  (BIT(31))
#define RTC_CNTL_EXT_WAKEUP1_LV_V  0x1
#define RTC_CNTL_EXT_WAKEUP1_LV_S  31
/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: 0: external wakeup at low level  1: external wakeup at high level*/
#define RTC_CNTL_EXT_WAKEUP0_LV  (BIT(30))
#define RTC_CNTL_EXT_WAKEUP0_LV_M  (BIT(30))
#define RTC_CNTL_EXT_WAKEUP0_LV_V  0x1
#define RTC_CNTL_EXT_WAKEUP0_LV_S  30

#define RTC_CNTL_EXT_WAKEUP1_REG          (DR_REG_RTCCNTL_BASE + 0xcc)
/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */
/*description: clear ext wakeup1 status*/
#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR  (BIT(18))
#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M  (BIT(18))
#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V  0x1
#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S  18
/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */
/*description: Bitmap to select RTC pads for ext wakeup1*/
#define RTC_CNTL_EXT_WAKEUP1_SEL  0x0003FFFF
#define RTC_CNTL_EXT_WAKEUP1_SEL_M  ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S))
#define RTC_CNTL_EXT_WAKEUP1_SEL_V  0x3FFFF
#define RTC_CNTL_EXT_WAKEUP1_SEL_S  0

#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG          (DR_REG_RTCCNTL_BASE + 0xd0)
/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */
/*description: ext wakeup1 status*/
#define RTC_CNTL_EXT_WAKEUP1_STATUS  0x0003FFFF
#define RTC_CNTL_EXT_WAKEUP1_STATUS_M  ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S))
#define RTC_CNTL_EXT_WAKEUP1_STATUS_V  0x3FFFF
#define RTC_CNTL_EXT_WAKEUP1_STATUS_S  0

#define RTC_IO_EXT_WAKEUP0_REG          (DR_REG_RTCIO_BASE + 0xbc)
/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/
#define RTC_IO_EXT_WAKEUP0_SEL  0x0000001F
#define RTC_IO_EXT_WAKEUP0_SEL_M  ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S))
#define RTC_IO_EXT_WAKEUP0_SEL_V  0x1F
#define RTC_IO_EXT_WAKEUP0_SEL_S  27

#define RTC_IO_XTL_EXT_CTR_REG          (DR_REG_RTCIO_BASE + 0xc0)
/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select
 GPIO2 ...Ò17Ó select GPIO17*/
#define RTC_IO_XTL_EXT_CTR_SEL  0x0000001F
#define RTC_IO_XTL_EXT_CTR_SEL_M  ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S))
#define RTC_IO_XTL_EXT_CTR_SEL_V  0x1F
#define RTC_IO_XTL_EXT_CTR_SEL_S  27

• 0x3ff484c0 = 0x0
• 0x3ff484bc = 0x0
• 0x3ff480d0 = 0x0
• 0x3ff480cc = 0x0
• 0x3ff4805c = 0x0
• 0x3ff48060 = 0x0

7 RTC CMD Inst

7.1 rtc_cmd_wr_reg

   0x4008f378 <rtc_cmd_wr_reg>:	entry	a1, 32
   0x4008f37b <rtc_cmd_wr_reg+3>:	l32r	a9, 0x40085078
   0x4008f37e <rtc_cmd_wr_reg+6>:	extui	a5, a5, 0, 8
   0x4008f381 <rtc_cmd_wr_reg+9>:	slli	a8, a5, 10
   0x4008f384 <rtc_cmd_wr_reg+12>:	extui	a4, a4, 0, 5
   0x4008f387 <rtc_cmd_wr_reg+15>:	or	a8, a8, a9
   0x4008f38a <rtc_cmd_wr_reg+18>:	slli	a9, a4, 18
   0x4008f38d <rtc_cmd_wr_reg+21>:	or	a8, a8, a9
   0x4008f390 <rtc_cmd_wr_reg+24>:	extui	a3, a3, 0, 5
   0x4008f393 <rtc_cmd_wr_reg+27>:	extui	a2, a2, 0, 10
   0x4008f396 <rtc_cmd_wr_reg+30>:	or	a2, a8, a2
   0x4008f399 <rtc_cmd_wr_reg+33>:	slli	a4, a3, 23
   0x4008f39c <rtc_cmd_wr_reg+36>:	or	a2, a2, a4
   0x4008f39f <rtc_cmd_wr_reg+39>:	retw.n
   0x4008f3a1:	ill
(gdb) x /1x 0x40085078
0x40085078:	0x10000000

7.2 rtc_cmd_rd_reg

   0x4008f3a4 <rtc_cmd_rd_reg>:	entry	a1, 32
   0x4008f3a7 <rtc_cmd_rd_reg+3>:	l32r	a9, 0x4008043c
   0x4008f3aa <rtc_cmd_rd_reg+6>:	extui	a4, a4, 0, 5
   0x4008f3ad <rtc_cmd_rd_reg+9>:	slli	a8, a4, 18
   0x4008f3b0 <rtc_cmd_rd_reg+12>:	or	a8, a8, a9
   0x4008f3b3 <rtc_cmd_rd_reg+15>:	extui	a3, a3, 0, 5
   0x4008f3b6 <rtc_cmd_rd_reg+18>:	extui	a2, a2, 0, 10
   0x4008f3b9 <rtc_cmd_rd_reg+21>:	or	a2, a8, a2
   0x4008f3bc <rtc_cmd_rd_reg+24>:	slli	a9, a3, 23
   0x4008f3bf <rtc_cmd_rd_reg+27>:	or	a2, a2, a9
   0x4008f3c2 <rtc_cmd_rd_reg+30>:	retw.n
   0x4008f3c4:	ill
(gdb) x /1x 0x4008043c
0x4008043c:	0x20000000

7.3 rtc_cmd_wr_i2c

   0x4008f3c8 <rtc_cmd_wr_i2c>:	entry	a1, 32
   0x4008f3cb <rtc_cmd_wr_i2c+3>:	l32r	a8, 0x4008f3c4
   0x4008f3ce <rtc_cmd_wr_i2c+6>:	slli	a7, a7, 8
   0x4008f3d1 <rtc_cmd_wr_i2c+9>:	or	a4, a4, a8
   0x4008f3d4 <rtc_cmd_wr_i2c+12>:	or	a7, a4, a7
   0x4008f3d7 <rtc_cmd_wr_i2c+15>:	slli	a6, a6, 16
   0x4008f3da <rtc_cmd_wr_i2c+18>:	or	a7, a7, a6
   0x4008f3dd <rtc_cmd_wr_i2c+21>:	slli	a5, a5, 19
   0x4008f3e0 <rtc_cmd_wr_i2c+24>:	or	a7, a7, a5
   0x4008f3e3 <rtc_cmd_wr_i2c+27>:	slli	a3, a3, 22
   0x4008f3e6 <rtc_cmd_wr_i2c+30>:	or	a7, a7, a3
   0x4008f3e9 <rtc_cmd_wr_i2c+33>:	slli	a2, a2, 27
   0x4008f3ec <rtc_cmd_wr_i2c+36>:	or	a2, a7, a2
   0x4008f3ef <rtc_cmd_wr_i2c+39>:	retw.n
   0x4008f3f1:	ill
(gdb) x /1x 0x4008f3c4
0x4008f3c4:	0x30000000

7.4 rtc_cmd_wait_delay

   0x4008f3f4 <rtc_cmd_wait_delay>:	entry	a1, 32
   0x4008f3f7 <rtc_cmd_wait_delay+3>:	l32r	a8, 0x400805a0
   0x4008f3fa <rtc_cmd_wait_delay+6>:	extui	a2, a2, 0, 16
   0x4008f3fd <rtc_cmd_wait_delay+9>:	or	a2, a2, a8
   0x4008f400 <rtc_cmd_wait_delay+12>:	retw.n
   0x4008f402:	ill
(gdb) x /1x 0x400805a0
0x400805a0:	0x40000000

7.5 rtc_cmd_meas_tsens

   0x4008f408 <rtc_cmd_meas_tsens>:	entry	a1, 32
   0x4008f40b <rtc_cmd_meas_tsens+3>:	l32r	a8, 0x4008f404
   0x4008f40e <rtc_cmd_meas_tsens+6>:	slli	a2, a2, 16
   0x4008f411 <rtc_cmd_meas_tsens+9>:	or	a3, a3, a8
   0x4008f414 <rtc_cmd_meas_tsens+12>:	or	a2, a3, a2
   0x4008f417 <rtc_cmd_meas_tsens+15>:	retw.n
   0x4008f419:	ill
(gdb) x /1x 0x4008f404
0x4008f404:	0xa0000000

7.6 rtc_cmd_meas_saradc

   0x4008f420 <rtc_cmd_meas_saradc>:	entry	a1, 32
   0x4008f423 <rtc_cmd_meas_saradc+3>:	l32r	a8, 0x4008f41c
   0x4008f426 <rtc_cmd_meas_saradc+6>:	extui	a4, a4, 0, 4
   0x4008f429 <rtc_cmd_meas_saradc+9>:	extui	a5, a5, 0, 2
   0x4008f42c <rtc_cmd_meas_saradc+12>:	or	a5, a5, a8
   0x4008f42f <rtc_cmd_meas_saradc+15>:	extui	a3, a3, 0, 2
   0x4008f432 <rtc_cmd_meas_saradc+18>:	slli	a8, a4, 2
   0x4008f435 <rtc_cmd_meas_saradc+21>:	or	a5, a5, a8
   0x4008f438 <rtc_cmd_meas_saradc+24>:	slli	a3, a3, 6
   0x4008f43b <rtc_cmd_meas_saradc+27>:	extui	a2, a2, 0, 16
   0x4008f43e <rtc_cmd_meas_saradc+30>:	or	a5, a5, a3
   0x4008f441 <rtc_cmd_meas_saradc+33>:	slli	a2, a2, 8
   0x4008f444 <rtc_cmd_meas_saradc+36>:	or	a2, a5, a2
   0x4008f447 <rtc_cmd_meas_saradc+39>:	retw.n
   0x4008f449:	ill
(gdb) x /1x 0x4008f41c
0x4008f41c:	0x50000000

7.7 rtc_cmd_write_mem

   0x4008f44c <rtc_cmd_write_mem>:	entry	a1, 32
   0x4008f44f <rtc_cmd_write_mem+3>:	l32r	a9, 0x400804d8
   0x4008f452 <rtc_cmd_write_mem+6>:	extui	a4, a4, 0, 2
   0x4008f455 <rtc_cmd_write_mem+9>:	extui	a3, a3, 0, 5
   0x4008f458 <rtc_cmd_write_mem+12>:	or	a4, a4, a9
   0x4008f45b <rtc_cmd_write_mem+15>:	extui	a2, a2, 0, 3
   0x4008f45e <rtc_cmd_write_mem+18>:	slli	a3, a3, 2
   0x4008f461 <rtc_cmd_write_mem+21>:	or	a3, a4, a3
   0x4008f464 <rtc_cmd_write_mem+24>:	slli	a2, a2, 7
   0x4008f467 <rtc_cmd_write_mem+27>:	or	a2, a3, a2
   0x4008f46a <rtc_cmd_write_mem+30>:	retw.n
(gdb) x /1x 0x400804d8
0x400804d8:	0x60000000

7.8 rtc_cmd_reg0_alu

   0x4008f470 <rtc_cmd_reg0_alu>:	entry	a1, 32
   0x4008f473 <rtc_cmd_reg0_alu+3>:	l32r	a9, 0x4008f46c
   0x4008f476 <rtc_cmd_reg0_alu+6>:	extui	a4, a4, 0, 2
   0x4008f479 <rtc_cmd_reg0_alu+9>:	extui	a3, a3, 0, 4
   0x4008f47c <rtc_cmd_reg0_alu+12>:	or	a4, a4, a9
   0x4008f47f <rtc_cmd_reg0_alu+15>:	extui	a2, a2, 0, 8
   0x4008f482 <rtc_cmd_reg0_alu+18>:	slli	a3, a3, 2
   0x4008f485 <rtc_cmd_reg0_alu+21>:	or	a3, a4, a3
   0x4008f488 <rtc_cmd_reg0_alu+24>:	slli	a2, a2, 6
   0x4008f48b <rtc_cmd_reg0_alu+27>:	or	a2, a3, a2
   0x4008f48e <rtc_cmd_reg0_alu+30>:	retw.n
(gdb) x /1x 0x4008f46c
0x4008f46c:	0x70000000

7.9 rtc_cmd_stage_alu

   0x4008f494 <rtc_cmd_stage_alu>:	entry	a1, 32
   0x4008f497 <rtc_cmd_stage_alu+3>:	l32r	a9, 0x4008f490
   0x4008f49a <rtc_cmd_stage_alu+6>:	extui	a3, a3, 0, 4
   0x4008f49d <rtc_cmd_stage_alu+9>:	extui	a2, a2, 0, 4
   0x4008f4a0 <rtc_cmd_stage_alu+12>:	slli	a3, a3, 2
   0x4008f4a3 <rtc_cmd_stage_alu+15>:	or	a3, a3, a9
   0x4008f4a6 <rtc_cmd_stage_alu+18>:	slli	a2, a2, 6
   0x4008f4a9 <rtc_cmd_stage_alu+21>:	or	a2, a3, a2
   0x4008f4ac <rtc_cmd_stage_alu+24>:	retw.n
(gdb) x /1x 0x4008f490
0x4008f490:	0x72000000

7.10 rtc_cmd_force_branch

   0x4008f4b0 <rtc_cmd_force_branch>:	entry	a1, 32
   0x4008f4b3 <rtc_cmd_force_branch+3>:	l32r	a8, 0x40080690
   0x4008f4b6 <rtc_cmd_force_branch+6>:	slli	a2, a2, 17
   0x4008f4b9 <rtc_cmd_force_branch+9>:	or	a2, a2, a8
   0x4008f4bc <rtc_cmd_force_branch+12>:	retw.n
(gdb) x /1x 0x40080690
0x40080690:	0x80000000

7.11 rtc_cmd_reg0_branch

   0x4008f4c4 <rtc_cmd_reg0_branch>:	entry	a1, 32
   0x4008f4c7 <rtc_cmd_reg0_branch+3>:	l32r	a8, 0x4008f4c0
   0x4008f4ca <rtc_cmd_reg0_branch+6>:	slli	a3, a3, 16
   0x4008f4cd <rtc_cmd_reg0_branch+9>:	or	a4, a4, a8
   0x4008f4d0 <rtc_cmd_reg0_branch+12>:	or	a3, a4, a3
   0x4008f4d3 <rtc_cmd_reg0_branch+15>:	slli	a2, a2, 17
   0x4008f4d6 <rtc_cmd_reg0_branch+18>:	or	a2, a3, a2
   0x4008f4d9 <rtc_cmd_reg0_branch+21>:	retw.n
(gdb) x /1x 0x4008f4c0
0x4008f4c0:	0x82000000

7.12 rtc_cmd_stage_branch

   0x4008f4dc <rtc_cmd_stage_branch>:	entry	a1, 32
   0x4008f4df <rtc_cmd_stage_branch+3>:	l32r	a9, 0x400807d0
   0x4008f4e2 <rtc_cmd_stage_branch+6>:	extui	a4, a4, 0, 4
   0x4008f4e5 <rtc_cmd_stage_branch+9>:	extui	a3, a3, 0, 2
   0x4008f4e8 <rtc_cmd_stage_branch+12>:	or	a4, a4, a9
   0x4008f4eb <rtc_cmd_stage_branch+15>:	extui	a2, a2, 0, 8
   0x4008f4ee <rtc_cmd_stage_branch+18>:	slli	a3, a3, 15
   0x4008f4f1 <rtc_cmd_stage_branch+21>:	or	a3, a4, a3
   0x4008f4f4 <rtc_cmd_stage_branch+24>:	slli	a2, a2, 17
   0x4008f4f7 <rtc_cmd_stage_branch+27>:	or	a2, a3, a2
   0x4008f4fa <rtc_cmd_stage_branch+30>:	retw.n
(gdb) x /1x 0x400807d0
0x400807d0:	0x84000000

7.13 rtc_cmd_cpu_wakeup

   0x4008f500 <rtc_cmd_cpu_wakeup>:	entry	a1, 32
   0x4008f503 <rtc_cmd_cpu_wakeup+3>:	l32r	a8, 0x4008f4fc
   0x4008f506 <rtc_cmd_cpu_wakeup+6>:	or	a2, a2, a8
   0x4008f509 <rtc_cmd_cpu_wakeup+9>:	retw.n
(gdb) x /1x 0x4008f4fc
0x4008f4fc:	0x90000000

7.14 rtc_cmd_sleep_cyc_sel

   0x4008f510 <rtc_cmd_sleep_cyc_sel>:	entry	a1, 32
   0x4008f513 <rtc_cmd_sleep_cyc_sel+3>:	l32r	a8, 0x4008f50c
   0x4008f516 <rtc_cmd_sleep_cyc_sel+6>:	or	a2, a2, a8
   0x4008f519 <rtc_cmd_sleep_cyc_sel+9>:	retw.n
(gdb) x /1x 0x4008f50c
0x4008f50c:	0x92000000

7.15 rtc_cmd_meas_end

   0x4008f520 <rtc_cmd_meas_end>:	entry	a1, 32
   0x4008f523 <rtc_cmd_meas_end+3>:	l32r	a2, 0x4008f51c
   0x4008f526 <rtc_cmd_meas_end+6>:	retw.n
(gdb) x /1x 0x4008f51c
0x4008f51c:	0xb0000000