2016年12月8日 (四) 22:58的版本

Overview

 REG_SET_BITS(RTC_CNTL_TIMER1_REG, p3 << 24, RTC_CNTL_PLL_BUF_WAIT_M)
 REG_SET_BITS(RTC_CNTL_TIMER1_REG, p2 << 14, RTC_CNTL_XTL_BUF_WAIT_M)
 REG_SET_BITS(RTC_CNTL_TIMER1_REG, p1 << 6, RTC_CNTL_CK8M_WAIT_M)

0x4008e5a0 <rtc_init>:	entry	a1, 48
0x4008e5a3 <rtc_init+3>:	l32r	a8, 0x4008e57c  /* a8 = 0x3ff4801c, RTC_CNTL_TIMER1_REG */
0x4008e5a6 <rtc_init+6>:	l32r	a10, 0x40084ce0  /* a10 = 0x00ffffff */
0x4008e5a9 <rtc_init+9>:	memw
0x4008e5ac <rtc_init+12>:	l32i.n	a9, a8, 0
0x4008e5ae <rtc_init+14>:	slli	a4, a4, 24  /* p3 << 24 */
0x4008e5b1 <rtc_init+17>:	and	a9, a9, a10
0x4008e5b4 <rtc_init+20>:	or	a9, a4, a9  /* set BIT[31:24] = p3 */
0x4008e5b7 <rtc_init+23>:	memw
0x4008e5ba <rtc_init+26>:	s32i.n	a9, a8, 0
0x4008e5bc <rtc_init+28>:	memw
/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40; PLL wait cycles in slow_clk_rtc*/

0x4008e5bf <rtc_init+31>:	l32i.n	a9, a8, 0
0x4008e5c1 <rtc_init+33>:	l32r	a10, 0x4008e580  /* a8 = 0xff003fff, BIT[23:14] */
0x4008e5c4 <rtc_init+36>:	extui	a3, a3, 0, 10  /* p2[9:0] */
0x4008e5c7 <rtc_init+39>:	slli	a4, a3, 14  /* p2[9:0] << 14 */
0x4008e5ca <rtc_init+42>:	and	a9, a9, a10
0x4008e5cd <rtc_init+45>:	or	a9, a4, a9
0x4008e5d0 <rtc_init+48>:	memw
0x4008e5d3 <rtc_init+51>:	s32i.n	a9, a8, 0
0x4008e5d5 <rtc_init+53>:	memw
/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; XTAL wait cycles in slow_clk_rtc */

0x4008e5d8 <rtc_init+56>:	l32i.n	a4, a8, 0
0x4008e5da <rtc_init+58>:	l32r	a9, 0x4008e584  /* a8 = 0xffffc03f, BIT[13:6] */
0x4008e5dd <rtc_init+61>:	extui	a2, a2, 0, 8  /* p1[7:0] */
0x4008e5e0 <rtc_init+64>:	and	a4, a4, a9
0x4008e5e3 <rtc_init+67>:	slli	a10, a2, 6  /* p1[7:0] << 6 */
0x4008e5e6 <rtc_init+70>:	l32r	a9, 0x4008e588  /* a9 = 0x3ff48078, RTC_CNTL_BIAS_CONF_REG */
0x4008e5e9 <rtc_init+73>:	or	a4, a10, a4
0x4008e5ec <rtc_init+76>:	memw
0x4008e5ef <rtc_init+79>:	s32i.n	a4, a8, 0
0x4008e5f1 <rtc_init+81>:	memw
/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; CK8M wait cycles in slow_clk_rtc */

0x4008e5f4 <rtc_init+84>:	l32i.n	a8, a9, 0  /* read RTC_CNTL_BIAS_CONF_REG */
0x4008e5f6 <rtc_init+86>:	l32r	a4, 0x4008b7a4  /* a4 = 0x03000000 */
0x4008e5f9 <rtc_init+89>:	or	a4, a8, a4
0x4008e5fc <rtc_init+92>:	memw
0x4008e5ff <rtc_init+95>:	s32i.n	a4, a9, 0  /* set BIT[25:24] */
0x4008e601 <rtc_init+97>:	memw
/* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:24] ;default: 2'b00; DBG_ATTEN*/

REG_SET_BIT(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_M);

0x4008e604 <rtc_init+100>:	l32i.n	a4, a9, 0  /* read RTC_CNTL_BIAS_CONF_REG */
0x4008e606 <rtc_init+102>:	l32r	a8, 0x400804f0  /* a8 = 0x60000000 */
0x4008e609 <rtc_init+105>:	or	a4, a4, a8
0x4008e60c <rtc_init+108>:	memw
0x4008e60f <rtc_init+111>:	s32i.n	a4, a9, 0  /* set BIT[30:29] */
/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0; DEC_HEARTBEAT_WIDTH*/
/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0; INC_HEARTBEAT_PERIOD*/

REG_SET_BIT(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DEC_HEARTBEAT_WIDTH | RTC_CNTL_INC_HEARTBEAT_PERIOD);

0x4008e611 <rtc_init+113>:	beqz	a5, 0x4008e820 <rtc_init+640>   // p4 == 0, jump ------->

0x4008e614 <rtc_init+116>:	l32r	a4, 0x4008e53c  /* a4 = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */
0x4008e617 <rtc_init+119>:	l32r	a9, 0x4008c008  /* a9 = 0xfbffffff */
0x4008e61a <rtc_init+122>:	memw
0x4008e61d <rtc_init+125>:	l32i.n	a10, a4, 0
0x4008e61f <rtc_init+127>:	l32r	a8, 0x400804e0  /* a8 = 0x3ff48000, RTC_CNTL_OPTIONS0_REG */
0x4008e622 <rtc_init+130>:	and	a9, a10, a9  /* set BIT[26] */
0x4008e625 <rtc_init+133>:	memw
0x4008e628 <rtc_init+136>:	s32i.n	a9, a4, 0
0x4008e62a <rtc_init+138>:	memw
/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0; CK8M force power up*/

REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);

0x4008e62d <rtc_init+141>:	l32i.n	a10, a8, 0  /* read RTC_CNTL_OPTIONS0_REG */
0x4008e62f <rtc_init+143>:	l32r	a9, 0x4008db64  /* a9 = 0xffffdfff */
0x4008e632 <rtc_init+146>:	l32r	a4, 0x40088ad4  /* a4 = 0xffbfffff */
0x4008e635 <rtc_init+149>:	and	a9, a10, a9  /* clear BIT[13] */
0x4008e638 <rtc_init+152>:	memw
0x4008e63b <rtc_init+155>:	s32i.n	a9, a8, 0
0x4008e63d <rtc_init+157>:	memw
/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1; crystall force power up*/

REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);

0x4008e640 <rtc_init+160>:	l32i.n	a9, a8, 0  /* read RTC_CNTL_OPTIONS0_REG */
0x4008e642 <rtc_init+162>:	l32r	a10, 0x4008cb04  /* a10 = 0xfff7ffff */
0x4008e645 <rtc_init+165>:	and	a9, a9, a4  /* clear BIT[22] */
0x4008e648 <rtc_init+168>:	memw
0x4008e64b <rtc_init+171>:	s32i.n	a9, a8, 0
0x4008e64d <rtc_init+173>:	memw
/* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22]; BIAS_CORE force power up*/

REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PU);

0x4008e650 <rtc_init+176>:	l32i.n	a9, a8, 0  /* read RTC_CNTL_OPTIONS0_REG */
0x4008e652 <rtc_init+178>:	and	a9, a9, a10  /* clear BIT[19] */
0x4008e655 <rtc_init+181>:	memw
0x4008e658 <rtc_init+184>:	s32i.n	a9, a8, 0
0x4008e65a <rtc_init+186>:	memw
/* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1; BIAS_I2C force power up*/

REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PU;

0x4008e65d <rtc_init+189>:	l32i.n	a11, a8, 0
0x4008e65f <rtc_init+191>:	l32r	a9, 0x4008c0e4  /* a9 = 0xfffeffff */
0x4008e662 <rtc_init+194>:	and	a9, a11, a9  /* clear bit 16 */
0x4008e665 <rtc_init+197>:	memw
0x4008e668 <rtc_init+200>:	s32i.n	a9, a8, 0
0x4008e66a <rtc_init+202>:	memw
/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep*/

REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);

0x4008e66d <rtc_init+205>:	l32i.n	a9, a8, 0
0x4008e66f <rtc_init+207>:	and	a4, a9, a4  /* a4 = 0xffbfffff, clear bit 22 */
0x4008e672 <rtc_init+210>:	memw
0x4008e675 <rtc_init+213>:	s32i.n	a4, a8, 0
0x4008e677 <rtc_init+215>:	memw
/* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22]; BIAS_CORE force power up*/

REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PU);

0x4008e67a <rtc_init+218>:	l32i.n	a4, a8, 0
0x4008e67c <rtc_init+220>:	l32r	a9, 0x4008e4d4  /* a9 = 0x3ff48030 */
0x4008e67f <rtc_init+223>:	and	a4, a4, a10
0x4008e682 <rtc_init+226>:	memw
0x4008e685 <rtc_init+229>:	s32i.n	a4, a8, 0
0x4008e687 <rtc_init+231>:	memw

0x4008e68a <rtc_init+234>:	l32i.n	a11, a8, 0
0x4008e68c <rtc_init+236>:	l32r	a4, 0x4008ada0  /* 0x00100000 */
0x4008e68f <rtc_init+239>:	or	a4, a11, a4
0x4008e692 <rtc_init+242>:	memw
0x4008e695 <rtc_init+245>:	s32i.n	a4, a8, 0
0x4008e697 <rtc_init+247>:	memw

0x4008e69a <rtc_init+250>:	l32i.n	a11, a8, 0
0x4008e69c <rtc_init+252>:	l32r	a4, 0x40087268  /* 0x00020000 */
0x4008e69f <rtc_init+255>:	or	a4, a11, a4
0x4008e6a2 <rtc_init+258>:	memw
0x4008e6a5 <rtc_init+261>:	s32i.n	a4, a8, 0
0x4008e6a7 <rtc_init+263>:	memw

0x4008e6aa <rtc_init+266>:	l32i.n	a11, a9, 0
0x4008e6ac <rtc_init+268>:	l32r	a4, 0x4008c000 /* 0xfeffffff */
0x4008e6af <rtc_init+271>:	and	a4, a11, a4
0x4008e6b2 <rtc_init+274>:	memw
0x4008e6b5 <rtc_init+277>:	s32i.n	a4, a9, 0
0x4008e6b7 <rtc_init+279>:	memw

0x4008e6ba <rtc_init+282>:	l32i.n	a11, a9, 0
0x4008e6bc <rtc_init+284>:	l32r	a4, 0x40084ce8  /* 0x00800000 */
0x4008e6bf <rtc_init+287>:	or	a4, a11, a4
0x4008e6c2 <rtc_init+290>:	memw
0x4008e6c5 <rtc_init+293>:	s32i.n	a4, a9, 0
0x4008e6c7 <rtc_init+295>:	memw

0x4008e6ca <rtc_init+298>:	l32i.n	a11, a8, 0
0x4008e6cc <rtc_init+300>:	l32r	a4, 0x40088a14  /* 0xfffff7ff */
0x4008e6cf <rtc_init+303>:	l32r	a9, 0x4008e58c  /* 0x3ff4807c */
0x4008e6d2 <rtc_init+306>:	and	a4, a11, a4
0x4008e6d5 <rtc_init+309>:	memw
0x4008e6d8 <rtc_init+312>:	s32i.n	a4, a8, 0
0x4008e6da <rtc_init+314>:	memw

0x4008e6dd <rtc_init+317>:	l32i.n	a12, a8, 0
0x4008e6df <rtc_init+319>:	movi	a4, 0xfffffdff
0x4008e6e2 <rtc_init+322>:	and	a4, a12, a4
0x4008e6e5 <rtc_init+325>:	memw
0x4008e6e8 <rtc_init+328>:	s32i.n	a4, a8, 0
0x4008e6ea <rtc_init+330>:	memw

0x4008e6ed <rtc_init+333>:	l32i.n	a8, a9, 0
0x4008e6ef <rtc_init+335>:	l32r	a11, 0x400804c0  /* 0x7fffffff */
0x4008e6f2 <rtc_init+338>:	l32r	a4, 0x40086318   /* 0xdfffffff */
0x4008e6f5 <rtc_init+341>:	and	a8, a8, a11
0x4008e6f8 <rtc_init+344>:	memw
0x4008e6fb <rtc_init+347>:	s32i.n	a8, a9, 0
0x4008e6fd <rtc_init+349>:	memw

0x4008e700 <rtc_init+352>:	l32i.n	a8, a9, 0
0x4008e702 <rtc_init+354>:	and	a8, a8, a4
0x4008e705 <rtc_init+357>:	memw
0x4008e708 <rtc_init+360>:	s32i.n	a8, a9, 0
0x4008e70a <rtc_init+362>:	memw

0x4008e70d <rtc_init+365>:	l32i.n	a8, a9, 0

0x4008e70f <rtc_init+367>:	beqz.n	a7, 0x4008e720 <rtc_init+384>

0x4008e711 <rtc_init+369>:	l32r	a7, 0x400865e0  /* 0x10000000 */
0x4008e714 <rtc_init+372>:	or	a7, a8, a7
0x4008e717 <rtc_init+375>:	memw
0x4008e71a <rtc_init+378>:	s32i.n	a7, a9, 0
0x4008e71c <rtc_init+380>:	j	0x4008e72b <rtc_init+395>
0x4008e71e <rtc_init+382>:	0x0000

0x4008e720 <rtc_init+384>:	l32r	a7, 0x40087248  /* 0xefffffff */
0x4008e723 <rtc_init+387>:	and	a7, a8, a7
0x4008e726 <rtc_init+390>:	memw
0x4008e729 <rtc_init+393>:	s32i.n	a7, a9, 0

>>>>
0x4008e72b <rtc_init+395>:	l32r	a8, 0x4008e2f0  /* 0x3ff48084 */
0x4008e72e <rtc_init+398>:	movi.n	a7, -17
0x4008e730 <rtc_init+400>:	memw
0x4008e733 <rtc_init+403>:	l32i.n	a9, a8, 0
0x4008e735 <rtc_init+405>:	and	a7, a9, a7
0x4008e738 <rtc_init+408>:	memw
0x4008e73b <rtc_init+411>:	s32i.n	a7, a8, 0
0x4008e73d <rtc_init+413>:	memw

0x4008e740 <rtc_init+416>:	l32i.n	a9, a8, 0
0x4008e742 <rtc_init+418>:	l32r	a7, 0x400855d8  /* 0xffefffff */
0x4008e745 <rtc_init+421>:	and	a7, a9, a7
0x4008e748 <rtc_init+424>:	memw
0x4008e74b <rtc_init+427>:	s32i.n	a7, a8, 0
0x4008e74d <rtc_init+429>:	memw

0x4008e750 <rtc_init+432>:	l32i.n	a9, a8, 0
0x4008e752 <rtc_init+434>:	l32r	a7, 0x4008c704  /* 0xfffbffff *?
0x4008e755 <rtc_init+437>:	and	a7, a9, a7
0x4008e758 <rtc_init+440>:	memw
0x4008e75b <rtc_init+443>:	s32i.n	a7, a8, 0
0x4008e75d <rtc_init+445>:	memw

0x4008e760 <rtc_init+448>:	l32i.n	a12, a8, 0
0x4008e762 <rtc_init+450>:	l32r	a7, 0x4008e590  /* 0xfffeaabf */
0x4008e765 <rtc_init+453>:	l32r	a9, 0x4008e2f4  /* 0x3ff48080 */
0x4008e768 <rtc_init+456>:	and	a7, a12, a7
0x4008e76b <rtc_init+459>:	memw
0x4008e76e <rtc_init+462>:	s32i.n	a7, a8, 0
0x4008e770 <rtc_init+464>:	memw

0x4008e773 <rtc_init+467>:	l32i.n	a12, a9, 0
0x4008e775 <rtc_init+469>:	l32r	a7, 0x4008e594  /* 0xfffedfff */
0x4008e778 <rtc_init+472>:	l32r	a8, 0x4008e598  /* 0x3ff48088 */
0x4008e77b <rtc_init+475>:	and	a7, a12, a7
0x4008e77e <rtc_init+478>:	memw
0x4008e781 <rtc_init+481>:	s32i.n	a7, a9, 0
0x4008e783 <rtc_init+483>:	memw

0x4008e786 <rtc_init+486>:	l32i.n	a7, a9, 0
0x4008e788 <rtc_init+488>:	and	a10, a7, a10
0x4008e78b <rtc_init+491>:	memw
0x4008e78e <rtc_init+494>:	s32i.n	a10, a9, 0
0x4008e790 <rtc_init+496>:	memw

0x4008e793 <rtc_init+499>:	l32i.n	a7, a8, 0
0x4008e795 <rtc_init+501>:	and	a11, a7, a11
0x4008e798 <rtc_init+504>:	memw
0x4008e79b <rtc_init+507>:	s32i.n	a11, a8, 0
0x4008e79d <rtc_init+509>:	memw

0x4008e7a0 <rtc_init+512>:	l32i.n	a7, a8, 0
0x4008e7a2 <rtc_init+514>:	and	a4, a7, a4
0x4008e7a5 <rtc_init+517>:	memw
0x4008e7a8 <rtc_init+520>:	s32i.n	a4, a8, 0
0x4008e7aa <rtc_init+522>:	memw

0x4008e7ad <rtc_init+525>:	l32i.n	a7, a8, 0
0x4008e7af <rtc_init+527>:	l32r	a4, 0x4008e59c  /* 0xf555ffff */
0x4008e7b2 <rtc_init+530>:	and	a4, a7, a4
0x4008e7b5 <rtc_init+533>:	memw
0x4008e7b8 <rtc_init+536>:	s32i.n	a4, a8, 0
0x4008e7ba <rtc_init+538>:	memw

0x4008e7bd <rtc_init+541>:	l32i.n	a7, a9, 0
0x4008e7bf <rtc_init+543>:	movi.n	a4, -6
0x4008e7c1 <rtc_init+545>:	and	a4, a7, a4
0x4008e7c4 <rtc_init+548>:	memw
0x4008e7c7 <rtc_init+551>:	s32i.n	a4, a9, 0
0x4008e7c9 <rtc_init+553>:	memw

0x4008e7cc <rtc_init+556>:	l32i.n	a7, a9, 0
0x4008e7ce <rtc_init+558>:	movi	a4, -33
0x4008e7d1 <rtc_init+561>:	and	a4, a7, a4
0x4008e7d4 <rtc_init+564>:	memw
0x4008e7d7 <rtc_init+567>:	s32i.n	a4, a9, 0
0x4008e7d9 <rtc_init+569>:	memw

0x4008e7dc <rtc_init+572>:	l32i.n	a7, a8, 0
0x4008e7de <rtc_init+574>:	l32r	a4, 0x40080434  /* 0xffffbfff */
0x4008e7e1 <rtc_init+577>:	and	a4, a7, a4
0x4008e7e4 <rtc_init+580>:	memw
0x4008e7e7 <rtc_init+583>:	s32i.n	a4, a8, 0
0x4008e7e9 <rtc_init+585>:	memw

0x4008e7ec <rtc_init+588>:	l32i.n	a7, a8, 0
0x4008e7ee <rtc_init+590>:	l32r	a4, 0x4008724c  /* 0xffffefff */
0x4008e7f1 <rtc_init+593>:	and	a4, a7, a4
0x4008e7f4 <rtc_init+596>:	memw
0x4008e7f7 <rtc_init+599>:	s32i.n	a4, a8, 0

0x4008e7f9 <rtc_init+601>:	beqz.n	a6, 0x4008e80e <rtc_init+622> // if (a6 == 0); jump to 622 --->

0x4008e7fb <rtc_init+603>:	movi.n	a15, 1
0x4008e7fd <rtc_init+605>:	s32i.n	a15, a1, 0
0x4008e7ff <rtc_init+607>:	mov.n	a10, a15
0x4008e801 <rtc_init+609>:	mov.n	a11, a15
0x4008e803 <rtc_init+611>:	mov.n	a12, a15
0x4008e805 <rtc_init+613>:	mov.n	a13, a15
0x4008e807 <rtc_init+615>:	mov.n	a14, a15
0x4008e809 <rtc_init+617>:	call8	0x4008e318 <rtc_lslp_mem_inf_pd_cfg>  /* rtc_lslp_mem_inf_pd_cfg(0, 0, 0, 0, 0, 0);
0x4008e80c <rtc_init+620>:	retw.n

0x4008e80e <rtc_init+622>:	s32i.n	a6, a1, 0
0x4008e810 <rtc_init+624>:	mov.n	a10, a6
0x4008e812 <rtc_init+626>:	mov.n	a11, a6
0x4008e814 <rtc_init+628>:	mov.n	a12, a6
0x4008e816 <rtc_init+630>:	mov.n	a13, a6
0x4008e818 <rtc_init+632>:	mov.n	a14, a6
0x4008e81a <rtc_init+634>:	or	a15, a6, a6
0x4008e81d <rtc_init+637>:	call8	0x4008e318 <rtc_lslp_mem_inf_pd_cfg> /* rtc_lslp_mem_inf_pd_cfg(0, 0, 0, 0, 0, p5);
0x4008e820 <rtc_init+640>:	retw.n