查看ESP32 RTC Sleep Prepare的源代码
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ESP32 RTC Sleep Prepare
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== rtc_digital_lp_mode == <source lang=c> void rtc_digital_lp_mode() { REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, 0x05550000); // iram4 ~ iram0 and rom are force iso REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x0000aaa0); // iram4 ~ iram0 and rom are force power down REG_WRITE(DPORT_PERIP_CLK_EN_REG, 0x0); REG_WRITE(DPORT_WIFI_CLK_EN_REG, 0x0); REG_CLR_BIT(DPORT_WIFI_CLK_EN_REG, 0x40); // seems like to enable the MAC clk of wifi ?? REG_SET_BIT(DPORT_WIFI_RST_EN_REG, DPORT_MAC_RST); // wifi mac reset REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO); // wifi force iso REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD); // wifi power down REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, 0x10000000, RTC_CNTL_SOC_CLK_SEL_M); // select the CK8K REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, 0x00001500, 0x00003f00); // crystall, BB_PLL, BB_PLL_I2C force power down REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PD) // bias core force power down REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); // bias i2c force power down } </source> <source lang=c> 0x4008f0cc <rtc_digital_lp_mode>: entry a1, 32 0x4008f0cf <rtc_digital_lp_mode+3>: l32r a9, 0x4008e598 /* a9 = 0x3ff48088, RTC_CNTL_DIG_ISO_REG */ 0x4008f0d2 <rtc_digital_lp_mode+6>: l32r a10, 0x4008f0c0 /* a10 = 0x05550000 */ 0x4008f0d5 <rtc_digital_lp_mode+9>: memw 0x4008f0d8 <rtc_digital_lp_mode+12>: l32i.n a11, a9, 0 0x4008f0da <rtc_digital_lp_mode+14>: l32r a8, 0x4008e2f0 /* a8 = 0x3ff48084, RTC_CNTL_DIG_PWC_REG */ 0x4008f0dd <rtc_digital_lp_mode+17>: or a10, a11, a10 /* set BIT[26], 24, 22, 20, 18, 16 */ 0x4008f0e0 <rtc_digital_lp_mode+20>: memw 0x4008f0e3 <rtc_digital_lp_mode+23>: s32i.n a10, a9, 0 0x4008f0e5 <rtc_digital_lp_mode+25>: memw /* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0; internal SRAM 4 force ISO*/ /* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0; internal SRAM 3 force ISO*/ /* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0; internal SRAM 2 force ISO*/ /* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0; internal SRAM 1 force ISO*/ 0x4008f0e8 <rtc_digital_lp_mode+28>: l32i.n a11, a8, 0 0x4008f0ea <rtc_digital_lp_mode+30>: l32r a10, 0x4008f0c4 /* a10 = 0x0000aaa0 */ 0x4008f0ed <rtc_digital_lp_mode+33>: l32r a12, 0x4008f0c8 /* a12 = 0x3ff000c0 */ 0x4008f0f0 <rtc_digital_lp_mode+36>: or a10, a11, a10 /* set BIT[15], 13, 11, 9, 7, 5 */ 0x4008f0f3 <rtc_digital_lp_mode+39>: memw 0x4008f0f6 <rtc_digital_lp_mode+42>: s32i.n a10, a8, 0 /* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0; internal SRAM 4 force power down*/ /* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0; internal SRAM 3 force power down*/ /* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0; internal SRAM 2 force power down*/ /* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0; internal SRAM 1 force power down*/ /* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0; internal SRAM 0 force power down*/ /* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0; ROM force power down*/ 0x4008f0f8 <rtc_digital_lp_mode+44>: movi.n a11, 0 0x4008f0fa <rtc_digital_lp_mode+46>: l32r a10, 0x4008efb4 /* a10 = 0x3ff000cc */ 0x4008f0fd <rtc_digital_lp_mode+49>: memw 0x4008f100 <rtc_digital_lp_mode+52>: s32i.n a11, a12, 0 /* set DPORT_PERIP_CLK_EN_REG to 0 */ #define DR_REG_DPORT_BASE 0x3ff00000 #define DPORT_PERIP_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0C0) #define DPORT_WIFI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0CC) 0x4008f102 <rtc_digital_lp_mode+54>: memw 0x4008f105 <rtc_digital_lp_mode+57>: s32i.n a11, a10, 0 /* set DPORT_WIFI_CLK_EN_REG to 0 */ 0x4008f107 <rtc_digital_lp_mode+59>: memw 0x4008f10a <rtc_digital_lp_mode+62>: l32i.n a13, a10, 0 /* read DPORT_WIFI_CLK_EN_REG */ 0x4008f10c <rtc_digital_lp_mode+64>: movi a12, -65 /* a12 = 0xffff ffbf */ 0x4008f10f <rtc_digital_lp_mode+67>: l32r a11, 0x4008efb8 /* a11 = 0x3ff000d0 */ 0x4008f112 <rtc_digital_lp_mode+70>: and a12, a13, a12 /* clear BIT[6] */ 0x4008f115 <rtc_digital_lp_mode+73>: memw 0x4008f118 <rtc_digital_lp_mode+76>: s32i.n a12, a10, 0 0x4008f11a <rtc_digital_lp_mode+78>: memw /* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 0x4008f11d <rtc_digital_lp_mode+81>: l32i.n a12, a11, 0 /* read DPORT_WIFI_RST_EN_REG */ 0x4008f11f <rtc_digital_lp_mode+83>: movi.n a10, 4 0x4008f121 <rtc_digital_lp_mode+85>: or a10, a12, a10 /* set BIT[2], DPORT_MAC_RST */ 0x4008f124 <rtc_digital_lp_mode+88>: memw 0x4008f127 <rtc_digital_lp_mode+91>: s32i.n a10, a11, 0 0x4008f129 <rtc_digital_lp_mode+93>: memw 0x4008f12c <rtc_digital_lp_mode+96>: l32i.n a11, a9, 0 /* read RTC_CNTL_DIG_ISO_REG */ 0x4008f12e <rtc_digital_lp_mode+98>: l32r a10, 0x400865e0 /* a10 = 0x10000000 */ 0x4008f131 <rtc_digital_lp_mode+101>: or a11, a11, a10 /* set BIT[28] */ 0x4008f134 <rtc_digital_lp_mode+104>: memw 0x4008f137 <rtc_digital_lp_mode+107>: s32i.n a11, a9, 0 0x4008f139 <rtc_digital_lp_mode+109>: memw /* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0; wifi force ISO*/ 0x4008f13c <rtc_digital_lp_mode+112>: l32i.n a12, a8, 0 /* read RTC_CNTL_DIG_PWC_REG */ 0x4008f13e <rtc_digital_lp_mode+114>: l32r a11, 0x40087268 /* a11 = 0x00020000 */ 0x4008f141 <rtc_digital_lp_mode+117>: l32r a9, 0x4008e53c /* a9 = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */ 0x4008f144 <rtc_digital_lp_mode+120>: or a11, a12, a11 /* set BIT[17] */ 0x4008f147 <rtc_digital_lp_mode+123>: memw 0x4008f14a <rtc_digital_lp_mode+126>: s32i.n a11, a8, 0 0x4008f14c <rtc_digital_lp_mode+128>: memw /* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0; wifi force power down*/ 0x4008f14f <rtc_digital_lp_mode+131>: l32i.n a12, a9, 0 /* read RTC_CNTL_CLK_CONF_REG */ 0x4008f151 <rtc_digital_lp_mode+133>: l32r a11, 0x400865dc /* a11 = 0xe7ffffff */ 0x4008f154 <rtc_digital_lp_mode+136>: l32r a8, 0x400804e0 /* a8 = 0x3ff48000, RTC_CNTL_OPTIONS0_REG */ 0x4008f157 <rtc_digital_lp_mode+139>: and a11, a12, a11 0x4008f15a <rtc_digital_lp_mode+142>: or a10, a11, a10 /* clear BIT[28:27] and set to 0x2 */ 0x4008f15d <rtc_digital_lp_mode+145>: memw 0x4008f160 <rtc_digital_lp_mode+148>: s32i.n a10, a9, 0 0x4008f162 <rtc_digital_lp_mode+150>: memw /* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0; SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ 0x4008f165 <rtc_digital_lp_mode+153>: l32i.n a10, a8, 0 /* read RTC_CNTL_OPTIONS0_REG */ 0x4008f167 <rtc_digital_lp_mode+155>: l32r a9, 0x4008ba54 /* a9 = 0xffffc0ff */ 0x4008f16a <rtc_digital_lp_mode+158>: and a9, a10, a9 0x4008f16d <rtc_digital_lp_mode+161>: l32r a10, 0x4008e540 /* a10 = 0x00001500 */ 0x4008f170 <rtc_digital_lp_mode+164>: or a9, a9, a10 /* clear BIT[13:8] and set to 0x15 */ 0x4008f173 <rtc_digital_lp_mode+167>: memw 0x4008f176 <rtc_digital_lp_mode+170>: s32i.n a9, a8, 0 0x4008f178 <rtc_digital_lp_mode+172>: memw /* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1; crystall force power up*/ /* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0; crystall force power down*/ /* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0; BB_PLL force power up*/ /* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0; BB_PLL force power down*/ /* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0; BB_PLL_I2C force power up*/ /* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0; BB_PLL _I2C force power down*/ 0x4008f17b <rtc_digital_lp_mode+175>: l32i.n a10, a8, 0 /* read RTC_CNTL_OPTIONS0_REG */ 0x4008f17d <rtc_digital_lp_mode+177>: l32r a9, 0x40087764 /* a9 = 0x00200000 */ 0x4008f180 <rtc_digital_lp_mode+180>: or a9, a10, a9 /* set BIT[21] */ 0x4008f183 <rtc_digital_lp_mode+183>: memw 0x4008f186 <rtc_digital_lp_mode+186>: s32i.n a9, a8, 0 0x4008f188 <rtc_digital_lp_mode+188>: memw /* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0; BIAS_CORE force power down*/ 0x4008f18b <rtc_digital_lp_mode+191>: l32i.n a10, a8, 0 /* read RTC_CNTL_OPTIONS0_REG */ 0x4008f18d <rtc_digital_lp_mode+193>: l32r a9, 0x4008a52c /* a9 = 0x00040000 */ 0x4008f190 <rtc_digital_lp_mode+196>: or a9, a10, a9 /* set BIT[18] */ 0x4008f193 <rtc_digital_lp_mode+199>: memw 0x4008f196 <rtc_digital_lp_mode+202>: s32i.n a9, a8, 0 /* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0; BIAS_I2C force power down*/ 0x4008f198 <rtc_digital_lp_mode+204>: retw.n </source> <br> <br><br> <br><br> <br><br> <br><br> <br><br> <br><br>
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ESP32 RTC Sleep Prepare
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