查看ESP32 RTC Sleep Prepare的源代码
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ESP32 RTC Sleep Prepare
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== rtc_slowck_cali == p1: <source lang=cpp> typedef enum { CALI_RTC_MUX = 0, CALI_8MD256 = 1, CALI_32K_XTAL = 2 } cali_clk_t; </source> <source lang=bash> 0x4008ecd4 <rtc_slowck_cali>: entry a1, 32 0x4008ecd7 <rtc_slowck_cali+3>: bnei a2, 2, 0x4008ecf1 <rtc_slowck_cali+29> /* p1 == 2 */ 0x4008ecda <rtc_slowck_cali+6>: l32r a4, 0x4008e660 /* 0x3ff48070, read RTC_CNTL_CLK_CONF_REG */ 0x4008ecdd <rtc_slowck_cali+9>: movi a8, 0x100 0x4008ece0 <rtc_slowck_cali+12>: memw 0x4008ece3 <rtc_slowck_cali+15>: l32i.n a9, a4, 0 0x4008ece5 <rtc_slowck_cali+17>: or a8, a9, a8 /* set bit[8] */ 0x4008ece8 <rtc_slowck_cali+20>: memw 0x4008eceb <rtc_slowck_cali+23>: s32i.n a8, a4, 0 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); 0x4008eced <rtc_slowck_cali+25>: j 0x4008ed09 <rtc_slowck_cali+53> 0x4008ecef <rtc_slowck_cali+27>: 0x0000 >>>> 0x4008ecf1 <rtc_slowck_cali+29>: bnei a2, 1, 0x4008ed09 <rtc_slowck_cali+53> /* p1 == 1 */ 0x4008ecf4 <rtc_slowck_cali+32>: l32r a4, 0x4008e660 /* 0x3ff48070, read RTC_CNTL_CLK_CONF_REG */ 0x4008ecf7 <rtc_slowck_cali+35>: movi a8, 0x200 0x4008ecfa <rtc_slowck_cali+38>: memw 0x4008ecfd <rtc_slowck_cali+41>: l32i a9, a4, 0 0x4008ed00 <rtc_slowck_cali+44>: or a8, a9, a8 /* set bit[9] */ 0x4008ed03 <rtc_slowck_cali+47>: memw 0x4008ed06 <rtc_slowck_cali+50>: s32i a8, a4, 0 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN); >>>> /* p1 == 0 */ 0x4008ed09 <rtc_slowck_cali+53>: l32r a4, 0x4008ecc4 /* 0x6001f068 */ 0x4008ed0c <rtc_slowck_cali+56>: l32r a8, 0x4008ecc8 /* 0xffff9fff */ 0x4008ed0f <rtc_slowck_cali+59>: memw 0x4008ed12 <rtc_slowck_cali+62>: l32i.n a10, a4, 0 /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00013000 */ 0x4008ed14 <rtc_slowck_cali+64>: extui a9, a2, 0, 2 0x4008ed17 <rtc_slowck_cali+67>: slli a9, a9, 13 0x4008ed1a <rtc_slowck_cali+70>: and a8, a10, a8 0x4008ed1d <rtc_slowck_cali+73>: or a8, a9, a8 /* clear and set bit[14:13] */ 0x4008ed20 <rtc_slowck_cali+76>: memw 0x4008ed23 <rtc_slowck_cali+79>: s32i.n a8, a4, 0 0x4008ed25 <rtc_slowck_cali+81>: memw 0x4008ed28 <rtc_slowck_cali+84>: l32i.n a9, a4, 0 /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00011000 */ 0x4008ed2a <rtc_slowck_cali+86>: l32r a8, 0x40087370 /* 0xffffefff */ 0x4008ed2d <rtc_slowck_cali+89>: and a8, a9, a8 /* clear bit[12] */ 0x4008ed30 <rtc_slowck_cali+92>: memw 0x4008ed33 <rtc_slowck_cali+95>: s32i.n a8, a4, 0 0x4008ed35 <rtc_slowck_cali+97>: memw 0x4008ed38 <rtc_slowck_cali+100>: l32i.n a10, a4, 0 /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00010000 */ 0x4008ed3a <rtc_slowck_cali+102>: l32r a8, 0x4008eccc /* 0x8000ffff */ 0x4008ed3d <rtc_slowck_cali+105>: extui a9, a3, 0, 15 /* p2[15:0] */ 0x4008ed40 <rtc_slowck_cali+108>: slli a9, a9, 16 0x4008ed43 <rtc_slowck_cali+111>: and a8, a10, a8 0x4008ed46 <rtc_slowck_cali+114>: or a8, a9, a8 /* clear and set bit[30:16] */ 0x4008ed49 <rtc_slowck_cali+117>: memw 0x4008ed4c <rtc_slowck_cali+120>: s32i.n a8, a4, 0 0x4008ed4e <rtc_slowck_cali+122>: memw 0x4008ed51 <rtc_slowck_cali+125>: l32i.n a9, a4, 0 /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00010000 */ 0x4008ed53 <rtc_slowck_cali+127>: l32r a8, 0x400806f4 /* 0x7fffffff */ 0x4008ed56 <rtc_slowck_cali+130>: movi a10, 0x12c 0x4008ed59 <rtc_slowck_cali+133>: and a8, a9, a8 /* clear bit[31] */ 0x4008ed5c <rtc_slowck_cali+136>: memw 0x4008ed5f <rtc_slowck_cali+139>: s32i.n a8, a4, 0 0x4008ed61 <rtc_slowck_cali+141>: memw 0x4008ed64 <rtc_slowck_cali+144>: l32i.n a9, a4, 0 /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00010000 */ 0x4008ed66 <rtc_slowck_cali+146>: l32r a8, 0x400806b8 /* 0x80000000 */ 0x4008ed69 <rtc_slowck_cali+149>: or a8, a9, a8 /* set bit[31] = 1 */ 0x4008ed6c <rtc_slowck_cali+152>: memw 0x4008ed6f <rtc_slowck_cali+155>: s32i a8, a4, 0 0x4008ed72 <rtc_slowck_cali+158>: l32r a8, 0x40080848 /* a8 = 0x40008534, ets_delay_us */ 0x4008ed75 <rtc_slowck_cali+161>: callx8 a8 /* ets_delay_us(300) */ 0x4008ed78 <rtc_slowck_cali+164>: l32r a9, 0x400879e0 /* a9 = 0x00008000 */ >>>> 0x4008ed7b <rtc_slowck_cali+167>: memw 0x4008ed7e <rtc_slowck_cali+170>: l32i.n a8, a4, 0 /* read 0x6001f068 (DR_REG_BB_BASE+0x68) */ 0x4008ed80 <rtc_slowck_cali+172>: bnone a8, a9, 0x4008ed7b <rtc_slowck_cali+167> if a8[15] is not set, then branch ----> 0x4008ed83 <rtc_slowck_cali+175>: bnei a2, 2, 0x4008ed9c <rtc_slowck_cali+200> 0x4008ed86 <rtc_slowck_cali+178>: l32r a2, 0x4008e660 /* 0x4008ed89 <rtc_slowck_cali+181>: movi a4, 0xfffffeff 0x4008ed8c <rtc_slowck_cali+184>: memw 0x4008ed8f <rtc_slowck_cali+187>: l32i.n a8, a2, 0 0x4008ed91 <rtc_slowck_cali+189>: and a4, a8, a4 0x4008ed94 <rtc_slowck_cali+192>: memw 0x4008ed97 <rtc_slowck_cali+195>: s32i.n a4, a2, 0 0x4008ed99 <rtc_slowck_cali+197>: j 0x4008edb4 <rtc_slowck_cali+224> >>>> 0x4008ed9c <rtc_slowck_cali+200>: bnei a2, 1, 0x4008edb4 <rtc_slowck_cali+224> 0x4008ed9f <rtc_slowck_cali+203>: l32r a2, 0x4008e660 /* 0x3ff48070, read RTC_CNTL_CLK_CONF_REG */ 0x4008eda2 <rtc_slowck_cali+206>: movi a4, 0xfffffdff 0x4008eda5 <rtc_slowck_cali+209>: memw 0x4008eda8 <rtc_slowck_cali+212>: l32i a8, a2, 0 0x4008edab <rtc_slowck_cali+215>: and a4, a8, a4 /* clear bit[9] */ 0x4008edae <rtc_slowck_cali+218>: memw 0x4008edb1 <rtc_slowck_cali+221>: s32i a4, a2, 0 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN); >>>> 0x4008edb4 <rtc_slowck_cali+224>: l32r a2, 0x4008ecd0 /* 0x6001f06c, (DR_REG_BB_BASE+0x6c) */ 0x4008edb7 <rtc_slowck_cali+227>: memw 0x4008edba <rtc_slowck_cali+230>: l32i a2, a2, 0 /* a2 = 0x00026280 = 156288 */ 0x4008edbd <rtc_slowck_cali+233>: call8 0x4008fb14 <rtc_get_xtal> 0x4008edc0 <rtc_slowck_cali+236>: mull a12, a10, a3 //a12 = 300 * p2, a10 = 300 0x4008edc3 <rtc_slowck_cali+239>: srli a10, a2, 7 // a10 = 0x4c5 = 1221 0x4008edc6 <rtc_slowck_cali+242>: extui a11, a2, 20, 12 // a11 = 0 0x4008edc9 <rtc_slowck_cali+245>: movi a13, 0 // a13 = 0 0x4008edcc <rtc_slowck_cali+248>: slli a10, a10, 19 // a10 = 1221 * 2^19 = 640155648 0x4008edcf <rtc_slowck_cali+251>: call8 0x400e7440 <__udivdi3> 0x4008edd2 <rtc_slowck_cali+254>: mov.n a2, a10 0x4008edd4 <rtc_slowck_cali+256>: retw.n </source> <br><br>
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ESP32 RTC Sleep Prepare
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