查看ESP32 RTC Sleep Prepare的源代码
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ESP32 RTC Sleep Prepare
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== rtc_slp_prep_lite == <source lang=cpp> #define DEEP_SLEEP_PD_NORMAL BIT(0) /* Base deep sleep mode */ #define DEEP_SLEEP_PD_RTC_PERIPH BIT(1) /* Power down RTC peripherals */ #define DEEP_SLEEP_PD_RTC_SLOW_MEM BIT(2) /* Power down RTC SLOW memory */ #define DEEP_SLEEP_PD_RTC_FAST_MEM BIT(3) /* Power down RTC FAST memory */ /* * @brief Prepare for entering sleep mode * @param deep_slp DEEP_SLEEP_PD_ flags combined with OR (DEEP_SLEEP_PD_NORMAL must be included) * @param cpu_lp_mode for deep sleep, should be 0 */ void rtc_slp_prep_lite(uint32_t deep_slp, uint32_t cpu_lp_mode); </source> <source lang=bash> 0x4008f5f8 <rtc_slp_prep_lite>: entry a1, 80 0x4008f5fb <rtc_slp_prep_lite+3>: movi.n a9, 4 /* a9 = 4 */ 0x4008f5fd <rtc_slp_prep_lite+5>: movi.n a13, 0 /* a13 = 0 */ 0x4008f5ff <rtc_slp_prep_lite+7>: mov.n a10, a9 /* a10 = 4 */ 0x4008f601 <rtc_slp_prep_lite+9>: movnez a10, a13, a3 /* a10 = 0 = a13, if (a3 != 0) */ 0x4008f604 <rtc_slp_prep_lite+12>: movi.n a8, 2 /* a8 = 2 */ 0x4008f606 <rtc_slp_prep_lite+14>: mov.n a11, a13 /* a11 = 0 = a13 */ 0x4008f608 <rtc_slp_prep_lite+16>: extui a12, a2, 0, 1 /* a12 = a2[0] */ 0x4008f60b <rtc_slp_prep_lite+19>: movnez a11, a8, a3 /* a11 = 2 = a8, if (a3 != 0) */ // if (a3 != 0), then: a10 = 0, a11 = 2 // if (a3 == 0), then: a10 = 4, a11 = 0 0x4008f60e <rtc_slp_prep_lite+22>: and a9, a2, a9 /* a9 = a2 & 0x4, a2 is the 1st param deep_slp */ 0x4008f611 <rtc_slp_prep_lite+25>: and a8, a2, a8 /* a8 = a2 & 0x2 */ 0x4008f614 <rtc_slp_prep_lite+28>: s32i.n a10, a1, 28 // if (a3 == 0) *(a1 + 28) = 4 OR *(a1 + 28) = 0 0x4008f616 <rtc_slp_prep_lite+30>: movi.n a14, 16 0x4008f618 <rtc_slp_prep_lite+32>: l32r a10, 0x4008f5f4 /* a10 = *(0x4008f5f4 ) = 0xdd000000 */ 0x4008f61b <rtc_slp_prep_lite+35>: movi.n a15, 8 0x4008f61d <rtc_slp_prep_lite+37>: s32i.n a12, a1, 16 // *(a1 + 16) = deep_slp[0] 0x4008f61f <rtc_slp_prep_lite+39>: s32i.n a9, a1, 0 // *(a1 + 0) = deep_slp & 0x4 0x4008f621 <rtc_slp_prep_lite+41>: s32i.n a8, a1, 4 // *(a1 + 4) = deep_slp & 0x2 0x4008f623 <rtc_slp_prep_lite+43>: s32i.n a13, a1, 8 // *(a1 + 8) = 0 0x4008f625 <rtc_slp_prep_lite+45>: s32i.n a13, a1, 12 // *(a1 + 12) = 0 // *(a1 + 16) = deep_slp[0] 0x4008f627 <rtc_slp_prep_lite+47>: s32i.n a13, a1, 20 // *(a1 + 20) = 0 0x4008f629 <rtc_slp_prep_lite+49>: s32i.n a3, a1, 24 // *(a1 + 24) = a3, cpu_lp_mode 0x4008f62b <rtc_slp_prep_lite+51>: s32i.n a13, a1, 32 // *(a1 + 32) = 0 0x4008f62d <rtc_slp_prep_lite+53>: s32i.n a13, a1, 36 // *(a1 + 36) = 0 0x4008f62f <rtc_slp_prep_lite+55>: s32i.n a13, a1, 40 // *(a1 + 40) = 0 0x4008f631 <rtc_slp_prep_lite+57>: mov.n a12, a13 // a12 = 0 a13 = 0 0x4008f633 <rtc_slp_prep_lite+59>: and a14, a2, a14 // a14 = deep_slp & 0x10 0x4008f636 <rtc_slp_prep_lite+62>: and a15, a2, a15 // a15 = deep_slp & 0x8 0x4008f639 <rtc_slp_prep_lite+65>: call8 0x4008f248 <rtc_slp_prep> 0x4008f63c <rtc_slp_prep_lite+68>: retw.n </source> ;;cpu_lp_mode == 0 (deep sleep), the parameters of rtc_slp_prep(): <pre> * 1st param, a10 = 0xdd000000 * 2nd param, a11 = 0 /* SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL */ <----------- * 3rd param, a12 = 0 /* 1: memories in digital core force no PD in sleep; 0: memories in digital core force PD in sleep */ * 4th param, a13 = 0 /* 1: Slow and Fast RTC memory force power up; 0: clear */ * 5th param, a14 = deep_slp & 0x10 /* 1: Power down the RTC memory and Fast RTC memory; 0: clear */ * 6th param, a15 = deep_slp & 0x8 /* 0: RTC Fast Memory not Power down; 1: RTC Fast Memory Power down in sleep */ *(a1 + 0) = deep_slp & 0x4 /* 0: RTC memory not power down in sleep; 1: RTC memory power down in sleep */ *(a1 + 4) = deep_slp & 0x2 /* 0: RTC_PERI not power down; 1: RTC_PERI power down in sleep */ *(a1 + 8) = 0 /* 0: wifi not power down in sleep, 1: wifi power down in sleep */ *(a1 + 12) = 0 /* 0: SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are not power down in sleep; 1: SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are power down in sleep */ *(a1 + 16) = deep_slp[0] /* 0: BIAS_SLEEP force sleep; 1: BIAS_SLEEP force no sleep */ *(a1 + 20) = 0 *(a1 + 24) = a3, cpu_lp_mode *(a1 + 28) = 4 *(a1 + 32) = 0 *(a1 + 36) = 0 *(a1 + 40) = 0 </pre> 4th param: * ==0: RTC memory and Fast RTC memory force power up clear * !=0: RTC memory and Fast RTC memory force power up set */ ;;cpu_lp_mode != 0, the parameters of rtc_slp_prep(): * 1st param, a10 = 0xdd000000 * 2nd param, a11 = 2 <----------- * 3rd param, a12 = 0 * 4th param, a13 = 0 * 5th param, a14 = deep_slp & 0x10 * 6th param, a15 = deep_slp & 0x8 *(a1 + 0) = deep_slp & 0x4 *(a1 + 4) = deep_slp & 0x2 *(a1 + 8) = 0 *(a1 + 12) = 0 *(a1 + 16) = deep_slp[0] *(a1 + 20) = 0 *(a1 + 24) = a3, cpu_lp_mode *(a1 + 28) = 0 <-------------- *(a1 + 32) = 0 *(a1 + 36) = 0 *(a1 + 40) = 0 <br><br>
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ESP32 RTC Sleep Prepare
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