查看ESP32 RTC Sleep Prepare的源代码
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ESP32 RTC Sleep Prepare
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=== Part Two === <source lang=c> rtc_uart_div_modify(0); REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, 0xdd00 0000); // clear PLL_I2C/CKGEN_I2C/RFRX_PBUS/TXRF_I2C/PVTMON/PLLA REG_CLR_BIT(SARADC_SAR_MEAS_WAIT2_REG, SARADC_FORCE_XPD_SAR_M); // 0x3 << 18 if (p3 != 0) { REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x1 << 4); // memories in digital core force power up in sleep } else { REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x1 << 4); // memories in digital core force no power up in sleep } if (p4 != 0) { REG_SET_BIT(RTC_CNTL_PWC_REG, 0x00012000); // set BIT[13], 16 // RTC memory and Fast RTC memory force power up } else { REG_CLR_BIT(RTC_CNTL_PWC_REG, 0x00012000); // clear BIT[13], 16 // RTC memory and Fast RTC memory force no power up } // p5 = deep_slp & 0x10, BIT[4] if (p5 != 0) { // Power down the RTC memory and Fast RTC memory REG_SET_BIT(RTC_CNTL_PWC_REG, 0x0000 0240); // set BIT[9], 6 /* * RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0; * 1: RTC memory PD following CPU * 0: RTC memory PD following RTC state machine * * RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 * 1: Fast RTC memory PD following CPU * 0: fast RTC memory PD following RTC state machine */ } else { REG_CLR_BIT(RTC_CNTL_PWC_REG, 0x0000 0240); // clear BIT[9], 6 } // p6 = deep_slp & 0x8, BIT[3], PD_RTC_FAST_MEM if (p6 != 0) { // Power down Fast Memory REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN); REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU); REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO) } else { // Power up fast memory REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN); REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU); REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO) } </source> <source lang=bash> >>>>>>>>>>>>>>>>>>>>>>>> 0x4008f34e <rtc_slp_prep+394>: movi a10, 0 0x4008f351 <rtc_slp_prep+397>: call8 0x4008fa5c <rtc_uart_div_modify> /* rtc_uart_div_modify(0) */ 0x4008f354 <rtc_slp_prep+400>: l32r a8, 0x4008e4d4 /* a8 = 0x3ff48030, RTC_CNTL_ANA_CONF_REG */ 0x4008f357 <rtc_slp_prep+403>: movi a3, -1 /* a3 = 0xffff ffff */ 0x4008f35a <rtc_slp_prep+406>: memw 0x4008f35d <rtc_slp_prep+409>: l32i a9, a8, 0 0x4008f360 <rtc_slp_prep+412>: xor a2, a3, a2 /* a2 = ~p1 = 0x22ff ffff */ 0x4008f363 <rtc_slp_prep+415>: and a2, a2, a9 /* clear BIT[31], 30, 28, 27, 26, 24 */ 0x4008f366 <rtc_slp_prep+418>: l32r a3, 0x4008bff8 /* a3 = 0x3ff4880c, SARADC_SAR_MEAS_WAIT2_REG */ 0x4008f369 <rtc_slp_prep+421>: memw 0x4008f36c <rtc_slp_prep+424>: s32i.n a2, a8, 0 0x4008f36e <rtc_slp_prep+426>: memw /* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0; 1: PLL_I2C power up otherwise power down*/ /* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0; 1: CKGEN_I2C power up otherwise power down*/ /* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0; 1: RFRX_PBUS power up otherwise power down*/ /* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0; 1: TXRF_I2C power up otherwise power down*/ /* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0; 1: PVTMON power up otherwise power down*/ /* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; PLLA force power up*/ 0x4008f371 <rtc_slp_prep+429>: l32i.n a8, a3, 0 0x4008f373 <rtc_slp_prep+431>: l32r a2, 0x4008af28 /* a2 = 0xfff3ffff */ 0x4008f376 <rtc_slp_prep+434>: and a2, a8, a2 /* clear BIT[19:18] of SARADC_SAR_MEAS_WAIT2_REG */ 0x4008f379 <rtc_slp_prep+437>: memw 0x4008f37c <rtc_slp_prep+440>: s32i.n a2, a3, 0 /* SARADC_FORCE_XPD_SAR : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ 0x4008f37e <rtc_slp_prep+442>: l32r a2, 0x4008e2f0 /* a2 = 0x3ff48084, RTC_CNTL_DIG_PWC_REG */ <<<===== 0x4008f381 <rtc_slp_prep+445>: beqz.n a4, 0x4008f395 ------> if (a4 == 0); jump to 465 (a4 is 0 in lite) 0x4008f383 <rtc_slp_prep+447>: memw 0x4008f386 <rtc_slp_prep+450>: l32i.n a4, a2, 0 /* a4 = 0x80000000 */ 0x4008f388 <rtc_slp_prep+452>: movi.n a3, 16 0x4008f38a <rtc_slp_prep+454>: or a3, a4, a3 /* (RTC_CNTL_DIG_PWC_REG | 0x10) */ 0x4008f38d <rtc_slp_prep+457>: memw 0x4008f390 <rtc_slp_prep+460>: s32i.n a3, a2, 0 /* set BIT[4] = 1 */ /* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; memories in digital core force no PD in sleep*/ 0x4008f392 <rtc_slp_prep+462>: j 0x4008f3a4 <rtc_slp_prep+480> >>>>>>>>> 0x4008f395 <rtc_slp_prep+465>: memw 0x4008f398 <rtc_slp_prep+468>: l32i.n a4, a2, 0 0x4008f39a <rtc_slp_prep+470>: movi.n a3, -17 /* a3 = 0xffff ffef */ 0x4008f39c <rtc_slp_prep+472>: and a3, a4, a3 /* clear BIT[4] */ 0x4008f39f <rtc_slp_prep+475>: memw 0x4008f3a2 <rtc_slp_prep+478>: s32i.n a3, a2, 0 /* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; memories in digital core force no PD in sleep*/ >>>>>>>>> 0x4008f3a4 <rtc_slp_prep+480>: l32r a8, 0x4008e2f4 /* a8 = 0x3ff48080, RTC_CNTL_PWC_REG */ <<<===== 0x4008f3a7 <rtc_slp_prep+483>: memw 0x4008f3aa <rtc_slp_prep+486>: l32i.n a4, a8, 0 /* a4 = 0x00000000 */ 0x4008f3ac <rtc_slp_prep+488>: beqz.n a5, 0x4008f3bc if (a5 == 0); jump to 504 (a5 is 0 in lite) -----> >>>> a5 is non-zero 0x4008f3ae <rtc_slp_prep+490>: l32r a3, 0x4008f1b4 /* a3 = 0x00012000 */ 0x4008f3b1 <rtc_slp_prep+493>: or a3, a4, a3 /* set BIT[16] = 1, BIT[13] = 1 */ 0x4008f3b4 <rtc_slp_prep+496>: memw 0x4008f3b7 <rtc_slp_prep+499>: s32i.n a3, a8, 0 /* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1; RTC memory force power up*/ /* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1; Fast RTC memory force power up*/ 0x4008f3b9 <rtc_slp_prep+501>: j 0x4008f3c7 <rtc_slp_prep+515> >>>>>>>>> a5 is zero 0x4008f3bc <rtc_slp_prep+504>: l32r a3, 0x4008e594 /* a3 = 0xfffedfff */ 0x4008f3bf <rtc_slp_prep+507>: and a3, a4, a3 /* clear BIT[16], BIT[13] */ 0x4008f3c2 <rtc_slp_prep+510>: memw 0x4008f3c5 <rtc_slp_prep+513>: s32i.n a3, a8, 0 >>>>>>>>> 0x4008f3c7 <rtc_slp_prep+515>: memw 0x4008f3ca <rtc_slp_prep+518>: l32i.n a4, a8, 0 0x4008f3cc <rtc_slp_prep+520>: beqz.n a6, 0x4008f3dc <rtc_slp_prep+536> if (a6 == 0); jump to 536 (a6 is 0 in lite) -----> /* a6 = deep_slp & 0x10, BIT[4] */ If (a6 set BIT[4]); then: >>> Power down the RTC memory and Fast RTC memory 0x4008f3ce <rtc_slp_prep+522>: movi a3, 0x240 0x4008f3d1 <rtc_slp_prep+525>: or a3, a4, a3 /* set BIT[9], BIT[6] = 1 */ 0x4008f3d4 <rtc_slp_prep+528>: memw 0x4008f3d7 <rtc_slp_prep+531>: s32i.n a3, a8, 0 /* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0; * 1: RTC memory PD following CPU * 0: RTC memory PD following RTC state machine * * RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 * 1: Fast RTC memory PD following CPU * 0: fast RTC memory PD following RTC state machine */ 0x4008f3d9 <rtc_slp_prep+533>: j 0x4008f3e7 <rtc_slp_prep+547> >>>>>>>>> 0x4008f3dc <rtc_slp_prep+536>: movi a3, 0xfffffdbf 0x4008f3df <rtc_slp_prep+539>: and a3, a4, a3 /* clear BIT[9], BIT[6] */ 0x4008f3e2 <rtc_slp_prep+542>: memw 0x4008f3e5 <rtc_slp_prep+545>: s32i.n a3, a8, 0 >>>>>>>>> 0x4008f3e7 <rtc_slp_prep+547>: memw 0x4008f3ea <rtc_slp_prep+550>: l32i.n a4, a8, 0 0x4008f3ec <rtc_slp_prep+552>: beqz.n a7, 0x4008f41c <rtc_slp_prep+600> if (a7 == 0); jump to 600 ----> /* a7 = deep_slp & 0x8, BIT[3], PD_RTC_FAST_MEM */ //// Following to Power down Fast Memory 0x4008f3ee <rtc_slp_prep+554>: l32r a3, 0x400878b8 /* a3 = 0x00004000 */ 0x4008f3f1 <rtc_slp_prep+557>: or a3, a4, a3 /* set BIT[14] = 1 */ 0x4008f3f4 <rtc_slp_prep+560>: memw 0x4008f3f7 <rtc_slp_prep+563>: s32i.n a3, a8, 0 0x4008f3f9 <rtc_slp_prep+565>: memw /* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0; enable power down fast RTC memory in sleep*/ 0x4008f3fc <rtc_slp_prep+568>: l32i.n a4, a8, 0 0x4008f3fe <rtc_slp_prep+570>: l32r a3, 0x4008db64 /* a3 = 0xffffdfff */ 0x4008f401 <rtc_slp_prep+573>: and a3, a4, a3 /* clear BIT[13] */ 0x4008f404 <rtc_slp_prep+576>: memw 0x4008f407 <rtc_slp_prep+579>: s32i.n a3, a8, 0 0x4008f409 <rtc_slp_prep+581>: memw /* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1; Fast RTC memory force power up*/ 0x4008f40c <rtc_slp_prep+584>: l32i.n a4, a8, 0 0x4008f40e <rtc_slp_prep+586>: movi.n a3, -2 /* a3 = 0xffff fffe */ 0x4008f410 <rtc_slp_prep+588>: and a3, a4, a3 /* clear BIT[0] */ 0x4008f413 <rtc_slp_prep+591>: memw 0x4008f416 <rtc_slp_prep+594>: s32i.n a3, a8, 0 /* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1; Fast RTC memory force no ISO*/ 0x4008f418 <rtc_slp_prep+596>: j 0x4008f446 <rtc_slp_prep+642> 0x4008f41a <rtc_slp_prep+598>: 0x0000 >>>>>> Fast memory not power down 0x4008f41c <rtc_slp_prep+600>: l32r a3, 0x40080434 /* a3 = 0xffffbfff */ 0x4008f41f <rtc_slp_prep+603>: and a3, a4, a3 /* clear BIT[14] */ 0x4008f422 <rtc_slp_prep+606>: memw 0x4008f425 <rtc_slp_prep+609>: s32i.n a3, a8, 0 // Fast mem power down clear 0x4008f427 <rtc_slp_prep+611>: memw 0x4008f42a <rtc_slp_prep+614>: l32i.n a4, a8, 0 0x4008f42c <rtc_slp_prep+616>: l32r a3, 0x4008063c /* a3 = 0x00002000 */ 0x4008f42f <rtc_slp_prep+619>: or a3, a4, a3 /* set BIT[13] */ 0x4008f432 <rtc_slp_prep+622>: memw 0x4008f435 <rtc_slp_prep+625>: s32i.n a3, a8, 0 // Fast mem power up 0x4008f437 <rtc_slp_prep+627>: memw 0x4008f43a <rtc_slp_prep+630>: l32i.n a4, a8, 0 0x4008f43c <rtc_slp_prep+632>: movi.n a3, 1 0x4008f43e <rtc_slp_prep+634>: or a3, a4, a3 /* set BIT[0] */ 0x4008f441 <rtc_slp_prep+637>: memw 0x4008f444 <rtc_slp_prep+640>: s32i.n a3, a8, 0 // Force no ISO </source> <br>
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ESP32 RTC Sleep Prepare
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