查看ESP32 RTC Sleep Prepare的源代码
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ESP32 RTC Sleep Prepare
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=== Part three === <source lang=c> // p7 if (deep_slp & 0x4 != 0) { // Power down RTC memory (SLOW) REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN); REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU); REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_SLOWMEM_FORCE_NOISO) } else { REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN); REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU); REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_SLOWMEM_FORCE_NOISO) } // p8 if (deep_slp & 0x2 != 0) { REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN); // enable power down rtc_peri in sleep } else { REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN); // disable power down rtc_peri in sleep } // p9 = up_a1 + 8 = a1 + 48 + 8 if (p9 != 0) { // enable power down wifi in sleep REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } else { // disable power down wifi in sleep REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } // p10 = up_a1 + 12 = a1 + 48 + 12 if (p9 != 0) { // SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are power down in sleep // BIT[29:14] REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x3f000000); } else { // SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are not power down in sleep REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x3f000000); } // p11 = up_a1 + 16 = a1 + 48 + 16 if (p11 != 0) { rtc_deep_slp_conf(); REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP); // bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep } else { REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); // bitpos:[31] ;default: 1'd0; SW system reset* REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP); // R/W ;bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep } // p12 = *(a1 + 48 + 20), p13 = *(a1 + 48 + 24) = cpu_lp_mode rtc_dbias_cfg(p14, p15, p16, p17); if (p13 != 0) rtc_digital_lp_mode(); // cpu_lp_mode != 0; not deep sleep return; </source> <source lang=c> >>>>>> 0x4008f446 <rtc_slp_prep+642>: l32i.n a3, a1, 48 /* (a1 + 48 + 0), a3 = deep_slp & 0x4, BIT[2] */ 0x4008f448 <rtc_slp_prep+644>: memw 0x4008f44b <rtc_slp_prep+647>: l32i.n a4, a8, 0 0x4008f44d <rtc_slp_prep+649>: beqz.n a3, 0x4008f47c <rtc_slp_prep+696> if (a3 == 0); jump to 696 ---> >>>>> p1 Non-Zero, RTC memory power down in sleep 0x4008f44f <rtc_slp_prep+651>: l32r a3, 0x40087268 /* a3 = 0x00020000 */ 0x4008f452 <rtc_slp_prep+654>: or a3, a4, a3 /* set BIT[17] */ 0x4008f455 <rtc_slp_prep+657>: memw 0x4008f458 <rtc_slp_prep+660>: s32i.n a3, a8, 0 0x4008f45a <rtc_slp_prep+662>: memw /* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0; enable power down RTC memory in sleep*/ 0x4008f45d <rtc_slp_prep+665>: l32i.n a4, a8, 0 0x4008f45f <rtc_slp_prep+667>: l32r a3, 0x4008c0e4 /* a3 = 0xfffeffff */ 0x4008f462 <rtc_slp_prep+670>: and a3, a4, a3 /* clear BIT[16] */ 0x4008f465 <rtc_slp_prep+673>: memw 0x4008f468 <rtc_slp_prep+676>: s32i.n a3, a8, 0 0x4008f46a <rtc_slp_prep+678>: memw /* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1; RTC memory force power up*/ 0x4008f46d <rtc_slp_prep+681>: l32i.n a4, a8, 0 0x4008f46f <rtc_slp_prep+683>: movi.n a3, -5 /* a3 = 0xffff fffc */ 0x4008f471 <rtc_slp_prep+685>: and a3, a4, a3 /* clear BIT[1:0] */ 0x4008f474 <rtc_slp_prep+688>: memw 0x4008f477 <rtc_slp_prep+691>: s32i.n a3, a8, 0 /* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0; Fast RTC memory force ISO*/ /* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1; Fast RTC memory force no ISO*/ 0x4008f479 <rtc_slp_prep+693>: j 0x4008f4a6 <rtc_slp_prep+738> ---------> jump to 738 >>>>>p1 zero, RTC memory power up in sleep 0x4008f47c <rtc_slp_prep+696>: l32r a3, 0x400855e0 /* a3 = 0xfffdffff */ 0x4008f47f <rtc_slp_prep+699>: and a3, a4, a3 /* clear BIT[17] */ 0x4008f482 <rtc_slp_prep+702>: memw 0x4008f485 <rtc_slp_prep+705>: s32i.n a3, a8, 0 0x4008f487 <rtc_slp_prep+707>: memw /* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0; enable power down RTC memory in sleep*/ 0x4008f48a <rtc_slp_prep+710>: l32i.n a4, a8, 0 0x4008f48c <rtc_slp_prep+712>: l32r a3, 0x40088a98 /* a3 = 0x00010000 */ 0x4008f48f <rtc_slp_prep+715>: or a3, a4, a3 /* set BIT[16] = 1 */ 0x4008f492 <rtc_slp_prep+718>: memw 0x4008f495 <rtc_slp_prep+721>: s32i.n a3, a8, 0 0x4008f497 <rtc_slp_prep+723>: memw /* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1; RTC memory force power up*/ 0x4008f49a <rtc_slp_prep+726>: l32i.n a4, a8, 0 0x4008f49c <rtc_slp_prep+728>: movi.n a3, 4 /* a3 = 0x4 */ 0x4008f49e <rtc_slp_prep+730>: or a3, a4, a3 /* set BIT[2] = 1 */ 0x4008f4a1 <rtc_slp_prep+733>: memw 0x4008f4a4 <rtc_slp_prep+736>: s32i.n a3, a8, 0 /* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1; RTC memory force no ISO*/ >>>>>> 0x4008f4a6 <rtc_slp_prep+738>: l32i.n a3, a1, 52 /* load the param from stack */ a3 = 0x0 = deep_slp & 0x2 0x4008f4a8 <rtc_slp_prep+740>: memw 0x4008f4ab <rtc_slp_prep+743>: l32i.n a4, a8, 0 0x4008f4ad <rtc_slp_prep+745>: beqz.n a3, 0x4008f4bd <rtc_slp_prep+761> if (a3 == 0); jump 761 ----> /// RTC_PERI power down, Px Non-zero 0x4008f4af <rtc_slp_prep+747>: l32r a3, 0x4008ada0 /* a3 = 0x00100000 */ 0x4008f4b2 <rtc_slp_prep+750>: or a3, a4, a3 /* set BIT[20] */ 0x4008f4b5 <rtc_slp_prep+753>: memw 0x4008f4b8 <rtc_slp_prep+756>: s32i.n a3, a8, 0 /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0; enable power down rtc_peri in sleep*/ 0x4008f4ba <rtc_slp_prep+758>: j 0x4008f4c8 <rtc_slp_prep+772> >>>>>Px Zero, RTC_PERI not power down 0x4008f4bd <rtc_slp_prep+761>: l32r a3, 0x400855d8 /* a3 = 0xffefffff */ 0x4008f4c0 <rtc_slp_prep+764>: and a3, a4, a3 /* clear BIT[20] */ 0x4008f4c3 <rtc_slp_prep+767>: memw 0x4008f4c6 <rtc_slp_prep+770>: s32i.n a3, a8, 0 >>>>> 0x4008f4c8 <rtc_slp_prep+772>: l32i.n a3, a1, 56 /* load the param from stack */ a3 = 0x0 (up_a1 + 8) = a1 + 48 + 8 0x4008f4ca <rtc_slp_prep+774>: memw 0x4008f4cd <rtc_slp_prep+777>: l32i.n a4, a2, 0 /* read RTC_CNTL_DIG_PWC_REG */ 0x4008f4cf <rtc_slp_prep+779>: beqz.n a3, 0x4008f4e0 <rtc_slp_prep+796> if (a3 == 0); jump to 796 ----> >>>>> Pwifi Non-zero (wifi power down in sleep) 0x4008f4d1 <rtc_slp_prep+781>: l32r a3, 0x400805fc /* a3 = 0x40000000 */ 0x4008f4d4 <rtc_slp_prep+784>: or a3, a4, a3 /* set BIT[30] */ 0x4008f4d7 <rtc_slp_prep+787>: memw 0x4008f4da <rtc_slp_prep+790>: s32i.n a3, a2, 0 /* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0; enable power down wifi in sleep*/ 0x4008f4dc <rtc_slp_prep+792>: j 0x4008f4eb <rtc_slp_prep+807> 0x4008f4de <rtc_slp_prep+794>: 0x0000 >>>>> Pwifi is zero (wifi not power down in sleep) 0x4008f4e0 <rtc_slp_prep+796>: l32r a3, 0x4008838c /* a3 = 0xbfffffff */ 0x4008f4e3 <rtc_slp_prep+799>: and a3, a4, a3 /* clear BIT[30] */ 0x4008f4e6 <rtc_slp_prep+802>: memw 0x4008f4e9 <rtc_slp_prep+805>: s32i.n a3, a2, 0 0x4008f4eb <rtc_slp_prep+807>: l32i.n a3, a1, 60 /* load the param from stack */ a3 = 0 (ai + 48 + 12) 0x4008f4ed <rtc_slp_prep+809>: memw 0x4008f4f0 <rtc_slp_prep+812>: l32i.n a4, a2, 0 0x4008f4f2 <rtc_slp_prep+814>: beqz.n a3, 0x4008f505 <rtc_slp_prep+833> if (a3 == 0); jump to 833 -----> >>>> Pz is Non-zero 0x4008f4f4 <rtc_slp_prep+816>: l32r a3, 0x4008f1b8 /* a3 = 0x3f000000 */ 0x4008f4f7 <rtc_slp_prep+819>: or a3, a4, a3 /* set BIT[29:24] */ 0x4008f4fa <rtc_slp_prep+822>: memw 0x4008f4fd <rtc_slp_prep+825>: s32i.n a3, a2, 0 /* SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are power down in sleep */ 0x4008f4ff <rtc_slp_prep+827>: j 0x4008f510 <rtc_slp_prep+844> 0x4008f502 <rtc_slp_prep+830>: ill >>>> Pz is Zero 0x4008f505 <rtc_slp_prep+833>: l32r a3, 0x4008f1bc /* a3 = 0xc0ffffff */ 0x4008f508 <rtc_slp_prep+836>: and a3, a4, a3 /* clear BIT[29:24] */ 0x4008f50b <rtc_slp_prep+839>: memw 0x4008f50e <rtc_slp_prep+842>: s32i.n a3, a2, 0 /* SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are not power down in sleep */ >>>> 0x4008f510 <rtc_slp_prep+844>: l32i a3, a1, 64 /* load the param from stack */ a3 = 0x1 (a1 + 48 + 16) 0x4008f513 <rtc_slp_prep+847>: beqz.n a3, 0x4008f530 <rtc_slp_prep+876> if (a3 == 0); jump to 876 ---------> 0x4008f515 <rtc_slp_prep+849>: call8 0x4008f054 <rtc_deep_slp_conf> 0x4008f518 <rtc_slp_prep+852>: l32r a2, 0x400804e0 /* a2 = 0x3ff48000, RTC_CNTL_OPTIONS0_REG */ 0x4008f51b <rtc_slp_prep+855>: l32r a3, 0x4008c0e4 /* a3 = 0xfffeffff */ 0x4008f51e <rtc_slp_prep+858>: memw 0x4008f521 <rtc_slp_prep+861>: l32i.n a4, a2, 0 0x4008f523 <rtc_slp_prep+863>: and a3, a4, a3 /* clear BIT[16] */ 0x4008f526 <rtc_slp_prep+866>: memw 0x4008f529 <rtc_slp_prep+869>: s32i.n a3, a2, 0 /* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep*/ 0x4008f52b <rtc_slp_prep+871>: j 0x4008f556 <rtc_slp_prep+914> 0x4008f52d <rtc_slp_prep+873>: 0x000000 >>>> 0x4008f530 <rtc_slp_prep+876>: memw 0x4008f533 <rtc_slp_prep+879>: l32i a5, a2, 0 0x4008f536 <rtc_slp_prep+882>: l32r a4, 0x400804c0 /* a4 = 0x7fffffff */ 0x4008f539 <rtc_slp_prep+885>: l32r a3, 0x400804e0 /* a3 = 0x3ff48000, RTC_CNTL_OPTIONS0_REG */ 0x4008f53c <rtc_slp_prep+888>: and a4, a5, a4 /* clear BIT[31] */ 0x4008f53f <rtc_slp_prep+891>: memw 0x4008f542 <rtc_slp_prep+894>: s32i a4, a2, 0 0x4008f545 <rtc_slp_prep+897>: memw /* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0; SW system reset*/ 0x4008f548 <rtc_slp_prep+900>: l32i a4, a3, 0 0x4008f54b <rtc_slp_prep+903>: l32r a2, 0x40088a98 /* a2 = 0x00010000 */ 0x4008f54e <rtc_slp_prep+906>: or a2, a4, a2 /* set BIT[16] */ 0x4008f551 <rtc_slp_prep+909>: memw 0x4008f554 <rtc_slp_prep+912>: s32i.n a2, a3, 0 /* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep*/ >>>> 0x4008f556 <rtc_slp_prep+914>: l32i a10, a1, 76 /* a10 = 0x4, (a1 + 48 + 28) */ 0x4008f559 <rtc_slp_prep+917>: l32i a11, a1, 80 /* a11 = 0x0, (a1 + 48 + 32) */ 0x4008f55c <rtc_slp_prep+920>: l32i a12, a1, 84 /* a12 = 0x0, (a1 + 48 + 36) */ 0x4008f55f <rtc_slp_prep+923>: l32i a13, a1, 88 /* a13 = 0x0, (a1 + 48 + 40) */ 0x4008f562 <rtc_slp_prep+926>: call8 0x4008fe30 <rtc_dbias_cfg> 0x4008f565 <rtc_slp_prep+929>: l32i a2, a1, 72 /* a2 = 0x0, (a1 + 48 + 24), cpu_lp_mode */ 0x4008f568 <rtc_slp_prep+932>: beqz.n a2, 0x4008f56d <rtc_slp_prep+937> /* cp_lp_mode == 0, deep_sleep */ 0x4008f56a <rtc_slp_prep+934>: call8 0x4008f0cc <rtc_digital_lp_mode> /* not deep_sleep mode */ 0x4008f56d <rtc_slp_prep+937>: retw.n </source> <br><br>
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ESP32 RTC Sleep Prepare
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