查看ESP32 RTC Sleep Prepare的源代码
←
ESP32 RTC Sleep Prepare
跳转到:
导航
,
搜索
因为以下原因,你没有权限编辑本页:
您刚才请求的操作只有这个用户组中的用户才能使用:
用户
您可以查看并复制此页面的源代码:
=== Overview === <source lang=c> void rtc_slp_prep(p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15, p16, p17) { int tick_per_us = rtc_get_xtal(); REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, p2 << 27, RTC_CNTL_SOC_CLK_SEL_M); if (p2 == 1) { // PLL clock REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 24, RTC_CNTL_PLL_BUF_WAIT_M); // PLL wait cycles in slow_clk_rtc REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M); // XTAL wait cycles in slow_clk_rtc REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M); // CK8M wait cycles in slow_clk_rtc } else if (p2 == 0) { // XTAL clock REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M); // PLL wait cycles in slow_clk_rtc REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M); // XTAL wait cycles in slow_clk_rtc REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M); // CK8M wait cycles in slow_clk_rtc ets_update_cpu_frequency(ticks_per_us); rtc_apb_freq_up(ticks_per_us * 1000000); } else if (p2 == 2) { // CK8M clock REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 25, RTC_CNTL_ROM_RAM_POWERUP_TIMER_M); REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 16, RTC_CNTL_ROM_RAM_WAIT_TIMER_M); REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 9, RTC_CNTL_WIFI_POWERUP_TIMER_M); REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1, RTC_CNTL_WAIT_TIMER_M); REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M); // PLL wait cycles in slow_clk_rtc REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x3 << 14, RTC_CNTL_XTL_BUF_WAIT_M); // XTAL wait cycles in slow_clk_rtc REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M); // CK8M wait cycles in slow_clk_rtc ets_update_cpu_frequency(8); rtc_apb_freq_up(8000000); } rtc_uart_div_modify(0); REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, 0xdd00 0000); // clear PLL_I2C/CKGEN_I2C/RFRX_PBUS/TXRF_I2C/PVTMON/PLLA REG_CLR_BIT(SARADC_SAR_MEAS_WAIT2_REG, SARADC_FORCE_XPD_SAR_M); // 0x3 << 18 if (p3 != 0) { REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x1 << 4); // memories in digital core force power up in sleep } else { REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x1 << 4); // memories in digital core force no power up in sleep } if (p4 != 0) { REG_SET_BIT(RTC_CNTL_PWC_REG, 0x00012000); // set BIT[13], 16 // RTC memory and Fast RTC memory force power up } else { REG_CLR_BIT(RTC_CNTL_PWC_REG, 0x00012000); // clear BIT[13], 16 // RTC memory and Fast RTC memory force no power up } // p5 = deep_slp & 0x10, BIT[4] if (p5 != 0) { // Power down the RTC memory and Fast RTC memory REG_SET_BIT(RTC_CNTL_PWC_REG, 0x0000 0240); // set BIT[9], 6 /* * RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0; * 1: RTC memory PD following CPU * 0: RTC memory PD following RTC state machine * * RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 * 1: Fast RTC memory PD following CPU * 0: fast RTC memory PD following RTC state machine */ } else { REG_CLR_BIT(RTC_CNTL_PWC_REG, 0x0000 0240); // clear BIT[9], 6 } // p6 = deep_slp & 0x8, BIT[3], PD_RTC_FAST_MEM if (p6 != 0) { // Power down Fast Memory REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN); REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU); REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO) } else { // Power up fast memory REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN); REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU); REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO) } // p7 if (deep_slp & 0x4 != 0) { // Power down RTC memory (SLOW) REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN); REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU); REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_SLOWMEM_FORCE_NOISO) } else { REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN); REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU); REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_SLOWMEM_FORCE_NOISO) } // p8 if (deep_slp & 0x2 != 0) { REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN); // enable power down rtc_peri in sleep } else { REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN); // disable power down rtc_peri in sleep } // p9 = up_a1 + 8 = a1 + 48 + 8 if (p9 != 0) { // enable power down wifi in sleep REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } else { // disable power down wifi in sleep REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } // p10 = up_a1 + 12 = a1 + 48 + 12 if (p9 != 0) { // SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are power down in sleep // BIT[29:14] REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x3f000000); } else { // SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are not power down in sleep REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x3f000000); } // p11 = up_a1 + 16 = a1 + 48 + 16 if (p11 != 0) { rtc_deep_slp_conf(); REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP); // bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep } else { REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); // bitpos:[31] ;default: 1'd0; SW system reset* REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP); // R/W ;bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep } // p12 = *(a1 + 48 + 20), p13 = *(a1 + 48 + 24) = cpu_lp_mode rtc_dbias_cfg(p14, p15, p16, p17); if (p13 != 0) rtc_digital_lp_mode(); // cpu_lp_mode != 0; not deep sleep return; } void rtc_deep_slp_conf() { REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, 0x00003000); // clear DG_PAD_FORCE_ISO and DG_PAD_FORCE_NOISO REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x80000000); // enable power down digital core in sleep REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x00180000); // clear DG_WRAP_FORCE_PU and DG_WRAP_FORCE_PD REG_SET_BITS(RTC_CNTL_TIMER4_REG, 0x0200 0000, 0xfe000000); // DG_WRAP_POWERUP_TIMER = 0x1 REG_SET_BITS(RTC_CNTL_TIMER4_REG, 0x0001 0000, 0x01ff0000); // DG_WRAP_WAIT_TIMER = 0x1 } void rtc_dbias_cfg(p1, p2, p3, p4) { REG_SET_BITS(RTC_CNTL_REG, p4 << 22, RTC_CNTL_DBIAS_SLP_M); // RTC_DBIAS during sleep REG_SET_BITS(RTC_CNTL_REG, p1 << 11, RTC_CNTL_DIG_DBIAS_WAK_M); // DIG_REG_DBIAS during wakeup REG_SET_BITS(RTC_CNTL_REG, p2 << 8, RTC_CNTL_DIG_DBIAS_SLP_M); // DIG_REG_DBIAS during sleep } void rtc_digital_lp_mode() { REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, 0x05550000); // iram4 ~ iram0 and rom are force iso REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x0000aaa0); // iram4 ~ iram0 and rom are force power down REG_WRITE(DPORT_PERIP_CLK_EN_REG, 0x0); REG_WRITE(DPORT_WIFI_CLK_EN_REG, 0x0); REG_CLR_BIT(DPORT_WIFI_CLK_EN_REG, 0x40); // seems like to enable the MAC clk of wifi ?? REG_SET_BIT(DPORT_WIFI_RST_EN_REG, DPORT_MAC_RST); // wifi mac reset REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO); // wifi force iso REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD); // wifi power down REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, 0x10000000, RTC_CNTL_SOC_CLK_SEL_M); // select the CK8K REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, 0x00001500, 0x00003f00); // crystall, BB_PLL, BB_PLL_I2C force power down REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PD) // bias core force power down REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); // bias i2c force power down } </source> <br>
返回到
ESP32 RTC Sleep Prepare
。
个人工具
登录
名字空间
页面
讨论
变换
查看
阅读
查看源代码
查看历史
操作
搜索
导航
首页
社区专页
新闻动态
最近更改
随机页面
帮助
工具箱
链入页面
相关更改
特殊页面