ESP32 RTC Sleep Prepare

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(版本间的差异)
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(rtc_digital_lp_mode)
(rtc_slowck_cali)
 
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第53行: 第53行:
 
   uint32_t rtc_get_xtal();
 
   uint32_t rtc_get_xtal();
  
 +
 +
<br><br>
 +
 +
== rtc_slowck_cali ==
 +
 +
p1:
 +
 +
<source lang=cpp>
 +
typedef enum {
 +
    CALI_RTC_MUX = 0,
 +
    CALI_8MD256 = 1,
 +
    CALI_32K_XTAL = 2
 +
} cali_clk_t;
 +
</source>
 +
 +
<source lang=bash>
 +
0x4008ecd4 <rtc_slowck_cali>: entry a1, 32
 +
0x4008ecd7 <rtc_slowck_cali+3>: bnei a2, 2, 0x4008ecf1 <rtc_slowck_cali+29>
 +
 +
/* p1 == 2 */
 +
0x4008ecda <rtc_slowck_cali+6>: l32r a4, 0x4008e660  /* 0x3ff48070, read RTC_CNTL_CLK_CONF_REG */
 +
0x4008ecdd <rtc_slowck_cali+9>: movi a8, 0x100
 +
0x4008ece0 <rtc_slowck_cali+12>: memw
 +
0x4008ece3 <rtc_slowck_cali+15>: l32i.n a9, a4, 0
 +
0x4008ece5 <rtc_slowck_cali+17>: or a8, a9, a8  /* set bit[8] */
 +
0x4008ece8 <rtc_slowck_cali+20>: memw
 +
0x4008eceb <rtc_slowck_cali+23>: s32i.n a8, a4, 0
 +
/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
 +
/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
 +
REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
 +
 +
0x4008eced <rtc_slowck_cali+25>: j 0x4008ed09 <rtc_slowck_cali+53>
 +
 +
0x4008ecef <rtc_slowck_cali+27>: 0x0000
 +
 +
>>>>
 +
0x4008ecf1 <rtc_slowck_cali+29>: bnei a2, 1, 0x4008ed09 <rtc_slowck_cali+53>
 +
 +
/* p1 == 1 */
 +
0x4008ecf4 <rtc_slowck_cali+32>: l32r a4, 0x4008e660  /* 0x3ff48070, read RTC_CNTL_CLK_CONF_REG */
 +
0x4008ecf7 <rtc_slowck_cali+35>: movi a8, 0x200
 +
0x4008ecfa <rtc_slowck_cali+38>: memw
 +
0x4008ecfd <rtc_slowck_cali+41>: l32i a9, a4, 0
 +
0x4008ed00 <rtc_slowck_cali+44>: or a8, a9, a8  /* set bit[9] */
 +
0x4008ed03 <rtc_slowck_cali+47>: memw
 +
0x4008ed06 <rtc_slowck_cali+50>: s32i a8, a4, 0
 +
/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
 +
/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
 +
REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
 +
 +
>>>>  /* p1 == 0 */
 +
0x4008ed09 <rtc_slowck_cali+53>: l32r a4, 0x4008ecc4  /* 0x6001f068 */
 +
0x4008ed0c <rtc_slowck_cali+56>: l32r a8, 0x4008ecc8  /* 0xffff9fff */
 +
0x4008ed0f <rtc_slowck_cali+59>: memw
 +
0x4008ed12 <rtc_slowck_cali+62>: l32i.n a10, a4, 0    /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00013000 */
 +
0x4008ed14 <rtc_slowck_cali+64>: extui a9, a2, 0, 2
 +
0x4008ed17 <rtc_slowck_cali+67>: slli a9, a9, 13
 +
0x4008ed1a <rtc_slowck_cali+70>: and a8, a10, a8
 +
0x4008ed1d <rtc_slowck_cali+73>: or a8, a9, a8    /* clear and set bit[14:13] */
 +
0x4008ed20 <rtc_slowck_cali+76>: memw
 +
0x4008ed23 <rtc_slowck_cali+79>: s32i.n a8, a4, 0
 +
0x4008ed25 <rtc_slowck_cali+81>: memw
 +
 +
0x4008ed28 <rtc_slowck_cali+84>: l32i.n a9, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00011000 */
 +
0x4008ed2a <rtc_slowck_cali+86>: l32r a8, 0x40087370  /* 0xffffefff */
 +
0x4008ed2d <rtc_slowck_cali+89>: and a8, a9, a8  /* clear bit[12] */
 +
0x4008ed30 <rtc_slowck_cali+92>: memw
 +
0x4008ed33 <rtc_slowck_cali+95>: s32i.n a8, a4, 0
 +
0x4008ed35 <rtc_slowck_cali+97>: memw
 +
 +
0x4008ed38 <rtc_slowck_cali+100>: l32i.n a10, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00010000 */
 +
0x4008ed3a <rtc_slowck_cali+102>: l32r a8, 0x4008eccc  /* 0x8000ffff */
 +
0x4008ed3d <rtc_slowck_cali+105>: extui a9, a3, 0, 15  /* p2[15:0] */
 +
0x4008ed40 <rtc_slowck_cali+108>: slli a9, a9, 16
 +
0x4008ed43 <rtc_slowck_cali+111>: and a8, a10, a8
 +
0x4008ed46 <rtc_slowck_cali+114>: or a8, a9, a8  /* clear and set bit[30:16] */
 +
0x4008ed49 <rtc_slowck_cali+117>: memw
 +
0x4008ed4c <rtc_slowck_cali+120>: s32i.n a8, a4, 0
 +
0x4008ed4e <rtc_slowck_cali+122>: memw
 +
 +
0x4008ed51 <rtc_slowck_cali+125>: l32i.n a9, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00010000 */
 +
0x4008ed53 <rtc_slowck_cali+127>: l32r a8, 0x400806f4  /* 0x7fffffff */
 +
0x4008ed56 <rtc_slowck_cali+130>: movi a10, 0x12c
 +
0x4008ed59 <rtc_slowck_cali+133>: and a8, a9, a8  /* clear bit[31] */
 +
0x4008ed5c <rtc_slowck_cali+136>: memw
 +
0x4008ed5f <rtc_slowck_cali+139>: s32i.n a8, a4, 0
 +
0x4008ed61 <rtc_slowck_cali+141>: memw
 +
 +
0x4008ed64 <rtc_slowck_cali+144>: l32i.n a9, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00010000 */
 +
0x4008ed66 <rtc_slowck_cali+146>: l32r a8, 0x400806b8  /* 0x80000000 */
 +
0x4008ed69 <rtc_slowck_cali+149>: or a8, a9, a8  /* set bit[31] = 1 */
 +
0x4008ed6c <rtc_slowck_cali+152>: memw
 +
0x4008ed6f <rtc_slowck_cali+155>: s32i a8, a4, 0
 +
 +
0x4008ed72 <rtc_slowck_cali+158>: l32r a8, 0x40080848  /* a8 = 0x40008534, ets_delay_us */
 +
0x4008ed75 <rtc_slowck_cali+161>: callx8 a8  /* ets_delay_us(300) */
 +
 +
0x4008ed78 <rtc_slowck_cali+164>: l32r a9, 0x400879e0  /* a9 = 0x00008000 */
 +
 +
>>>>
 +
0x4008ed7b <rtc_slowck_cali+167>: memw
 +
0x4008ed7e <rtc_slowck_cali+170>: l32i.n a8, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+0x68) */
 +
 +
0x4008ed80 <rtc_slowck_cali+172>: bnone a8, a9, 0x4008ed7b <rtc_slowck_cali+167> if a8[15] is not set, then branch ---->
 +
0x4008ed83 <rtc_slowck_cali+175>: bnei a2, 2, 0x4008ed9c <rtc_slowck_cali+200>
 +
 +
0x4008ed86 <rtc_slowck_cali+178>: l32r a2, 0x4008e660  /*
 +
0x4008ed89 <rtc_slowck_cali+181>: movi a4, 0xfffffeff
 +
0x4008ed8c <rtc_slowck_cali+184>: memw
 +
0x4008ed8f <rtc_slowck_cali+187>: l32i.n a8, a2, 0
 +
0x4008ed91 <rtc_slowck_cali+189>: and a4, a8, a4
 +
0x4008ed94 <rtc_slowck_cali+192>: memw
 +
0x4008ed97 <rtc_slowck_cali+195>: s32i.n a4, a2, 0
 +
 +
0x4008ed99 <rtc_slowck_cali+197>: j 0x4008edb4 <rtc_slowck_cali+224>
 +
 +
>>>>
 +
0x4008ed9c <rtc_slowck_cali+200>: bnei a2, 1, 0x4008edb4 <rtc_slowck_cali+224>
 +
 +
0x4008ed9f <rtc_slowck_cali+203>: l32r a2, 0x4008e660  /* 0x3ff48070, read RTC_CNTL_CLK_CONF_REG */
 +
0x4008eda2 <rtc_slowck_cali+206>: movi a4, 0xfffffdff
 +
0x4008eda5 <rtc_slowck_cali+209>: memw
 +
0x4008eda8 <rtc_slowck_cali+212>: l32i a8, a2, 0
 +
0x4008edab <rtc_slowck_cali+215>: and a4, a8, a4  /* clear bit[9] */
 +
0x4008edae <rtc_slowck_cali+218>: memw
 +
0x4008edb1 <rtc_slowck_cali+221>: s32i a4, a2, 0
 +
/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
 +
/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
 +
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
 +
 +
>>>>
 +
0x4008edb4 <rtc_slowck_cali+224>: l32r a2, 0x4008ecd0  /* 0x6001f06c,  (DR_REG_BB_BASE+0x6c) */
 +
0x4008edb7 <rtc_slowck_cali+227>: memw
 +
0x4008edba <rtc_slowck_cali+230>: l32i a2, a2, 0  /* a2 = 0x00026280 = 156288 */
 +
0x4008edbd <rtc_slowck_cali+233>: call8 0x4008fb14 <rtc_get_xtal>
 +
 +
0x4008edc0 <rtc_slowck_cali+236>: mull a12, a10, a3  //a12 = 300 * p2,  a10 = 300
 +
0x4008edc3 <rtc_slowck_cali+239>: srli a10, a2, 7  // a10 = 0x4c5 = 1221
 +
0x4008edc6 <rtc_slowck_cali+242>: extui a11, a2, 20, 12  // a11 = 0
 +
0x4008edc9 <rtc_slowck_cali+245>: movi a13, 0  // a13 = 0
 +
0x4008edcc <rtc_slowck_cali+248>: slli a10, a10, 19  // a10 = 1221 * 2^19 = 640155648
 +
0x4008edcf <rtc_slowck_cali+251>: call8 0x400e7440 <__udivdi3>
 +
0x4008edd2 <rtc_slowck_cali+254>: mov.n a2, a10
 +
0x4008edd4 <rtc_slowck_cali+256>: retw.n
 +
</source>
  
 
<br><br>
 
<br><br>
第171行: 第316行:
  
 
=== Part One ===
 
=== Part One ===
 +
 +
<source lang=c>
 +
int tick_per_us = rtc_get_xtal();
 +
 +
REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, p2 << 27, RTC_CNTL_SOC_CLK_SEL_M);
 +
 +
if (p2 == 1) {
 +
    // PLL clock
 +
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 24, RTC_CNTL_PLL_BUF_WAIT_M);  // PLL wait cycles in slow_clk_rtc
 +
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M);  // XTAL wait cycles in slow_clk_rtc
 +
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);      // CK8M wait cycles in slow_clk_rtc
 +
} else if (p2 == 0) {
 +
    // XTAL clock
 +
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M);  // PLL wait cycles in slow_clk_rtc
 +
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M);  // XTAL wait cycles in slow_clk_rtc
 +
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);      // CK8M wait cycles in slow_clk_rtc
 +
    ets_update_cpu_frequency(ticks_per_us);
 +
    rtc_apb_freq_up(ticks_per_us * 1000000);
 +
} else if (p2 == 2) {
 +
    // CK8M clock
 +
    REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 25, RTC_CNTL_ROM_RAM_POWERUP_TIMER_M);
 +
    REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 16, RTC_CNTL_ROM_RAM_WAIT_TIMER_M);
 +
    REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 9, RTC_CNTL_WIFI_POWERUP_TIMER_M);
 +
    REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1, RTC_CNTL_WAIT_TIMER_M);
 +
 +
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M);  // PLL wait cycles in slow_clk_rtc
 +
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x3 << 14, RTC_CNTL_XTL_BUF_WAIT_M);  // XTAL wait cycles in slow_clk_rtc
 +
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);    // CK8M wait cycles in slow_clk_rtc
 +
    ets_update_cpu_frequency(8);
 +
    rtc_apb_freq_up(8000000);
 +
}
 +
 +
</source>
  
 
<source lang=bash>
 
<source lang=bash>
第363行: 第541行:
  
 
=== Part Two ===
 
=== Part Two ===
 +
 +
<source lang=c>
 +
rtc_uart_div_modify(0);
 +
 +
REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, 0xdd00 0000);  // clear PLL_I2C/CKGEN_I2C/RFRX_PBUS/TXRF_I2C/PVTMON/PLLA
 +
REG_CLR_BIT(SARADC_SAR_MEAS_WAIT2_REG, SARADC_FORCE_XPD_SAR_M); // 0x3 << 18
 +
 +
if (p3 != 0) {
 +
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x1 << 4);  // memories in digital core force power up in sleep
 +
} else {
 +
    REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x1 << 4);  // memories in digital core force no power up in sleep
 +
}
 +
 +
if (p4 != 0) {
 +
    REG_SET_BIT(RTC_CNTL_PWC_REG, 0x00012000);  // set BIT[13], 16
 +
    // RTC memory and Fast RTC memory force power up
 +
} else {
 +
    REG_CLR_BIT(RTC_CNTL_PWC_REG, 0x00012000);  // clear BIT[13], 16
 +
    // RTC memory and Fast RTC memory force no power up
 +
}
 +
 +
// p5 = deep_slp & 0x10, BIT[4]
 +
if (p5 != 0) {
 +
    // Power down the RTC memory and Fast RTC memory
 +
    REG_SET_BIT(RTC_CNTL_PWC_REG, 0x0000 0240);  // set BIT[9], 6
 +
    /*
 +
    * RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0;
 +
    * 1: RTC memory  PD following CPU
 +
    * 0: RTC memory PD following RTC state machine
 +
    *
 +
    * RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0
 +
    * 1: Fast RTC memory PD following CPU
 +
    * 0: fast RTC memory PD following RTC state machine
 +
    */
 +
} else {
 +
    REG_CLR_BIT(RTC_CNTL_PWC_REG, 0x0000 0240);  // clear BIT[9], 6
 +
}
 +
 +
// p6 = deep_slp & 0x8, BIT[3], PD_RTC_FAST_MEM
 +
if (p6 != 0) {
 +
    // Power down Fast Memory
 +
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
 +
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
 +
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO)
 +
} else {
 +
    // Power up fast memory
 +
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
 +
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
 +
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO)
 +
}
 +
</source>
  
 
<source lang=bash>
 
<source lang=bash>
第373行: 第602行:
 
0x4008f35a <rtc_slp_prep+406>: memw
 
0x4008f35a <rtc_slp_prep+406>: memw
 
0x4008f35d <rtc_slp_prep+409>: l32i a9, a8, 0
 
0x4008f35d <rtc_slp_prep+409>: l32i a9, a8, 0
0x4008f360 <rtc_slp_prep+412>: xor a2, a3, a2
+
0x4008f360 <rtc_slp_prep+412>: xor a2, a3, a2 /* a2 = ~p1 = 0x22ff ffff */
0x4008f363 <rtc_slp_prep+415>: and a2, a2, a9
+
0x4008f363 <rtc_slp_prep+415>: and a2, a2, a9 /* clear BIT[31], 30, 28, 27, 26, 24 */
 
0x4008f366 <rtc_slp_prep+418>: l32r a3, 0x4008bff8  /* a3 = 0x3ff4880c, SARADC_SAR_MEAS_WAIT2_REG */
 
0x4008f366 <rtc_slp_prep+418>: l32r a3, 0x4008bff8  /* a3 = 0x3ff4880c, SARADC_SAR_MEAS_WAIT2_REG */
 
0x4008f369 <rtc_slp_prep+421>: memw
 
0x4008f369 <rtc_slp_prep+421>: memw
 
0x4008f36c <rtc_slp_prep+424>: s32i.n a2, a8, 0
 
0x4008f36c <rtc_slp_prep+424>: s32i.n a2, a8, 0
 
0x4008f36e <rtc_slp_prep+426>: memw
 
0x4008f36e <rtc_slp_prep+426>: memw
 +
/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0; 1: PLL_I2C power up  otherwise power down*/
 +
/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0; 1: CKGEN_I2C power up  otherwise power down*/
 +
/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0; 1: RFRX_PBUS power up  otherwise power down*/
 +
/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0; 1: TXRF_I2C power up  otherwise power down*/
 +
/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0; 1: PVTMON power up  otherwise power down*/
 +
/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; PLLA force power up*/
  
 
0x4008f371 <rtc_slp_prep+429>: l32i.n a8, a3, 0
 
0x4008f371 <rtc_slp_prep+429>: l32i.n a8, a3, 0
第511行: 第746行:
 
0x4008f441 <rtc_slp_prep+637>: memw
 
0x4008f441 <rtc_slp_prep+637>: memw
 
0x4008f444 <rtc_slp_prep+640>: s32i.n a3, a8, 0  // Force no ISO
 
0x4008f444 <rtc_slp_prep+640>: s32i.n a3, a8, 0  // Force no ISO
 +
</source>
  
 +
<br>
 +
 +
=== Part three ===
 +
 +
<source lang=c>
 +
// p7
 +
if (deep_slp & 0x4 != 0) {
 +
    // Power down RTC memory (SLOW)
 +
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
 +
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
 +
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_SLOWMEM_FORCE_NOISO)
 +
} else {
 +
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
 +
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
 +
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_SLOWMEM_FORCE_NOISO)
 +
}
 +
 +
// p8
 +
if (deep_slp & 0x2 != 0) {
 +
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);  // enable power down rtc_peri in sleep
 +
} else {
 +
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);  // disable power down rtc_peri in sleep
 +
}
 +
 +
// p9 = up_a1 + 8 = a1 + 48 + 8
 +
if (p9 != 0) {
 +
    // enable power down wifi in sleep
 +
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
 +
} else {
 +
    // disable power down wifi in sleep
 +
    REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
 +
}
 +
 +
// p10 = up_a1 + 12 = a1 + 48 + 12
 +
if (p9 != 0) {
 +
    // SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are power down in sleep
 +
    // BIT[29:14]
 +
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x3f000000);
 +
} else {
 +
    // SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are not power down in sleep
 +
    REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x3f000000);
 +
}
 +
 +
// p11 = up_a1 + 16 = a1 + 48 + 16
 +
if (p11 != 0) {
 +
    rtc_deep_slp_conf();
 +
 +
    REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
 +
    // bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep
 +
} else {
 +
    REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
 +
    // bitpos:[31] ;default: 1'd0; SW system reset*
 +
 +
    REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
 +
    // R/W ;bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep
 +
}
 +
 +
// p12 = *(a1 + 48 + 20), p13 = *(a1 + 48 + 24) = cpu_lp_mode
 +
 +
rtc_dbias_cfg(p14, p15, p16, p17);
 +
 +
if (p13 != 0) rtc_digital_lp_mode(); // cpu_lp_mode != 0; not deep sleep
 +
 +
return;
 +
</source>
 +
 +
<source lang=c>
 
>>>>>>
 
>>>>>>
0x4008f446 <rtc_slp_prep+642>: l32i.n a3, a1, 48  /* load the 1st param into a3 = 0x0 = deep_slp & 0x4 */
+
0x4008f446 <rtc_slp_prep+642>: l32i.n a3, a1, 48  /* (a1 + 48 + 0), a3 = deep_slp & 0x4, BIT[2]  */
 
0x4008f448 <rtc_slp_prep+644>: memw
 
0x4008f448 <rtc_slp_prep+644>: memw
 
0x4008f44b <rtc_slp_prep+647>: l32i.n a4, a8, 0
 
0x4008f44b <rtc_slp_prep+647>: l32i.n a4, a8, 0
 
0x4008f44d <rtc_slp_prep+649>: beqz.n a3, 0x4008f47c <rtc_slp_prep+696> if (a3 == 0); jump to 696 --->
 
0x4008f44d <rtc_slp_prep+649>: beqz.n a3, 0x4008f47c <rtc_slp_prep+696> if (a3 == 0); jump to 696 --->
/* p1 == 0x0 */
 
  
 
>>>>> p1 Non-Zero, RTC memory power down in sleep
 
>>>>> p1 Non-Zero, RTC memory power down in sleep
第688行: 第990行:
  
 
<br><br>
 
<br><br>
 +
 +
=== Overview ===
 +
 +
<source lang=c>
 +
void rtc_slp_prep(p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15, p16, p17)
 +
{
 +
int tick_per_us = rtc_get_xtal();
 +
 +
REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, p2 << 27, RTC_CNTL_SOC_CLK_SEL_M);
 +
 +
if (p2 == 1) {
 +
// PLL clock
 +
REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 24, RTC_CNTL_PLL_BUF_WAIT_M); // PLL wait cycles in slow_clk_rtc
 +
REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M); // XTAL wait cycles in slow_clk_rtc
 +
REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M); // CK8M wait cycles in slow_clk_rtc
 +
} else if (p2 == 0) {
 +
// XTAL clock
 +
REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M); // PLL wait cycles in slow_clk_rtc
 +
REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M); // XTAL wait cycles in slow_clk_rtc
 +
REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M); // CK8M wait cycles in slow_clk_rtc
 +
ets_update_cpu_frequency(ticks_per_us);
 +
rtc_apb_freq_up(ticks_per_us * 1000000);
 +
} else if (p2 == 2) {
 +
// CK8M clock
 +
REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 25,
 +
    RTC_CNTL_ROM_RAM_POWERUP_TIMER_M);
 +
REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 16,
 +
    RTC_CNTL_ROM_RAM_WAIT_TIMER_M);
 +
REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 9,
 +
    RTC_CNTL_WIFI_POWERUP_TIMER_M);
 +
REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1, RTC_CNTL_WAIT_TIMER_M);
 +
 +
REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M); // PLL wait cycles in slow_clk_rtc
 +
REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x3 << 14, RTC_CNTL_XTL_BUF_WAIT_M); // XTAL wait cycles in slow_clk_rtc
 +
REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M); // CK8M wait cycles in slow_clk_rtc
 +
ets_update_cpu_frequency(8);
 +
rtc_apb_freq_up(8000000);
 +
}
 +
 +
rtc_uart_div_modify(0);
 +
 +
REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, 0xdd00 0000); // clear PLL_I2C/CKGEN_I2C/RFRX_PBUS/TXRF_I2C/PVTMON/PLLA
 +
REG_CLR_BIT(SARADC_SAR_MEAS_WAIT2_REG, SARADC_FORCE_XPD_SAR_M); // 0x3 << 18
 +
 +
if (p3 != 0) {
 +
REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x1 << 4); // memories in digital core force power up in sleep
 +
} else {
 +
REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x1 << 4); // memories in digital core force no power up in sleep
 +
}
 +
 +
if (p4 != 0) {
 +
REG_SET_BIT(RTC_CNTL_PWC_REG, 0x00012000); // set BIT[13], 16
 +
// RTC memory and Fast RTC memory force power up
 +
} else {
 +
REG_CLR_BIT(RTC_CNTL_PWC_REG, 0x00012000); // clear BIT[13], 16
 +
// RTC memory and Fast RTC memory force no power up
 +
}
 +
 +
// p5 = deep_slp & 0x10, BIT[4]
 +
if (p5 != 0) {
 +
// Power down the RTC memory and Fast RTC memory
 +
REG_SET_BIT(RTC_CNTL_PWC_REG, 0x0000 0240); // set BIT[9], 6
 +
/*
 +
* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0;
 +
* 1: RTC memory  PD following CPU
 +
* 0: RTC memory PD following RTC state machine
 +
*
 +
* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0
 +
* 1: Fast RTC memory PD following CPU
 +
* 0: fast RTC memory PD following RTC state machine
 +
*/
 +
} else {
 +
REG_CLR_BIT(RTC_CNTL_PWC_REG, 0x0000 0240); // clear BIT[9], 6
 +
}
 +
 +
// p6 = deep_slp & 0x8, BIT[3], PD_RTC_FAST_MEM
 +
if (p6 != 0) {
 +
// Power down Fast Memory
 +
REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
 +
REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
 +
REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO)
 +
} else {
 +
// Power up fast memory
 +
REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
 +
REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
 +
REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO)
 +
}
 +
 +
// p7
 +
if (deep_slp & 0x4 != 0) {
 +
// Power down RTC memory (SLOW)
 +
REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
 +
REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
 +
REG_CLR_BIT(RTC_CNTL_PWC_REG,
 +
    RTC_CNTL_SLOWMEM_FORCE_ISO |
 +
    RTC_CNTL_SLOWMEM_FORCE_NOISO)
 +
} else {
 +
REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
 +
REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
 +
REG_SET_BIT(RTC_CNTL_PWC_REG,
 +
    RTC_CNTL_SLOWMEM_FORCE_ISO |
 +
    RTC_CNTL_SLOWMEM_FORCE_NOISO)
 +
}
 +
 +
// p8
 +
if (deep_slp & 0x2 != 0) {
 +
REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN); // enable power down rtc_peri in sleep
 +
} else {
 +
REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN); // disable power down rtc_peri in sleep
 +
}
 +
 +
// p9 = up_a1 + 8 = a1 + 48 + 8
 +
if (p9 != 0) {
 +
// enable power down wifi in sleep
 +
REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
 +
} else {
 +
// disable power down wifi in sleep
 +
REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
 +
}
 +
 +
// p10 = up_a1 + 12 = a1 + 48 + 12
 +
if (p9 != 0) {
 +
// SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are power down in sleep
 +
// BIT[29:14]
 +
REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x3f000000);
 +
} else {
 +
// SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are not power down in sleep
 +
REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x3f000000);
 +
}
 +
 +
// p11 = up_a1 + 16 = a1 + 48 + 16
 +
if (p11 != 0) {
 +
rtc_deep_slp_conf();
 +
 +
REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
 +
// bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep
 +
} else {
 +
REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
 +
// bitpos:[31] ;default: 1'd0; SW system reset*
 +
 +
REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
 +
// R/W ;bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep
 +
}
 +
 +
// p12 = *(a1 + 48 + 20), p13 = *(a1 + 48 + 24) = cpu_lp_mode
 +
 +
rtc_dbias_cfg(p14, p15, p16, p17);
 +
 +
if (p13 != 0)
 +
rtc_digital_lp_mode(); // cpu_lp_mode != 0; not deep sleep
 +
 +
return;
 +
}
 +
 +
void rtc_deep_slp_conf()
 +
{
 +
    REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, 0x00003000);  // clear DG_PAD_FORCE_ISO and DG_PAD_FORCE_NOISO
 +
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x80000000);  // enable power down digital core in sleep
 +
 +
    REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x00180000);  // clear DG_WRAP_FORCE_PU and DG_WRAP_FORCE_PD
 +
 +
    REG_SET_BITS(RTC_CNTL_TIMER4_REG, 0x0200 0000, 0xfe000000);  // DG_WRAP_POWERUP_TIMER = 0x1
 +
    REG_SET_BITS(RTC_CNTL_TIMER4_REG, 0x0001 0000, 0x01ff0000);  // DG_WRAP_WAIT_TIMER = 0x1
 +
}
 +
 +
void rtc_dbias_cfg(p1, p2, p3, p4)
 +
{
 +
    REG_SET_BITS(RTC_CNTL_REG, p4 << 22, RTC_CNTL_DBIAS_SLP_M);      // RTC_DBIAS during sleep
 +
    REG_SET_BITS(RTC_CNTL_REG, p1 << 11, RTC_CNTL_DIG_DBIAS_WAK_M);  // DIG_REG_DBIAS during wakeup
 +
    REG_SET_BITS(RTC_CNTL_REG, p2 << 8, RTC_CNTL_DIG_DBIAS_SLP_M);  // DIG_REG_DBIAS during sleep
 +
}
 +
 +
void rtc_digital_lp_mode()
 +
{
 +
    REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, 0x05550000);    // iram4 ~ iram0 and rom are force iso
 +
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x0000aaa0);    // iram4 ~ iram0 and rom are force power down
 +
 +
    REG_WRITE(DPORT_PERIP_CLK_EN_REG, 0x0);
 +
    REG_WRITE(DPORT_WIFI_CLK_EN_REG, 0x0);
 +
    REG_CLR_BIT(DPORT_WIFI_CLK_EN_REG, 0x40);      // seems like to enable the MAC clk of wifi ??
 +
 +
    REG_SET_BIT(DPORT_WIFI_RST_EN_REG, DPORT_MAC_RST);          // wifi mac reset
 +
    REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);  // wifi force iso
 +
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);  // wifi power down
 +
    REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, 0x10000000, RTC_CNTL_SOC_CLK_SEL_M);  // select the CK8K
 +
    REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, 0x00001500, 0x00003f00);      // crystall, BB_PLL, BB_PLL_I2C force power down
 +
    REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PD)  // bias core force power down
 +
    REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);  // bias i2c force power down
 +
}
 +
</source>
 +
 +
<br>
  
 
== rtc_deep_slp_conf ==
 
== rtc_deep_slp_conf ==
 +
 +
<source lang=c>
 +
void rtc_deep_slp_conf()
 +
{
 +
  REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, 0x00003000);  // clear DG_PAD_FORCE_ISO and DG_PAD_FORCE_NOISO
 +
  REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x80000000);  // enable power down digital core in sleep
 +
 +
  REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x00180000);  // clear DG_WRAP_FORCE_PU and DG_WRAP_FORCE_PD
 +
 +
  REG_SET_BITS(RTC_CNTL_TIMER4_REG, 0x0200 0000, 0xfe000000);  // DG_WRAP_POWERUP_TIMER = 0x1
 +
  REG_SET_BITS(RTC_CNTL_TIMER4_REG, 0x0001 0000, 0x01ff0000);  // DG_WRAP_WAIT_TIMER = 0x1
 +
}
 +
</source>
  
 
<source lang=c>
 
<source lang=c>
第705行: 第1,212行:
 
/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1; digital pad force no ISO*/
 
/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1; digital pad force no ISO*/
  
0x4008f070 <rtc_deep_slp_conf+28>: l32i.n a10, a9, 0
+
0x4008f070 <rtc_deep_slp_conf+28>: l32i.n a10, a9, 0 /* read RTC_CNTL_DIG_PWC_REG */
 
0x4008f072 <rtc_deep_slp_conf+30>: l32r a8, 0x400806ec  /* a8 = 0x80000000 */
 
0x4008f072 <rtc_deep_slp_conf+30>: l32r a8, 0x400806ec  /* a8 = 0x80000000 */
 
0x4008f075 <rtc_deep_slp_conf+33>: or a8, a10, a8  /* set BIT[31] */
 
0x4008f075 <rtc_deep_slp_conf+33>: or a8, a10, a8  /* set BIT[31] */
第713行: 第1,220行:
 
/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0; enable power down digital core in sleep*/
 
/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0; enable power down digital core in sleep*/
  
0x4008f080 <rtc_deep_slp_conf+44>: l32i.n a11, a9, 0
+
0x4008f080 <rtc_deep_slp_conf+44>: l32i.n a11, a9, 0 /* read RTC_CNTL_DIG_PWC_REG */
 
0x4008f082 <rtc_deep_slp_conf+46>: l32r a10, 0x4008f048  /* a10 = 0xffe7ffff */
 
0x4008f082 <rtc_deep_slp_conf+46>: l32r a10, 0x4008f048  /* a10 = 0xffe7ffff */
 
0x4008f085 <rtc_deep_slp_conf+49>: l32r a8, 0x4008f04c  /* a8 = 0x3ff48028, RTC_CNTL_TIMER4_REG */
 
0x4008f085 <rtc_deep_slp_conf+49>: l32r a8, 0x4008f04c  /* a8 = 0x3ff48028, RTC_CNTL_TIMER4_REG */
第723行: 第1,230行:
 
/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0; digital core force power down*/
 
/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0; digital core force power down*/
  
0x4008f093 <rtc_deep_slp_conf+63>: l32i.n a10, a8, 0
+
0x4008f093 <rtc_deep_slp_conf+63>: l32i.n a10, a8, 0 /* read RTC_CNTL_TIMER4_REG */
 
0x4008f095 <rtc_deep_slp_conf+65>: l32r a9, 0x4008f050  /* a9 = 0x01ffffff */
 
0x4008f095 <rtc_deep_slp_conf+65>: l32r a9, 0x4008f050  /* a9 = 0x01ffffff */
 
0x4008f098 <rtc_deep_slp_conf+68>: and a9, a10, a9  /* clear BIT[31:25] */
 
0x4008f098 <rtc_deep_slp_conf+68>: and a9, a10, a9  /* clear BIT[31:25] */
第733行: 第1,240行:
 
/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
 
/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
  
0x4008f0a9 <rtc_deep_slp_conf+85>: l32i.n a10, a8, 0
+
0x4008f0a9 <rtc_deep_slp_conf+85>: l32i.n a10, a8, 0 /* read RTC_CNTL_TIMER4_REG */
 
0x4008f0ab <rtc_deep_slp_conf+87>: l32r a9, 0x4008ba60  /* a9 = 0xfe00ffff */
 
0x4008f0ab <rtc_deep_slp_conf+87>: l32r a9, 0x4008ba60  /* a9 = 0xfe00ffff */
 
0x4008f0ae <rtc_deep_slp_conf+90>: and a9, a10, a9  /* clear BIT[24:16] */
 
0x4008f0ae <rtc_deep_slp_conf+90>: and a9, a10, a9  /* clear BIT[24:16] */
第743行: 第1,250行:
  
 
0x4008f0bc <rtc_deep_slp_conf+104>: retw.n
 
0x4008f0bc <rtc_deep_slp_conf+104>: retw.n
 +
</source>
 +
 +
<br>
 +
 +
== rtc_dbias_cfg ==
 +
 +
<source lang=c>
 +
void rtc_dbias_cfg(p1, p2, p3, p4)
 +
{
 +
    REG_SET_BITS(RTC_CNTL_REG, p4 << 22, RTC_CNTL_DBIAS_SLP_M);      // RTC_DBIAS during sleep
 +
    REG_SET_BITS(RTC_CNTL_REG, p1 << 11, RTC_CNTL_DIG_DBIAS_WAK_M);  // DIG_REG_DBIAS during wakeup
 +
    REG_SET_BITS(RTC_CNTL_REG, p2 << 8, RTC_CNTL_DIG_DBIAS_SLP_M);  // DIG_REG_DBIAS during sleep
 +
}
 +
</source>
 +
 +
<source lang=c>
 +
  0x4008fe30 <rtc_dbias_cfg>: entry a1, 32
 +
  0x4008fe33 <rtc_dbias_cfg+3>: l32r a8, 0x4008e58c  /* a8 = 0x3ff4807c, RTC_CNTL_REG */
 +
  0x4008fe36 <rtc_dbias_cfg+6>: l32r a11, 0x4008e824  /* a11 = 0xfe3fffff */
 +
  0x4008fe39 <rtc_dbias_cfg+9>: memw
 +
  0x4008fe3c <rtc_dbias_cfg+12>: l32i.n a9, a8, 0
 +
  0x4008fe3e <rtc_dbias_cfg+14>: extui a5, a5, 0, 3  /* p4[2:0] */
 +
  0x4008fe41 <rtc_dbias_cfg+17>: slli a10, a5, 22  /* a10 = p4[2:0] << 22 */
 +
  0x4008fe44 <rtc_dbias_cfg+20>: and a9, a9, a11
 +
  0x4008fe47 <rtc_dbias_cfg+23>: or a9, a10, a9
 +
  0x4008fe4a <rtc_dbias_cfg+26>: memw
 +
  0x4008fe4d <rtc_dbias_cfg+29>: s32i.n a9, a8, 0
 +
  0x4008fe4f <rtc_dbias_cfg+31>: memw
 +
  /* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4; RTC_DBIAS during sleep*/
 +
 +
  0x4008fe52 <rtc_dbias_cfg+34>: l32i.n a9, a8, 0  /* read RTC_CNTL_REG */
 +
  0x4008fe54 <rtc_dbias_cfg+36>: l32r a11, 0x4008e82c  /* a11 = 0xffffc7ff */
 +
  0x4008fe57 <rtc_dbias_cfg+39>: extui a2, a2, 0, 3  /* p1[2:0] */
 +
  0x4008fe5a <rtc_dbias_cfg+42>: slli a10, a2, 11  /* a10 = p1[2:0] << 11 */
 +
  0x4008fe5d <rtc_dbias_cfg+45>: and a9, a9, a11
 +
  0x4008fe60 <rtc_dbias_cfg+48>: or a9, a10, a9
 +
  0x4008fe63 <rtc_dbias_cfg+51>: memw
 +
  0x4008fe66 <rtc_dbias_cfg+54>: s32i.n a9, a8, 0
 +
  0x4008fe68 <rtc_dbias_cfg+56>: memw
 +
  /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4; DIG_REG_DBIAS during wakeup*/
 +
 +
  0x4008fe6b <rtc_dbias_cfg+59>: l32i.n a9, a8, 0  /* read RTC_CNTL_REG */
 +
  0x4008fe6d <rtc_dbias_cfg+61>: extui a3, a3, 0, 3  /* p2[2:0] */
 +
  0x4008fe70 <rtc_dbias_cfg+64>: movi a11, 0xfffff8ff
 +
  0x4008fe73 <rtc_dbias_cfg+67>: slli a10, a3, 8  /* a10 = p2[2:0] << 8 */
 +
  0x4008fe76 <rtc_dbias_cfg+70>: and a9, a9, a11
 +
  0x4008fe79 <rtc_dbias_cfg+73>: or a9, a10, a9
 +
  0x4008fe7c <rtc_dbias_cfg+76>: memw
 +
  0x4008fe7f <rtc_dbias_cfg+79>: s32i.n a9, a8, 0
 +
  /* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4; DIG_REG_DBIAS during sleep*/
 +
 +
  0x4008fe81 <rtc_dbias_cfg+81>: retw.n
 
</source>
 
</source>
  
第750行: 第1,309行:
  
 
<source lang=c>
 
<source lang=c>
REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, 0x05550000);    // iram4 ~ iram0 and rom are force iso
+
void rtc_digital_lp_mode()
REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x0000aaa0);    // iram4 ~ iram0 and rom are force power down
+
{
 +
    REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, 0x05550000);    // iram4 ~ iram0 and rom are force iso
 +
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x0000aaa0);    // iram4 ~ iram0 and rom are force power down
  
REG_WRITE(DPORT_PERIP_CLK_EN_REG, 0x0);
+
    REG_WRITE(DPORT_PERIP_CLK_EN_REG, 0x0);
REG_WRITE(DPORT_WIFI_CLK_EN_REG, 0x0);
+
    REG_WRITE(DPORT_WIFI_CLK_EN_REG, 0x0);
REG_CLR_BIT(DPORT_WIFI_CLK_EN_REG, 0x40);      // seems like to enable the MAC clk of wifi ??
+
    REG_CLR_BIT(DPORT_WIFI_CLK_EN_REG, 0x40);      // seems like to enable the MAC clk of wifi ??
  
REG_SET_BIT(DPORT_WIFI_RST_EN_REG, DPORT_MAC_RST);          // wifi mac reset
+
    REG_SET_BIT(DPORT_WIFI_RST_EN_REG, DPORT_MAC_RST);          // wifi mac reset
REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);  // wifi force iso
+
    REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);  // wifi force iso
REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);  // wifi power down
+
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);  // wifi power down
REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, 0x10000000, RTC_CNTL_SOC_CLK_SEL_M);  // select the CK8K
+
    REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, 0x10000000, RTC_CNTL_SOC_CLK_SEL_M);  // select the CK8K
REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, 0x00001500, 0x00003f00);      // crystall, BB_PLL, BB_PLL_I2C force power down
+
    REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, 0x00001500, 0x00003f00);      // crystall, BB_PLL, BB_PLL_I2C force power down
REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PD)  // bias core force power down
+
    REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PD)  // bias core force power down
REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);  // bias i2c force power down
+
    REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);  // bias i2c force power down
 +
}
 
</source>
 
</source>
  

2016年12月15日 (四) 19:50的最后版本

目录

[编辑] 1 rtc_get_xtal

RTC_CNTL_STORE5_REG is the External Xtal Frequency Register

0x4008fa70 <rtc_get_xtal>: entry	a1, 32
0x4008fa73 <rtc_get_xtal+3>: l32r	a11, 0x4008fa44  /* a11 = *(0x4008fa44) = 0x3ff480b0, RTC_CNTL_STORE4_REG */
0x4008fa76 <rtc_get_xtal+6>: l32r	a9, 0x4008fa68   /* a9 = *(0x4008fa68) = 0x3ff480b4, RTC_CNTL_STORE5_REG */
0x4008fa79 <rtc_get_xtal+9>: memw
0x4008fa7c <rtc_get_xtal+12>: l32i.n	a8, a11, 0   /* a8 = *(0x3ff480b0) = 0x00280028, read RTC_CNTL_STORE4_REG */
0x4008fa7e <rtc_get_xtal+14>: memw
0x4008fa81 <rtc_get_xtal+17>: l32i.n	a9, a9, 0    /* a9 = *(0x3ff480b4) = 0x4c4b4c4b, read RTC_CNTL_STORE5_REG */

0x4008fa83 <rtc_get_xtal+19>: extui	a10, a8, 0, 16    /* a10 = RTC_CNTL_STORE4_REG[15:0] */
0x4008fa86 <rtc_get_xtal+22>: extui	a12, a8, 16, 16   /* a12 = RTC_CNTL_STORE4_REG[31:16] */
0x4008fa89 <rtc_get_xtal+25>: bne	a10, a12, 0x4008fa95  /* branch; if (a10 != a12) */

0x4008fa8c <rtc_get_xtal+28>: mov.n	a2, a10             /* a2 = a10 = 0x28, a2 hold the return value */

0x4008fa8e <rtc_get_xtal+30>: addi.n	a8, a8, -1          /* a8 = RTC_CNTL_STORE4_REG - 1 */
0x4008fa90 <rtc_get_xtal+32>: movi.n	a10, -3             /* a10 = 0xFFFF FFFD */
0x4008fa92 <rtc_get_xtal+34>: bgeu	a10, a8, 0x4008fac2 /* branch to return; if (0xFFFF FFFD >= a8) */

0x4008fa95 <rtc_get_xtal+37>: extui	a8, a9, 0, 16       /* a8 = RTC_CNTL_STORE5_REG[15:0] */
0x4008fa98 <rtc_get_xtal+40>: extui	a10, a9, 16, 16     /* a10 = RTC_CNTL_STORE5_REG[31:16] */
0x4008fa9b <rtc_get_xtal+43>: bne	a8, a10, 0x4008fac2     /* branch; if (a8 != a10) */

0x4008fa9e <rtc_get_xtal+46>: addi.n	a9, a9, -1          /* a9 = RTC_CNTL_STORE5_REG - 1 */
0x4008faa0 <rtc_get_xtal+48>: movi.n	a10, -3             /* a10 = 0xFFFF FFFD */
0x4008faa2 <rtc_get_xtal+50>: bltu	a10, a9, 0x4008fac2 /* branch; if (0xFFFF FFFD < a9) */

0x4008faa5 <rtc_get_xtal+53>: l32r	a2, 0x4008fa6c      /* a2 = *(0x4008fa6c) = 0x01c9c37f */
0x4008faa8 <rtc_get_xtal+56>: slli	a8, a8, 12          /* a8 = RTC_CNTL_STORE5_REG[15:0] << 12 */
0x4008faab <rtc_get_xtal+59>: bgeu	a2, a8, 0x4008fab8  /* branch; if (a2 >= a8) */

0x4008faae <rtc_get_xtal+62>: l32r	a8, 0x4008fa60      /* a8 = *(0x4008fa60) = 0x00280028 */
0x4008fab1 <rtc_get_xtal+65>: movi.n	a2, 40
0x4008fab3 <rtc_get_xtal+67>: j	0x4008fabd

0x4008fab6 <rtc_get_xtal+70>: 0x0000   <<--- Seems like this the gdb/openocd-esp32 bug

0x4008fab8 <rtc_get_xtal+72>:	l32r	a8, 0x4008fa64  /* a8 = *(0x4008fa64) = 0x001a001a */
0x4008fabb <rtc_get_xtal+75>:	movi.n	a2, 26

0x4008fabd <rtc_get_xtal+77>:	memw
0x4008fac0 <rtc_get_xtal+80>:	s32i.n	a8, a11, 0
0x4008fac2 <rtc_get_xtal+82>:	retw.n


So:

 uint32_t rtc_get_xtal();




[编辑] 2 rtc_slowck_cali

p1:

typedef enum {
    CALI_RTC_MUX = 0,
    CALI_8MD256 = 1,
    CALI_32K_XTAL = 2
} cali_clk_t;
0x4008ecd4 <rtc_slowck_cali>: entry	a1, 32
0x4008ecd7 <rtc_slowck_cali+3>: bnei	a2, 2, 0x4008ecf1 <rtc_slowck_cali+29>

/* p1 == 2 */
0x4008ecda <rtc_slowck_cali+6>: l32r	a4, 0x4008e660  /* 0x3ff48070, read RTC_CNTL_CLK_CONF_REG */
0x4008ecdd <rtc_slowck_cali+9>: movi	a8, 0x100
0x4008ece0 <rtc_slowck_cali+12>: memw
0x4008ece3 <rtc_slowck_cali+15>: l32i.n	a9, a4, 0
0x4008ece5 <rtc_slowck_cali+17>: or	a8, a9, a8  /* set bit[8] */
0x4008ece8 <rtc_slowck_cali+20>: memw
0x4008eceb <rtc_slowck_cali+23>: s32i.n	a8, a4, 0
/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);

0x4008eced <rtc_slowck_cali+25>: j	0x4008ed09 <rtc_slowck_cali+53>

0x4008ecef <rtc_slowck_cali+27>: 0x0000

>>>>
0x4008ecf1 <rtc_slowck_cali+29>: bnei	a2, 1, 0x4008ed09 <rtc_slowck_cali+53>

/* p1 == 1 */
0x4008ecf4 <rtc_slowck_cali+32>: l32r	a4, 0x4008e660  /* 0x3ff48070, read RTC_CNTL_CLK_CONF_REG */
0x4008ecf7 <rtc_slowck_cali+35>: movi	a8, 0x200
0x4008ecfa <rtc_slowck_cali+38>: memw
0x4008ecfd <rtc_slowck_cali+41>: l32i	a9, a4, 0
0x4008ed00 <rtc_slowck_cali+44>: or	a8, a9, a8  /* set bit[9] */
0x4008ed03 <rtc_slowck_cali+47>: memw
0x4008ed06 <rtc_slowck_cali+50>: s32i	a8, a4, 0
/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);

>>>>  /* p1 == 0 */
0x4008ed09 <rtc_slowck_cali+53>: l32r	a4, 0x4008ecc4  /* 0x6001f068 */
0x4008ed0c <rtc_slowck_cali+56>: l32r	a8, 0x4008ecc8  /* 0xffff9fff */
0x4008ed0f <rtc_slowck_cali+59>: memw
0x4008ed12 <rtc_slowck_cali+62>: l32i.n	a10, a4, 0    /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00013000 */
0x4008ed14 <rtc_slowck_cali+64>: extui	a9, a2, 0, 2
0x4008ed17 <rtc_slowck_cali+67>: slli	a9, a9, 13
0x4008ed1a <rtc_slowck_cali+70>: and	a8, a10, a8
0x4008ed1d <rtc_slowck_cali+73>: or	a8, a9, a8    /* clear and set bit[14:13] */
0x4008ed20 <rtc_slowck_cali+76>: memw
0x4008ed23 <rtc_slowck_cali+79>: s32i.n	a8, a4, 0
0x4008ed25 <rtc_slowck_cali+81>: memw

0x4008ed28 <rtc_slowck_cali+84>: l32i.n	a9, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00011000 */
0x4008ed2a <rtc_slowck_cali+86>: l32r	a8, 0x40087370  /* 0xffffefff */
0x4008ed2d <rtc_slowck_cali+89>: and	a8, a9, a8  /* clear bit[12] */
0x4008ed30 <rtc_slowck_cali+92>: memw
0x4008ed33 <rtc_slowck_cali+95>: s32i.n	a8, a4, 0
0x4008ed35 <rtc_slowck_cali+97>: memw

0x4008ed38 <rtc_slowck_cali+100>: l32i.n	a10, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00010000 */
0x4008ed3a <rtc_slowck_cali+102>: l32r	a8, 0x4008eccc  /* 0x8000ffff */
0x4008ed3d <rtc_slowck_cali+105>: extui	a9, a3, 0, 15  /* p2[15:0] */
0x4008ed40 <rtc_slowck_cali+108>: slli	a9, a9, 16
0x4008ed43 <rtc_slowck_cali+111>: and	a8, a10, a8
0x4008ed46 <rtc_slowck_cali+114>: or	a8, a9, a8  /* clear and set bit[30:16] */
0x4008ed49 <rtc_slowck_cali+117>: memw
0x4008ed4c <rtc_slowck_cali+120>: s32i.n	a8, a4, 0
0x4008ed4e <rtc_slowck_cali+122>: memw

0x4008ed51 <rtc_slowck_cali+125>: l32i.n	a9, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00010000 */
0x4008ed53 <rtc_slowck_cali+127>: l32r	a8, 0x400806f4  /* 0x7fffffff */
0x4008ed56 <rtc_slowck_cali+130>: movi	a10, 0x12c
0x4008ed59 <rtc_slowck_cali+133>: and	a8, a9, a8  /* clear bit[31] */
0x4008ed5c <rtc_slowck_cali+136>: memw
0x4008ed5f <rtc_slowck_cali+139>: s32i.n	a8, a4, 0
0x4008ed61 <rtc_slowck_cali+141>: memw

0x4008ed64 <rtc_slowck_cali+144>: l32i.n	a9, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+68) = 0x00010000 */
0x4008ed66 <rtc_slowck_cali+146>: l32r	a8, 0x400806b8  /* 0x80000000 */
0x4008ed69 <rtc_slowck_cali+149>: or	a8, a9, a8  /* set bit[31] = 1 */
0x4008ed6c <rtc_slowck_cali+152>: memw
0x4008ed6f <rtc_slowck_cali+155>: s32i	a8, a4, 0

0x4008ed72 <rtc_slowck_cali+158>: l32r	a8, 0x40080848  /* a8 = 0x40008534, ets_delay_us */
0x4008ed75 <rtc_slowck_cali+161>: callx8	a8  /* ets_delay_us(300) */

0x4008ed78 <rtc_slowck_cali+164>: l32r	a9, 0x400879e0  /* a9 = 0x00008000 */

>>>>
0x4008ed7b <rtc_slowck_cali+167>: memw
0x4008ed7e <rtc_slowck_cali+170>: l32i.n	a8, a4, 0  /* read 0x6001f068 (DR_REG_BB_BASE+0x68) */

0x4008ed80 <rtc_slowck_cali+172>: bnone	a8, a9, 0x4008ed7b <rtc_slowck_cali+167> if a8[15] is not set, then branch ---->
0x4008ed83 <rtc_slowck_cali+175>: bnei	a2, 2, 0x4008ed9c <rtc_slowck_cali+200>

0x4008ed86 <rtc_slowck_cali+178>: l32r	a2, 0x4008e660  /* 
0x4008ed89 <rtc_slowck_cali+181>: movi	a4, 0xfffffeff
0x4008ed8c <rtc_slowck_cali+184>: memw
0x4008ed8f <rtc_slowck_cali+187>: l32i.n	a8, a2, 0
0x4008ed91 <rtc_slowck_cali+189>: and	a4, a8, a4
0x4008ed94 <rtc_slowck_cali+192>: memw
0x4008ed97 <rtc_slowck_cali+195>: s32i.n	a4, a2, 0

0x4008ed99 <rtc_slowck_cali+197>: j	0x4008edb4 <rtc_slowck_cali+224>

>>>>
0x4008ed9c <rtc_slowck_cali+200>: bnei	a2, 1, 0x4008edb4 <rtc_slowck_cali+224>

0x4008ed9f <rtc_slowck_cali+203>: l32r	a2, 0x4008e660  /* 0x3ff48070, read RTC_CNTL_CLK_CONF_REG */
0x4008eda2 <rtc_slowck_cali+206>: movi	a4, 0xfffffdff
0x4008eda5 <rtc_slowck_cali+209>: memw
0x4008eda8 <rtc_slowck_cali+212>: l32i	a8, a2, 0
0x4008edab <rtc_slowck_cali+215>: and	a4, a8, a4  /* clear bit[9] */
0x4008edae <rtc_slowck_cali+218>: memw
0x4008edb1 <rtc_slowck_cali+221>: s32i	a4, a2, 0
/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);

>>>>
0x4008edb4 <rtc_slowck_cali+224>: l32r	a2, 0x4008ecd0  /* 0x6001f06c,  (DR_REG_BB_BASE+0x6c) */
0x4008edb7 <rtc_slowck_cali+227>: memw
0x4008edba <rtc_slowck_cali+230>: l32i	a2, a2, 0  /* a2 = 0x00026280 = 156288 */
0x4008edbd <rtc_slowck_cali+233>: call8	0x4008fb14 <rtc_get_xtal>

0x4008edc0 <rtc_slowck_cali+236>: mull	a12, a10, a3  //a12 = 300 * p2,  a10 = 300
0x4008edc3 <rtc_slowck_cali+239>: srli	a10, a2, 7  // a10 = 0x4c5 = 1221
0x4008edc6 <rtc_slowck_cali+242>: extui	a11, a2, 20, 12  // a11 = 0
0x4008edc9 <rtc_slowck_cali+245>: movi	a13, 0  // a13 = 0
0x4008edcc <rtc_slowck_cali+248>: slli	a10, a10, 19  // a10 = 1221 * 2^19 = 640155648
0x4008edcf <rtc_slowck_cali+251>: call8	0x400e7440 <__udivdi3>
0x4008edd2 <rtc_slowck_cali+254>: mov.n	a2, a10
0x4008edd4 <rtc_slowck_cali+256>: retw.n



[编辑] 3 rtc_slp_prep_lite

#define DEEP_SLEEP_PD_NORMAL         BIT(0)   /* Base deep sleep mode */
#define DEEP_SLEEP_PD_RTC_PERIPH     BIT(1)   /* Power down RTC peripherals */
#define DEEP_SLEEP_PD_RTC_SLOW_MEM   BIT(2)   /* Power down RTC SLOW memory */
#define DEEP_SLEEP_PD_RTC_FAST_MEM   BIT(3)   /* Power down RTC FAST memory */

/*
 * @brief Prepare for entering sleep mode
 * @param deep_slp   DEEP_SLEEP_PD_ flags combined with OR (DEEP_SLEEP_PD_NORMAL must be included)
 * @param cpu_lp_mode  for deep sleep, should be 0
 */
void rtc_slp_prep_lite(uint32_t deep_slp, uint32_t cpu_lp_mode);


0x4008f5f8 <rtc_slp_prep_lite>: entry	a1, 80
0x4008f5fb <rtc_slp_prep_lite+3>: movi.n	a9, 4         /* a9 = 4 */
0x4008f5fd <rtc_slp_prep_lite+5>: movi.n	a13, 0        /* a13 = 0 */
0x4008f5ff <rtc_slp_prep_lite+7>: mov.n	a10, a9       /* a10 = 4 */
0x4008f601 <rtc_slp_prep_lite+9>: movnez	a10, a13, a3  /* a10 = 0 = a13, if (a3 != 0) */
0x4008f604 <rtc_slp_prep_lite+12>: movi.n	a8, 2         /* a8 = 2 */
0x4008f606 <rtc_slp_prep_lite+14>: mov.n	a11, a13      /* a11 = 0 = a13 */
0x4008f608 <rtc_slp_prep_lite+16>: extui	a12, a2, 0, 1 /* a12 = a2[0] */
0x4008f60b <rtc_slp_prep_lite+19>: movnez	a11, a8, a3   /* a11 = 2 = a8, if (a3 != 0) */
// if (a3 != 0), then: a10 = 0, a11 = 2
// if (a3 == 0), then: a10 = 4, a11 = 0

0x4008f60e <rtc_slp_prep_lite+22>: and	a9, a2, a9    /* a9 = a2 & 0x4, a2 is the 1st param deep_slp */
0x4008f611 <rtc_slp_prep_lite+25>: and	a8, a2, a8    /* a8 = a2 & 0x2 */

0x4008f614 <rtc_slp_prep_lite+28>: s32i.n	a10, a1, 28  // if (a3 == 0)  *(a1 + 28) = 4  OR *(a1 + 28) = 0

0x4008f616 <rtc_slp_prep_lite+30>: movi.n	a14, 16
0x4008f618 <rtc_slp_prep_lite+32>: l32r	a10, 0x4008f5f4  /* a10 = *(0x4008f5f4 ) = 0xdd000000 */
0x4008f61b <rtc_slp_prep_lite+35>: movi.n	a15, 8
0x4008f61d <rtc_slp_prep_lite+37>: s32i.n	a12, a1, 16  // *(a1 + 16) = deep_slp[0]

0x4008f61f <rtc_slp_prep_lite+39>: s32i.n	a9, a1, 0  // *(a1 + 0) = deep_slp & 0x4
0x4008f621 <rtc_slp_prep_lite+41>: s32i.n	a8, a1, 4  // *(a1 + 4) = deep_slp & 0x2
0x4008f623 <rtc_slp_prep_lite+43>: s32i.n	a13, a1, 8  // *(a1 + 8) = 0
0x4008f625 <rtc_slp_prep_lite+45>: s32i.n	a13, a1, 12  // *(a1 + 12) = 0    // *(a1 + 16) = deep_slp[0]
0x4008f627 <rtc_slp_prep_lite+47>: s32i.n	a13, a1, 20  // *(a1 + 20) = 0
0x4008f629 <rtc_slp_prep_lite+49>: s32i.n	a3, a1, 24  // *(a1 + 24) = a3, cpu_lp_mode
0x4008f62b <rtc_slp_prep_lite+51>: s32i.n	a13, a1, 32  // *(a1 + 32) = 0
0x4008f62d <rtc_slp_prep_lite+53>: s32i.n	a13, a1, 36  // *(a1 + 36) = 0
0x4008f62f <rtc_slp_prep_lite+55>: s32i.n	a13, a1, 40  // *(a1 + 40) = 0

0x4008f631 <rtc_slp_prep_lite+57>: mov.n	a12, a13  // a12 = 0    a13 = 0
0x4008f633 <rtc_slp_prep_lite+59>: and	a14, a2, a14  // a14 = deep_slp & 0x10
0x4008f636 <rtc_slp_prep_lite+62>: and	a15, a2, a15  // a15 = deep_slp & 0x8
0x4008f639 <rtc_slp_prep_lite+65>: call8	0x4008f248 <rtc_slp_prep>
0x4008f63c <rtc_slp_prep_lite+68>: retw.n


cpu_lp_mode == 0 (deep sleep), the parameters of rtc_slp_prep()
* 1st param, a10 = 0xdd000000
* 2nd param, a11 = 0  /* SOC clock sel. 0: XTAL  1: PLL  2: CK8M  3: APLL */       <-----------
* 3rd param, a12 = 0  /* 1: memories in digital core force no PD in sleep; 0: memories in digital core force PD in sleep */
* 4th param, a13 = 0  /* 1: Slow and Fast RTC memory force power up; 0: clear */
* 5th param, a14 = deep_slp & 0x10  /* 1: Power down the RTC memory and Fast RTC memory; 0: clear */
* 6th param, a15 = deep_slp & 0x8  /* 0: RTC Fast Memory not Power down; 1: RTC Fast Memory Power down in sleep */

*(a1 + 0) = deep_slp & 0x4  /* 0: RTC memory not power down in sleep; 1: RTC memory power down in sleep */
*(a1 + 4) = deep_slp & 0x2  /* 0: RTC_PERI not power down; 1: RTC_PERI power down in sleep */
*(a1 + 8) = 0  /* 0: wifi not power down in sleep, 1: wifi power down in sleep */
*(a1 + 12) = 0  /* 0: SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are not power down in sleep;
                                1: SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are power down in sleep */
*(a1 + 16) = deep_slp[0]  /* 0: BIAS_SLEEP force sleep; 1: BIAS_SLEEP force no sleep */
*(a1 + 20) = 0
*(a1 + 24) = a3, cpu_lp_mode
*(a1 + 28) = 4
*(a1 + 32) = 0
*(a1 + 36) = 0
*(a1 + 40) = 0


4th param:

  • ==0: RTC memory and Fast RTC memory force power up clear
  •  !=0: RTC memory and Fast RTC memory force power up set */


cpu_lp_mode != 0, the parameters of rtc_slp_prep()
  • 1st param, a10 = 0xdd000000
  • 2nd param, a11 = 2 <-----------
  • 3rd param, a12 = 0
  • 4th param, a13 = 0
  • 5th param, a14 = deep_slp & 0x10
  • 6th param, a15 = deep_slp & 0x8
  • (a1 + 0) = deep_slp & 0x4
  • (a1 + 4) = deep_slp & 0x2
  • (a1 + 8) = 0
  • (a1 + 12) = 0
  • (a1 + 16) = deep_slp[0]
  • (a1 + 20) = 0
  • (a1 + 24) = a3, cpu_lp_mode
  • (a1 + 28) = 0 <--------------
  • (a1 + 32) = 0
  • (a1 + 36) = 0
  • (a1 + 40) = 0



[编辑] 4 rtc_slp_prep

[编辑] 4.1 Part One

int tick_per_us = rtc_get_xtal();

REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, p2 << 27, RTC_CNTL_SOC_CLK_SEL_M);

if (p2 == 1) {
    // PLL clock
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 24, RTC_CNTL_PLL_BUF_WAIT_M);  // PLL wait cycles in slow_clk_rtc
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M);  // XTAL wait cycles in slow_clk_rtc
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);      // CK8M wait cycles in slow_clk_rtc
} else if (p2 == 0) {
    // XTAL clock
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M);   // PLL wait cycles in slow_clk_rtc
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M);  // XTAL wait cycles in slow_clk_rtc
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);      // CK8M wait cycles in slow_clk_rtc
    ets_update_cpu_frequency(ticks_per_us);
    rtc_apb_freq_up(ticks_per_us * 1000000);
} else if (p2 == 2) {
    // CK8M clock
    REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 25, RTC_CNTL_ROM_RAM_POWERUP_TIMER_M);
    REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 16, RTC_CNTL_ROM_RAM_WAIT_TIMER_M);
    REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 9, RTC_CNTL_WIFI_POWERUP_TIMER_M);
    REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1, RTC_CNTL_WAIT_TIMER_M); 

    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M);  // PLL wait cycles in slow_clk_rtc
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x3 << 14, RTC_CNTL_XTL_BUF_WAIT_M);  // XTAL wait cycles in slow_clk_rtc
    REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);     // CK8M wait cycles in slow_clk_rtc
    ets_update_cpu_frequency(8);
    rtc_apb_freq_up(8000000);
}

0x4008f1c4 <rtc_slp_prep>: entry	a1, 48
0x4008f1c7 <rtc_slp_prep+3>: call8	0x4008f9ec <rtc_get_xtal>
0x4008f1ca <rtc_slp_prep+6>: l32r	a8, 0x4008e53c  /* a8 = *(0x4008e5c0) = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */
0x4008f1cd <rtc_slp_prep+9>: l32r	a9, 0x400865dc  /* a9 = *(0x40086674) = 0xe7ffffff */
0x4008f1d0 <rtc_slp_prep+12>: memw
0x4008f1d3 <rtc_slp_prep+15>: l32i	a12, a8, 0  /* a12 = read RTC_CNTL_CLK_CONF_REG = 0x2d580210 */
0x4008f1d6 <rtc_slp_prep+18>: extui	a11, a3, 0, 2   /* a11 = p2[1:0], 2nd_param of rtc_slp_prep */
0x4008f1d9 <rtc_slp_prep+21>: slli	a11, a11, 27
0x4008f1dc <rtc_slp_prep+24>: and	a9, a12, a9
0x4008f1df <rtc_slp_prep+27>: or	a9, a11, a9  /* set BIT[28:27] of RTC_CNTL_CLK_CONF_REG */
0x4008f1e2 <rtc_slp_prep+30>: memw
0x4008f1e5 <rtc_slp_prep+33>: s32i	a9, a8, 0
/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0; SOC clock sel. 0: XTAL  1: PLL  2: CK8M  3: APLL */

0x4008f1e8 <rtc_slp_prep+36>: or	a13, a10, a10  /* a10 is the return value of rtc_get_xtal() */
0x4008f1eb <rtc_slp_prep+39>: bnei	a3, 1, 0x4008f238 <rtc_slp_prep+116>  ------> If (a3 != 1), not the PLL clock, jump

/* Following is related the PLL clock */
0x4008f1ee <rtc_slp_prep+42>: l32r	a3, 0x4008e57c  /* a3 = 0x3ff4801c, RTC_CNTL_TIMER1_REG */
0x4008f1f1 <rtc_slp_prep+45>: l32r	a8, 0x40084ce0  /* a8 = 0x00ffffff, BIT[31:24] */
0x4008f1f4 <rtc_slp_prep+48>: memw
0x4008f1f7 <rtc_slp_prep+51>: l32i.n	a9, a3, 0
0x4008f1f9 <rtc_slp_prep+53>: and	a8, a9, a8
0x4008f1fc <rtc_slp_prep+56>: l32r	a9, 0x4008f19c  /* a9 = 0x14000000 */
0x4008f1ff <rtc_slp_prep+59>: or	a8, a8, a9       /* set BIT[31:24] = 0x14 */
0x4008f202 <rtc_slp_prep+62>: memw
0x4008f205 <rtc_slp_prep+65>: s32i.n	a8, a3, 0  /* Write back to RTC_CNTL_TIMER1_REG */
0x4008f207 <rtc_slp_prep+67>: memw
/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; PLL wait cycles in slow_clk_rtc */

0x4008f20a <rtc_slp_prep+70>: l32i.n	a9, a3, 0
0x4008f20c <rtc_slp_prep+72>: l32r	a8, 0x4008e580  /* a8 = 0xff003fff, BIT[23:14] */
0x4008f20f <rtc_slp_prep+75>: and	a8, a9, a8
0x4008f212 <rtc_slp_prep+78>: l32r	a9, 0x4008f1a0  /* a9 = 0x00050000 */
0x4008f215 <rtc_slp_prep+81>: or	a8, a8, a9     /* set BIT[23:14] = 0x14 */
0x4008f218 <rtc_slp_prep+84>: memw
0x4008f21b <rtc_slp_prep+87>: s32i.n	a8, a3, 0
0x4008f21d <rtc_slp_prep+89>: memw
/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; XTAL wait cycles in slow_clk_rtc */

0x4008f220 <rtc_slp_prep+92>: l32i.n	a9, a3, 0
0x4008f222 <rtc_slp_prep+94>: l32r	a8, 0x4008e584  /* a8 = 0xffffc03f, BIT[13:6] */
0x4008f225 <rtc_slp_prep+97>: and	a8, a9, a8
0x4008f228 <rtc_slp_prep+100>: movi	a9, 0x500
0x4008f22b <rtc_slp_prep+103>: or	a8, a8, a9  /* set BIT[13:6] = 0x14 */
0x4008f22e <rtc_slp_prep+106>: memw
0x4008f231 <rtc_slp_prep+109>: s32i.n	a8, a3, 0
/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; CK8M wait cycles in slow_clk_rtc */

0x4008f233 <rtc_slp_prep+111>: j	0x4008f34e <rtc_slp_prep+394>  ------> jump 394

0x4008f235 <rtc_slp_prep+113>: ill  (0x0000)  <------------- openocd/gdb bug

>>>>>>>>>
0x4008f238 <rtc_slp_prep+116>: bnez	a3, 0x4008f298 <rtc_slp_prep+212> if (a3 != 0), not the XTAL clock, jump --------->

/* Following should be related to the XTAL clock */
0x4008f23b <rtc_slp_prep+119>: l32r	a3, 0x4008e57c  /* a3 = 0x3ff4801c, RTC_CNTL_TIMER1_REG */
0x4008f23e <rtc_slp_prep+122>: l32r	a8, 0x40084ce0  /* a8 = 0x00ffffff, BIT[31:24] */
0x4008f241 <rtc_slp_prep+125>: memw
0x4008f244 <rtc_slp_prep+128>: l32i.n	a9, a3, 0
0x4008f246 <rtc_slp_prep+130>: and	a8, a9, a8
0x4008f249 <rtc_slp_prep+133>: l32r	a9, 0x40084c80  /* a9 = 0x01000000 */
0x4008f24c <rtc_slp_prep+136>: or	a8, a8, a9  /* set BIT[31:24] = 0x1 */
0x4008f24f <rtc_slp_prep+139>: memw
0x4008f252 <rtc_slp_prep+142>: s32i.n	a8, a3, 0
0x4008f254 <rtc_slp_prep+144>: memw
/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; PLL wait cycles in slow_clk_rtc */

0x4008f257 <rtc_slp_prep+147>: l32i.n	a9, a3, 0
0x4008f259 <rtc_slp_prep+149>: l32r	a8, 0x4008e580  /* a8 = 0xff003fff, BIT[23:14] */
0x4008f25c <rtc_slp_prep+152>: and	a8, a9, a8
0x4008f25f <rtc_slp_prep+155>: l32r	a9, 0x4008f1a0  /* a9 = 0x00050000 */
0x4008f262 <rtc_slp_prep+158>: or	a8, a8, a9     /* set BIT[23:14] = 0x14 */
0x4008f265 <rtc_slp_prep+161>: memw
0x4008f268 <rtc_slp_prep+164>: s32i.n	a8, a3, 0
0x4008f26a <rtc_slp_prep+166>: memw
/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; XTAL wait cycles in slow_clk_rtc */

0x4008f26d <rtc_slp_prep+169>: l32i.n	a9, a3, 0
0x4008f26f <rtc_slp_prep+171>: l32r	a8, 0x4008e584  /* a8 = 0xffffc03f, BIT[13:6] */
0x4008f272 <rtc_slp_prep+174>: and	a8, a9, a8
0x4008f275 <rtc_slp_prep+177>: movi	a9, 0x500
0x4008f278 <rtc_slp_prep+180>: or	a8, a8, a9  /* set BIT[13:6] = 0x14 */
0x4008f27b <rtc_slp_prep+183>: memw
0x4008f27e <rtc_slp_prep+186>: s32i.n	a8, a3, 0
/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; CK8M wait cycles in slow_clk_rtc */

0x4008f280 <rtc_slp_prep+188>: s32i	a13, a1, 0  /* store the a13 into stack */

0x4008f283 <rtc_slp_prep+191>: l32r	a8, 0x4008f1c0  /* a8 = 0x40008550, ets_update_cpu_frequency */
0x4008f286 <rtc_slp_prep+194>: callx8	a8      /* ets_update_cpu_frequency(uint32_t ticks_per_us) */
/* a10 is the ticks_per_us, get from call rtc_get_xtal() */

0x4008f289 <rtc_slp_prep+197>: l32i.n	a13, a1, 0  /* restore a13 */

0x4008f28b <rtc_slp_prep+199>: l32r	a10, 0x40080574  /* a10 = 0x000f4240 */
0x4008f28e <rtc_slp_prep+202>: mull	a10, a13, a10  /* a10 = rtc_get_xtal() * 1000000 */
0x4008f291 <rtc_slp_prep+205>: call8	0x4008fa40 <rtc_apb_freq_up>
0x4008f294 <rtc_slp_prep+208>: j	0x4008f34e <rtc_slp_prep+394>      -----------------------> jump 394
0x4008f296 <rtc_slp_prep+210>:	0x0000             <-------------- openocd/gdb bug

>>>>>>>>>>>>>>>>>
0x4008f298 <rtc_slp_prep+212>:	beqi	a3, 2, 0x4008f29e <rtc_slp_prep+218>  /* if (a3 == 2); CK8M clock, jump */
0x4008f29b <rtc_slp_prep+215>:	j	0x4008f34e <rtc_slp_prep+394>    -------------------------> jump 394

/* Following is related to CK8M clock */
0x4008f29e <rtc_slp_prep+218>:	l32r	a3, 0x4008f1a4  /* a3 = 0x3ff48024, RTC_CNTL_TIMER3_REG */
0x4008f2a1 <rtc_slp_prep+221>: l32r	a8, 0x4008f050  /* a8 = 0x01ffffff, BIT[31:25] */
0x4008f2a4 <rtc_slp_prep+224>: memw
0x4008f2a7 <rtc_slp_prep+227>: l32i	a9, a3, 0  /* a9 = 0x14160a08 */
0x4008f2aa <rtc_slp_prep+230>: movi	a10, 1
0x4008f2ad <rtc_slp_prep+233>: and	a8, a9, a8
0x4008f2b0 <rtc_slp_prep+236>: l32r	a9, 0x40084c00  /* a9 = 0x02000000 */
0x4008f2b3 <rtc_slp_prep+239>: or	a8, a8, a9  /* set BIT[31:25] = 0x1 */
0x4008f2b6 <rtc_slp_prep+242>: memw
0x4008f2b9 <rtc_slp_prep+245>: s32i	a8, a3, 0
0x4008f2bc <rtc_slp_prep+248>: memw
/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */

0x4008f2bf <rtc_slp_prep+251>: l32i.n	a9, a3, 0
0x4008f2c1 <rtc_slp_prep+253>: l32r	a8, 0x4008ba60  /* a8 = 0xfe00ffff, BIT[24:16] */
0x4008f2c4 <rtc_slp_prep+256>: and	a8, a9, a8
0x4008f2c7 <rtc_slp_prep+259>: l32r	a9, 0x40088a98  /* a9 = 0x00010000 */
0x4008f2ca <rtc_slp_prep+262>: or	a8, a8, a9    /* set BIT[24:16] = 0x1 */
0x4008f2cd <rtc_slp_prep+265>: memw
0x4008f2d0 <rtc_slp_prep+268>: s32i.n	a8, a3, 0
0x4008f2d2 <rtc_slp_prep+270>: memw
/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */

0x4008f2d5 <rtc_slp_prep+273>: l32i.n	a9, a3, 0
0x4008f2d7 <rtc_slp_prep+275>: l32r	a8, 0x4008f1a8  /* a8 = 0xffff01ff, BIT[15:9] */
0x4008f2da <rtc_slp_prep+278>: and	a8, a9, a8
0x4008f2dd <rtc_slp_prep+281>: movi	a9, 0x200
0x4008f2e0 <rtc_slp_prep+284>: or	a8, a8, a9     /* set BIT[15:9] = 0x1 */
0x4008f2e3 <rtc_slp_prep+287>: memw
0x4008f2e6 <rtc_slp_prep+290>: s32i.n	a8, a3, 0
0x4008f2e8 <rtc_slp_prep+292>: memw
/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */

0x4008f2eb <rtc_slp_prep+295>: l32i.n	a9, a3, 0
0x4008f2ed <rtc_slp_prep+297>: movi	a8, 0xfffffe00  /* BIT[8:0] */
0x4008f2f0 <rtc_slp_prep+300>: and	a9, a9, a8
0x4008f2f3 <rtc_slp_prep+303>: or	a9, a9, a10    /* a10 == 1, set BIT[8:0] = 1 */
0x4008f2f6 <rtc_slp_prep+306>: l32r	a8, 0x4008e57c  /* a8 = 0x3ff4801c, RTC_CNTL_TIMER1_REG */
0x4008f2f9 <rtc_slp_prep+309>: memw
0x4008f2fc <rtc_slp_prep+312>: s32i.n	a9, a3, 0
0x4008f2fe <rtc_slp_prep+314>: memw
/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */

0x4008f301 <rtc_slp_prep+317>: l32i.n	a9, a8, 0   /* a9 = read TIMER1_REG = 0x14050043 */
0x4008f303 <rtc_slp_prep+319>: l32r	a3, 0x40084ce0  /* a3 = 0x00ffffff, BIT[31:24] */
0x4008f306 <rtc_slp_prep+322>: movi.n	a10, 8
0x4008f308 <rtc_slp_prep+324>: and	a3, a9, a3
0x4008f30b <rtc_slp_prep+327>: l32r	a9, 0x40084c80  /* a9 = 0x01000000 */
0x4008f30e <rtc_slp_prep+330>: or	a3, a3, a9  /* set BIT[31:24] = 0x1 */
0x4008f311 <rtc_slp_prep+333>: memw
0x4008f314 <rtc_slp_prep+336>: s32i.n	a3, a8, 0
0x4008f316 <rtc_slp_prep+338>: memw
/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; PLL wait cycles in slow_clk_rtc*/

0x4008f319 <rtc_slp_prep+341>: l32i.n	a9, a8, 0
0x4008f31b <rtc_slp_prep+343>: l32r	a3, 0x4008e580  /* a3 = 0xff003fff */
0x4008f31e <rtc_slp_prep+346>: and	a3, a9, a3
0x4008f321 <rtc_slp_prep+349>: l32r	a9, 0x4008f1ac  /* a9 = 0x0000c000 */
0x4008f324 <rtc_slp_prep+352>: or	a3, a3, a9     /* set BIT[23:14] = 0x3 */
0x4008f327 <rtc_slp_prep+355>: memw
0x4008f32a <rtc_slp_prep+358>: s32i.n	a3, a8, 0
0x4008f32c <rtc_slp_prep+360>: memw
/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80; XTAL wait cycles in slow_clk_rtc*/

0x4008f32f <rtc_slp_prep+363>: l32i.n	a9, a8, 0
0x4008f331 <rtc_slp_prep+365>: l32r	a3, 0x4008e584  /* a3 = 0xffffc03f */
0x4008f334 <rtc_slp_prep+368>: and	a3, a9, a3
0x4008f337 <rtc_slp_prep+371>: movi	a9, 0x500
0x4008f33a <rtc_slp_prep+374>: or	a3, a3, a9    /* set BIT[13:6] = 0x14 */
0x4008f33d <rtc_slp_prep+377>: memw
0x4008f340 <rtc_slp_prep+380>: s32i.n	a3, a8, 0
/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; CK8M wait cycles in slow_clk_rtc*/

0x4008f342 <rtc_slp_prep+382>: l32r	a8, 0x4008f1c0  /* a8 = 0x40008550, ets_update_cpu_frequency */
0x4008f345 <rtc_slp_prep+385>: callx8	a8   /* a10 = 8 */

0x4008f348 <rtc_slp_prep+388>: l32r	a10, 0x4008f1b0  /* a10 = 0x007a1200 = 8000000 */
0x4008f34b <rtc_slp_prep+391>: call8	0x4008fa40 <rtc_apb_freq_up>  /* rtc_apb_freq_up(8000000) */


[编辑] 4.2 Part Two

rtc_uart_div_modify(0);

REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, 0xdd00 0000);  // clear PLL_I2C/CKGEN_I2C/RFRX_PBUS/TXRF_I2C/PVTMON/PLLA
REG_CLR_BIT(SARADC_SAR_MEAS_WAIT2_REG, SARADC_FORCE_XPD_SAR_M); // 0x3 << 18

if (p3 != 0) {
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x1 << 4);  // memories in digital core force power up in sleep
} else {
    REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x1 << 4);  // memories in digital core force no power up in sleep
}

if (p4 != 0) {
    REG_SET_BIT(RTC_CNTL_PWC_REG, 0x00012000);  // set BIT[13], 16
    // RTC memory and Fast RTC memory force power up
} else {
    REG_CLR_BIT(RTC_CNTL_PWC_REG, 0x00012000);  // clear BIT[13], 16
    // RTC memory and Fast RTC memory force no power up
}

// p5 = deep_slp & 0x10, BIT[4]
if (p5 != 0) {
    // Power down the RTC memory and Fast RTC memory
    REG_SET_BIT(RTC_CNTL_PWC_REG, 0x0000 0240);  // set BIT[9], 6
    /*
     * RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0;
     * 1: RTC memory  PD following CPU
     * 0: RTC memory PD following RTC state machine
     *
     * RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0
     * 1: Fast RTC memory PD following CPU
     * 0: fast RTC memory PD following RTC state machine
     */
} else {
    REG_CLR_BIT(RTC_CNTL_PWC_REG, 0x0000 0240);  // clear BIT[9], 6
}

// p6 = deep_slp & 0x8, BIT[3], PD_RTC_FAST_MEM
if (p6 != 0) {
    // Power down Fast Memory
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO)
} else {
    // Power up fast memory
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO)
}
>>>>>>>>>>>>>>>>>>>>>>>>
0x4008f34e <rtc_slp_prep+394>: movi	a10, 0
0x4008f351 <rtc_slp_prep+397>: call8	0x4008fa5c <rtc_uart_div_modify>  /* rtc_uart_div_modify(0) */

0x4008f354 <rtc_slp_prep+400>: l32r	a8, 0x4008e4d4  /* a8 = 0x3ff48030, RTC_CNTL_ANA_CONF_REG */
0x4008f357 <rtc_slp_prep+403>: movi	a3, -1   /* a3 = 0xffff ffff */
0x4008f35a <rtc_slp_prep+406>: memw
0x4008f35d <rtc_slp_prep+409>: l32i	a9, a8, 0
0x4008f360 <rtc_slp_prep+412>: xor	a2, a3, a2  /* a2 = ~p1 = 0x22ff ffff */
0x4008f363 <rtc_slp_prep+415>: and	a2, a2, a9  /* clear BIT[31], 30, 28, 27, 26, 24 */
0x4008f366 <rtc_slp_prep+418>: l32r	a3, 0x4008bff8  /* a3 = 0x3ff4880c, SARADC_SAR_MEAS_WAIT2_REG */
0x4008f369 <rtc_slp_prep+421>: memw
0x4008f36c <rtc_slp_prep+424>: s32i.n	a2, a8, 0
0x4008f36e <rtc_slp_prep+426>: memw
/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0; 1: PLL_I2C power up   otherwise power down*/
/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0; 1: CKGEN_I2C power up   otherwise power down*/
/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0; 1: RFRX_PBUS power up   otherwise power down*/
/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0; 1: TXRF_I2C power up   otherwise power down*/
/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0; 1: PVTMON power up   otherwise power down*/
/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; PLLA force power up*/

0x4008f371 <rtc_slp_prep+429>: l32i.n	a8, a3, 0
0x4008f373 <rtc_slp_prep+431>: l32r	a2, 0x4008af28  /* a2 = 0xfff3ffff */
0x4008f376 <rtc_slp_prep+434>: and	a2, a8, a2    /* clear BIT[19:18] of SARADC_SAR_MEAS_WAIT2_REG */
0x4008f379 <rtc_slp_prep+437>: memw
0x4008f37c <rtc_slp_prep+440>: s32i.n	a2, a3, 0
/* SARADC_FORCE_XPD_SAR : R/W ;bitpos:[19:18] ;default: 2'd0 ; */

0x4008f37e <rtc_slp_prep+442>: l32r	a2, 0x4008e2f0  /* a2 = 0x3ff48084, RTC_CNTL_DIG_PWC_REG */  <<<=====
0x4008f381 <rtc_slp_prep+445>: beqz.n	a4, 0x4008f395 ------> if (a4 == 0); jump to 465 (a4 is 0 in lite)
0x4008f383 <rtc_slp_prep+447>: memw

0x4008f386 <rtc_slp_prep+450>: l32i.n	a4, a2, 0  /* a4 = 0x80000000 */
0x4008f388 <rtc_slp_prep+452>: movi.n	a3, 16
0x4008f38a <rtc_slp_prep+454>: or	a3, a4, a3  /* (RTC_CNTL_DIG_PWC_REG | 0x10) */
0x4008f38d <rtc_slp_prep+457>: memw
0x4008f390 <rtc_slp_prep+460>: s32i.n	a3, a2, 0  /* set BIT[4] = 1 */
/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; memories in digital core force no PD in sleep*/

0x4008f392 <rtc_slp_prep+462>: j	0x4008f3a4 <rtc_slp_prep+480>

>>>>>>>>>
0x4008f395 <rtc_slp_prep+465>: memw
0x4008f398 <rtc_slp_prep+468>: l32i.n	a4, a2, 0
0x4008f39a <rtc_slp_prep+470>: movi.n	a3, -17  /* a3 = 0xffff ffef */
0x4008f39c <rtc_slp_prep+472>: and	a3, a4, a3  /* clear BIT[4] */
0x4008f39f <rtc_slp_prep+475>: memw
0x4008f3a2 <rtc_slp_prep+478>: s32i.n	a3, a2, 0
/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; memories in digital core force no PD in sleep*/

>>>>>>>>>
0x4008f3a4 <rtc_slp_prep+480>: l32r	a8, 0x4008e2f4  /* a8 = 0x3ff48080, RTC_CNTL_PWC_REG */  <<<=====
0x4008f3a7 <rtc_slp_prep+483>: memw
0x4008f3aa <rtc_slp_prep+486>: l32i.n	a4, a8, 0  /* a4 = 0x00000000 */

0x4008f3ac <rtc_slp_prep+488>: beqz.n	a5, 0x4008f3bc if (a5 == 0); jump to 504 (a5 is 0 in lite) -----> 

>>>> a5 is non-zero
0x4008f3ae <rtc_slp_prep+490>: l32r	a3, 0x4008f1b4  /* a3 = 0x00012000 */
0x4008f3b1 <rtc_slp_prep+493>: or	a3, a4, a3    /* set BIT[16] = 1, BIT[13] = 1 */
0x4008f3b4 <rtc_slp_prep+496>: memw
0x4008f3b7 <rtc_slp_prep+499>: s32i.n	a3, a8, 0
/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1; RTC memory force power up*/
/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1; Fast RTC memory force power up*/

0x4008f3b9 <rtc_slp_prep+501>: j	0x4008f3c7 <rtc_slp_prep+515>

>>>>>>>>> a5 is zero
0x4008f3bc <rtc_slp_prep+504>: l32r	a3, 0x4008e594  /* a3 = 0xfffedfff */
0x4008f3bf <rtc_slp_prep+507>: and	a3, a4, a3    /* clear BIT[16], BIT[13] */
0x4008f3c2 <rtc_slp_prep+510>: memw
0x4008f3c5 <rtc_slp_prep+513>: s32i.n	a3, a8, 0

>>>>>>>>>
0x4008f3c7 <rtc_slp_prep+515>: memw
0x4008f3ca <rtc_slp_prep+518>: l32i.n	a4, a8, 0
0x4008f3cc <rtc_slp_prep+520>: beqz.n	a6, 0x4008f3dc <rtc_slp_prep+536> if (a6 == 0); jump to 536 (a6 is 0 in lite) ----->
/* a6 = deep_slp & 0x10, BIT[4] */

If (a6 set BIT[4]); then: >>> Power down the RTC memory and Fast RTC memory
0x4008f3ce <rtc_slp_prep+522>: movi	a3, 0x240
0x4008f3d1 <rtc_slp_prep+525>: or	a3, a4, a3    /* set BIT[9], BIT[6] = 1 */
0x4008f3d4 <rtc_slp_prep+528>: memw
0x4008f3d7 <rtc_slp_prep+531>: s32i.n	a3, a8, 0
/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0;
 * 1: RTC memory  PD following CPU
 * 0: RTC memory PD following RTC state machine
 *
 * RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0
 * 1: Fast RTC memory PD following CPU
 * 0: fast RTC memory PD following RTC state machine
 */

0x4008f3d9 <rtc_slp_prep+533>: j	0x4008f3e7 <rtc_slp_prep+547>

>>>>>>>>>
0x4008f3dc <rtc_slp_prep+536>: movi	a3, 0xfffffdbf
0x4008f3df <rtc_slp_prep+539>: and	a3, a4, a3    /* clear BIT[9], BIT[6] */
0x4008f3e2 <rtc_slp_prep+542>: memw
0x4008f3e5 <rtc_slp_prep+545>: s32i.n	a3, a8, 0

>>>>>>>>>
0x4008f3e7 <rtc_slp_prep+547>: memw
0x4008f3ea <rtc_slp_prep+550>: l32i.n	a4, a8, 0
0x4008f3ec <rtc_slp_prep+552>: beqz.n	a7, 0x4008f41c <rtc_slp_prep+600> if (a7 == 0); jump to 600 ---->
/* a7 = deep_slp & 0x8, BIT[3], PD_RTC_FAST_MEM */

//// Following to Power down Fast Memory
0x4008f3ee <rtc_slp_prep+554>: l32r	a3, 0x400878b8  /* a3 = 0x00004000 */
0x4008f3f1 <rtc_slp_prep+557>: or	a3, a4, a3    /* set BIT[14] = 1 */
0x4008f3f4 <rtc_slp_prep+560>: memw
0x4008f3f7 <rtc_slp_prep+563>: s32i.n	a3, a8, 0
0x4008f3f9 <rtc_slp_prep+565>: memw
/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0; enable power down fast RTC memory in sleep*/

0x4008f3fc <rtc_slp_prep+568>: l32i.n	a4, a8, 0
0x4008f3fe <rtc_slp_prep+570>: l32r	a3, 0x4008db64  /* a3 = 0xffffdfff */
0x4008f401 <rtc_slp_prep+573>: and	a3, a4, a3    /* clear BIT[13] */
0x4008f404 <rtc_slp_prep+576>: memw
0x4008f407 <rtc_slp_prep+579>: s32i.n	a3, a8, 0
0x4008f409 <rtc_slp_prep+581>: memw
/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1; Fast RTC memory force power up*/

0x4008f40c <rtc_slp_prep+584>: l32i.n	a4, a8, 0
0x4008f40e <rtc_slp_prep+586>: movi.n	a3, -2  /* a3 = 0xffff fffe */
0x4008f410 <rtc_slp_prep+588>: and	a3, a4, a3  /* clear BIT[0] */
0x4008f413 <rtc_slp_prep+591>: memw
0x4008f416 <rtc_slp_prep+594>: s32i.n	a3, a8, 0
/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1; Fast RTC memory force no ISO*/

0x4008f418 <rtc_slp_prep+596>: j	0x4008f446 <rtc_slp_prep+642>
0x4008f41a <rtc_slp_prep+598>: 0x0000

>>>>>> Fast memory not power down
0x4008f41c <rtc_slp_prep+600>: l32r	a3, 0x40080434  /* a3 = 0xffffbfff */
0x4008f41f <rtc_slp_prep+603>: and	a3, a4, a3    /* clear BIT[14] */
0x4008f422 <rtc_slp_prep+606>: memw
0x4008f425 <rtc_slp_prep+609>: s32i.n	a3, a8, 0  // Fast mem power down clear
0x4008f427 <rtc_slp_prep+611>: memw

0x4008f42a <rtc_slp_prep+614>: l32i.n	a4, a8, 0
0x4008f42c <rtc_slp_prep+616>: l32r	a3, 0x4008063c  /* a3 = 0x00002000 */
0x4008f42f <rtc_slp_prep+619>: or	a3, a4, a3    /* set BIT[13] */
0x4008f432 <rtc_slp_prep+622>: memw
0x4008f435 <rtc_slp_prep+625>: s32i.n	a3, a8, 0 // Fast mem power up
0x4008f437 <rtc_slp_prep+627>: memw

0x4008f43a <rtc_slp_prep+630>: l32i.n	a4, a8, 0
0x4008f43c <rtc_slp_prep+632>: movi.n	a3, 1
0x4008f43e <rtc_slp_prep+634>: or	a3, a4, a3  /* set BIT[0] */
0x4008f441 <rtc_slp_prep+637>: memw
0x4008f444 <rtc_slp_prep+640>: s32i.n	a3, a8, 0  // Force no ISO


[编辑] 4.3 Part three

// p7
if (deep_slp & 0x4 != 0) {
    // Power down RTC memory (SLOW)
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_SLOWMEM_FORCE_NOISO)
} else {
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_SLOWMEM_FORCE_NOISO)
}

// p8
if (deep_slp & 0x2 != 0) {
    REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);  // enable power down rtc_peri in sleep
} else {
    REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);  // disable power down rtc_peri in sleep
}

// p9 = up_a1 + 8 = a1 + 48 + 8
if (p9 != 0) {
    // enable power down wifi in sleep
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
} else {
    // disable power down wifi in sleep
    REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
}

// p10 = up_a1 + 12 = a1 + 48 + 12
if (p9 != 0) {
    // SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are power down in sleep
    // BIT[29:14]
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x3f000000);
} else {
    // SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are not power down in sleep
    REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x3f000000);
}

// p11 = up_a1 + 16 = a1 + 48 + 16
if (p11 != 0) {
    rtc_deep_slp_conf();

    REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
    // bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep
} else {
    REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
    // bitpos:[31] ;default: 1'd0; SW system reset*

    REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
    // R/W ;bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep
}

// p12 = *(a1 + 48 + 20), p13 = *(a1 + 48 + 24) = cpu_lp_mode 

rtc_dbias_cfg(p14, p15, p16, p17);

if (p13 != 0) rtc_digital_lp_mode(); // cpu_lp_mode != 0; not deep sleep

return;
>>>>>>
0x4008f446 <rtc_slp_prep+642>: l32i.n	a3, a1, 48  /* (a1 + 48 + 0), a3 = deep_slp & 0x4, BIT[2]  */
0x4008f448 <rtc_slp_prep+644>: memw
0x4008f44b <rtc_slp_prep+647>: l32i.n	a4, a8, 0
0x4008f44d <rtc_slp_prep+649>: beqz.n	a3, 0x4008f47c <rtc_slp_prep+696> if (a3 == 0); jump to 696 --->

>>>>> p1 Non-Zero, RTC memory power down in sleep
0x4008f44f <rtc_slp_prep+651>: l32r	a3, 0x40087268  /* a3 = 0x00020000 */
0x4008f452 <rtc_slp_prep+654>: or	a3, a4, a3    /* set BIT[17] */
0x4008f455 <rtc_slp_prep+657>: memw
0x4008f458 <rtc_slp_prep+660>: s32i.n	a3, a8, 0
0x4008f45a <rtc_slp_prep+662>: memw
/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0; enable power down RTC memory in sleep*/

0x4008f45d <rtc_slp_prep+665>: l32i.n	a4, a8, 0
0x4008f45f <rtc_slp_prep+667>: l32r	a3, 0x4008c0e4  /* a3 = 0xfffeffff */
0x4008f462 <rtc_slp_prep+670>: and	a3, a4, a3    /* clear BIT[16] */
0x4008f465 <rtc_slp_prep+673>: memw
0x4008f468 <rtc_slp_prep+676>: s32i.n	a3, a8, 0
0x4008f46a <rtc_slp_prep+678>: memw
/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1; RTC memory force power up*/

0x4008f46d <rtc_slp_prep+681>: l32i.n	a4, a8, 0
0x4008f46f <rtc_slp_prep+683>: movi.n	a3, -5  /* a3 = 0xffff fffc */
0x4008f471 <rtc_slp_prep+685>: and	a3, a4, a3  /* clear BIT[1:0] */
0x4008f474 <rtc_slp_prep+688>: memw
0x4008f477 <rtc_slp_prep+691>: s32i.n	a3, a8, 0
/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0; Fast RTC memory force ISO*/
/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1; Fast RTC memory force no ISO*/

0x4008f479 <rtc_slp_prep+693>: j	0x4008f4a6 <rtc_slp_prep+738>  ---------> jump to 738

>>>>>p1 zero, RTC memory power up in sleep
0x4008f47c <rtc_slp_prep+696>: l32r	a3, 0x400855e0  /* a3 = 0xfffdffff */
0x4008f47f <rtc_slp_prep+699>: and	a3, a4, a3    /* clear BIT[17] */
0x4008f482 <rtc_slp_prep+702>: memw
0x4008f485 <rtc_slp_prep+705>: s32i.n	a3, a8, 0
0x4008f487 <rtc_slp_prep+707>: memw
/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0; enable power down RTC memory in sleep*/

0x4008f48a <rtc_slp_prep+710>: l32i.n	a4, a8, 0
0x4008f48c <rtc_slp_prep+712>: l32r	a3, 0x40088a98  /* a3 = 0x00010000 */
0x4008f48f <rtc_slp_prep+715>: or	a3, a4, a3    /* set BIT[16] = 1 */
0x4008f492 <rtc_slp_prep+718>: memw
0x4008f495 <rtc_slp_prep+721>: s32i.n	a3, a8, 0
0x4008f497 <rtc_slp_prep+723>: memw
/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1; RTC memory force power up*/

0x4008f49a <rtc_slp_prep+726>: l32i.n	a4, a8, 0
0x4008f49c <rtc_slp_prep+728>: movi.n	a3, 4    /* a3 = 0x4 */
0x4008f49e <rtc_slp_prep+730>: or	a3, a4, a3    /* set BIT[2] = 1 */
0x4008f4a1 <rtc_slp_prep+733>: memw
0x4008f4a4 <rtc_slp_prep+736>: s32i.n	a3, a8, 0
/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1; RTC memory force no ISO*/

>>>>>>
0x4008f4a6 <rtc_slp_prep+738>: l32i.n	a3, a1, 52  /* load the param from stack */  a3 = 0x0 = deep_slp & 0x2
0x4008f4a8 <rtc_slp_prep+740>: memw
0x4008f4ab <rtc_slp_prep+743>: l32i.n	a4, a8, 0

0x4008f4ad <rtc_slp_prep+745>: beqz.n	a3, 0x4008f4bd <rtc_slp_prep+761> if (a3 == 0); jump 761 ---->

/// RTC_PERI power down, Px Non-zero
0x4008f4af <rtc_slp_prep+747>: l32r	a3, 0x4008ada0  /* a3 = 0x00100000 */
0x4008f4b2 <rtc_slp_prep+750>: or	a3, a4, a3   /* set BIT[20] */
0x4008f4b5 <rtc_slp_prep+753>: memw
0x4008f4b8 <rtc_slp_prep+756>: s32i.n	a3, a8, 0
/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0; enable power down rtc_peri in sleep*/

0x4008f4ba <rtc_slp_prep+758>: j	0x4008f4c8 <rtc_slp_prep+772>

>>>>>Px Zero, RTC_PERI not power down
0x4008f4bd <rtc_slp_prep+761>: l32r	a3, 0x400855d8  /* a3 = 0xffefffff */
0x4008f4c0 <rtc_slp_prep+764>: and	a3, a4, a3  /* clear BIT[20] */
0x4008f4c3 <rtc_slp_prep+767>: memw
0x4008f4c6 <rtc_slp_prep+770>: s32i.n	a3, a8, 0

>>>>>
0x4008f4c8 <rtc_slp_prep+772>: l32i.n	a3, a1, 56  /* load the param from stack */  a3 = 0x0 (up_a1 + 8) = a1 + 48 + 8
0x4008f4ca <rtc_slp_prep+774>: memw
0x4008f4cd <rtc_slp_prep+777>: l32i.n	a4, a2, 0  /* read  RTC_CNTL_DIG_PWC_REG */

0x4008f4cf <rtc_slp_prep+779>: beqz.n	a3, 0x4008f4e0 <rtc_slp_prep+796> if (a3 == 0); jump to 796 ---->

>>>>> Pwifi Non-zero (wifi power down in sleep)
0x4008f4d1 <rtc_slp_prep+781>: l32r	a3, 0x400805fc  /* a3 = 0x40000000 */
0x4008f4d4 <rtc_slp_prep+784>: or	a3, a4, a3  /* set BIT[30] */
0x4008f4d7 <rtc_slp_prep+787>: memw
0x4008f4da <rtc_slp_prep+790>: s32i.n	a3, a2, 0
/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0; enable power down wifi in sleep*/

0x4008f4dc <rtc_slp_prep+792>: j	0x4008f4eb <rtc_slp_prep+807>
0x4008f4de <rtc_slp_prep+794>: 0x0000

>>>>> Pwifi is zero (wifi not power down in sleep)
0x4008f4e0 <rtc_slp_prep+796>: l32r	a3, 0x4008838c  /* a3 = 0xbfffffff */
0x4008f4e3 <rtc_slp_prep+799>: and	a3, a4, a3    /* clear BIT[30] */
0x4008f4e6 <rtc_slp_prep+802>: memw
0x4008f4e9 <rtc_slp_prep+805>: s32i.n	a3, a2, 0

0x4008f4eb <rtc_slp_prep+807>: l32i.n	a3, a1, 60  /* load the param from stack */  a3 = 0 (ai + 48 + 12)
0x4008f4ed <rtc_slp_prep+809>: memw
0x4008f4f0 <rtc_slp_prep+812>: l32i.n	a4, a2, 0

0x4008f4f2 <rtc_slp_prep+814>: beqz.n	a3, 0x4008f505 <rtc_slp_prep+833> if (a3 == 0); jump to 833 ----->

>>>> Pz is Non-zero
0x4008f4f4 <rtc_slp_prep+816>: l32r	a3, 0x4008f1b8  /* a3 = 0x3f000000 */
0x4008f4f7 <rtc_slp_prep+819>: or	a3, a4, a3  /* set BIT[29:24] */
0x4008f4fa <rtc_slp_prep+822>: memw
0x4008f4fd <rtc_slp_prep+825>: s32i.n	a3, a2, 0
/* SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are power down in sleep */

0x4008f4ff <rtc_slp_prep+827>: j	0x4008f510 <rtc_slp_prep+844>
0x4008f502 <rtc_slp_prep+830>: ill

>>>> Pz is Zero
0x4008f505 <rtc_slp_prep+833>: l32r	a3, 0x4008f1bc  /* a3 = 0xc0ffffff */
0x4008f508 <rtc_slp_prep+836>: and	a3, a4, a3  /* clear BIT[29:24] */
0x4008f50b <rtc_slp_prep+839>: memw
0x4008f50e <rtc_slp_prep+842>: s32i.n	a3, a2, 0
/* SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are not power down in sleep */

>>>>
0x4008f510 <rtc_slp_prep+844>: l32i	a3, a1, 64  /* load the param from stack */  a3 = 0x1 (a1 + 48 + 16)
0x4008f513 <rtc_slp_prep+847>: beqz.n	a3, 0x4008f530 <rtc_slp_prep+876> if (a3 == 0); jump to 876 --------->

0x4008f515 <rtc_slp_prep+849>: call8	0x4008f054 <rtc_deep_slp_conf>

0x4008f518 <rtc_slp_prep+852>: l32r	a2, 0x400804e0  /* a2 = 0x3ff48000, RTC_CNTL_OPTIONS0_REG */
0x4008f51b <rtc_slp_prep+855>: l32r	a3, 0x4008c0e4  /* a3 = 0xfffeffff */
0x4008f51e <rtc_slp_prep+858>: memw
0x4008f521 <rtc_slp_prep+861>: l32i.n	a4, a2, 0
0x4008f523 <rtc_slp_prep+863>: and	a3, a4, a3  /* clear BIT[16] */
0x4008f526 <rtc_slp_prep+866>: memw
0x4008f529 <rtc_slp_prep+869>: s32i.n	a3, a2, 0
/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep*/

0x4008f52b <rtc_slp_prep+871>: j	0x4008f556 <rtc_slp_prep+914>
0x4008f52d <rtc_slp_prep+873>: 0x000000

>>>>
0x4008f530 <rtc_slp_prep+876>: memw
0x4008f533 <rtc_slp_prep+879>: l32i	a5, a2, 0
0x4008f536 <rtc_slp_prep+882>: l32r	a4, 0x400804c0  /* a4 = 0x7fffffff */
0x4008f539 <rtc_slp_prep+885>:	l32r	a3, 0x400804e0  /* a3 = 0x3ff48000, RTC_CNTL_OPTIONS0_REG */
0x4008f53c <rtc_slp_prep+888>: and	a4, a5, a4  /* clear BIT[31] */
0x4008f53f <rtc_slp_prep+891>: memw
0x4008f542 <rtc_slp_prep+894>: s32i	a4, a2, 0
0x4008f545 <rtc_slp_prep+897>: memw
/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0; SW system reset*/

0x4008f548 <rtc_slp_prep+900>: l32i	a4, a3, 0
0x4008f54b <rtc_slp_prep+903>: l32r	a2, 0x40088a98  /* a2 = 0x00010000 */
0x4008f54e <rtc_slp_prep+906>: or	a2, a4, a2    /* set BIT[16] */
0x4008f551 <rtc_slp_prep+909>: memw
0x4008f554 <rtc_slp_prep+912>: s32i.n	a2, a3, 0
/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep*/

>>>>
0x4008f556 <rtc_slp_prep+914>: l32i	a10, a1, 76  /* a10 = 0x4, (a1 + 48 + 28) */
0x4008f559 <rtc_slp_prep+917>: l32i	a11, a1, 80  /* a11 = 0x0, (a1 + 48 + 32) */
0x4008f55c <rtc_slp_prep+920>: l32i	a12, a1, 84  /* a12 = 0x0, (a1 + 48 + 36) */
0x4008f55f <rtc_slp_prep+923>: l32i	a13, a1, 88  /* a13 = 0x0, (a1 + 48 + 40) */
0x4008f562 <rtc_slp_prep+926>: call8	0x4008fe30 <rtc_dbias_cfg>

0x4008f565 <rtc_slp_prep+929>: l32i	a2, a1, 72  /* a2 = 0x0, (a1 + 48 + 24), cpu_lp_mode */
0x4008f568 <rtc_slp_prep+932>: beqz.n	a2, 0x4008f56d <rtc_slp_prep+937>  /* cp_lp_mode == 0, deep_sleep */

0x4008f56a <rtc_slp_prep+934>: call8	0x4008f0cc <rtc_digital_lp_mode>  /* not deep_sleep mode */

0x4008f56d <rtc_slp_prep+937>: retw.n



[编辑] 4.4 Overview

void rtc_slp_prep(p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15, p16, p17)
{
	int tick_per_us = rtc_get_xtal();

	REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, p2 << 27, RTC_CNTL_SOC_CLK_SEL_M);

	if (p2 == 1) {
		// PLL clock
		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 24, RTC_CNTL_PLL_BUF_WAIT_M);	// PLL wait cycles in slow_clk_rtc
		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M);	// XTAL wait cycles in slow_clk_rtc
		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);	// CK8M wait cycles in slow_clk_rtc
	} else if (p2 == 0) {
		// XTAL clock
		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M);	// PLL wait cycles in slow_clk_rtc
		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 14, RTC_CNTL_XTL_BUF_WAIT_M);	// XTAL wait cycles in slow_clk_rtc
		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);	// CK8M wait cycles in slow_clk_rtc
		ets_update_cpu_frequency(ticks_per_us);
		rtc_apb_freq_up(ticks_per_us * 1000000);
	} else if (p2 == 2) {
		// CK8M clock
		REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 25,
			     RTC_CNTL_ROM_RAM_POWERUP_TIMER_M);
		REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 16,
			     RTC_CNTL_ROM_RAM_WAIT_TIMER_M);
		REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1 << 9,
			     RTC_CNTL_WIFI_POWERUP_TIMER_M);
		REG_SET_BITS(RTC_CNTL_TIMER3_REG, 0x1, RTC_CNTL_WAIT_TIMER_M);

		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x1 << 24, RTC_CNTL_PLL_BUF_WAIT_M);	// PLL wait cycles in slow_clk_rtc
		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x3 << 14, RTC_CNTL_XTL_BUF_WAIT_M);	// XTAL wait cycles in slow_clk_rtc
		REG_SET_BITS(RTC_CNTL_TIMER1_REG, 0x14 << 6, RTC_CNTL_CK8M_WAIT_M);	// CK8M wait cycles in slow_clk_rtc
		ets_update_cpu_frequency(8);
		rtc_apb_freq_up(8000000);
	}

	rtc_uart_div_modify(0);

	REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, 0xdd00 0000);	// clear PLL_I2C/CKGEN_I2C/RFRX_PBUS/TXRF_I2C/PVTMON/PLLA
	REG_CLR_BIT(SARADC_SAR_MEAS_WAIT2_REG, SARADC_FORCE_XPD_SAR_M);	// 0x3 << 18

	if (p3 != 0) {
		REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x1 << 4);	// memories in digital core force power up in sleep
	} else {
		REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x1 << 4);	// memories in digital core force no power up in sleep
	}

	if (p4 != 0) {
		REG_SET_BIT(RTC_CNTL_PWC_REG, 0x00012000);	// set BIT[13], 16
		// RTC memory and Fast RTC memory force power up
	} else {
		REG_CLR_BIT(RTC_CNTL_PWC_REG, 0x00012000);	// clear BIT[13], 16
		// RTC memory and Fast RTC memory force no power up
	}

	// p5 = deep_slp & 0x10, BIT[4]
	if (p5 != 0) {
		// Power down the RTC memory and Fast RTC memory
		REG_SET_BIT(RTC_CNTL_PWC_REG, 0x0000 0240);	// set BIT[9], 6
		/*
		 * RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0;
		 * 1: RTC memory  PD following CPU
		 * 0: RTC memory PD following RTC state machine
		 *
		 * RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0
		 * 1: Fast RTC memory PD following CPU
		 * 0: fast RTC memory PD following RTC state machine
		 */
	} else {
		REG_CLR_BIT(RTC_CNTL_PWC_REG, 0x0000 0240);	// clear BIT[9], 6
	}

	// p6 = deep_slp & 0x8, BIT[3], PD_RTC_FAST_MEM
	if (p6 != 0) {
		// Power down Fast Memory
		REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
		REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
		REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO)
	} else {
		// Power up fast memory
		REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
		REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
		REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO)
	}

	// p7
	if (deep_slp & 0x4 != 0) {
		// Power down RTC memory (SLOW)
		REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
		REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
		REG_CLR_BIT(RTC_CNTL_PWC_REG,
			    RTC_CNTL_SLOWMEM_FORCE_ISO |
			    RTC_CNTL_SLOWMEM_FORCE_NOISO)
	} else {
		REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
		REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
		REG_SET_BIT(RTC_CNTL_PWC_REG,
			    RTC_CNTL_SLOWMEM_FORCE_ISO |
			    RTC_CNTL_SLOWMEM_FORCE_NOISO)
	}

	// p8
	if (deep_slp & 0x2 != 0) {
		REG_SET_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);	// enable power down rtc_peri in sleep
	} else {
		REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);	// disable power down rtc_peri in sleep
	}

	// p9 = up_a1 + 8 = a1 + 48 + 8
	if (p9 != 0) {
		// enable power down wifi in sleep
		REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
	} else {
		// disable power down wifi in sleep
		REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
	}

	// p10 = up_a1 + 12 = a1 + 48 + 12
	if (p9 != 0) {
		// SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are power down in sleep
		// BIT[29:14]
		REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x3f000000);
	} else {
		// SRAM4, SRAM3, SRAM2, SRAM1, SRAM0, ROM are not power down in sleep
		REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x3f000000);
	}

	// p11 = up_a1 + 16 = a1 + 48 + 16
	if (p11 != 0) {
		rtc_deep_slp_conf();

		REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
		// bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep
	} else {
		REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
		// bitpos:[31] ;default: 1'd0; SW system reset*

		REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
		// R/W ;bitpos:[16] ;default: 1'd1; BIAS_SLEEP force no sleep
	}

	// p12 = *(a1 + 48 + 20), p13 = *(a1 + 48 + 24) = cpu_lp_mode 

	rtc_dbias_cfg(p14, p15, p16, p17);

	if (p13 != 0)
		rtc_digital_lp_mode();	// cpu_lp_mode != 0; not deep sleep

	return;
}

void rtc_deep_slp_conf()
{
    REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, 0x00003000);  // clear DG_PAD_FORCE_ISO and DG_PAD_FORCE_NOISO
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x80000000);  // enable power down digital core in sleep

    REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x00180000);  // clear DG_WRAP_FORCE_PU and DG_WRAP_FORCE_PD

    REG_SET_BITS(RTC_CNTL_TIMER4_REG, 0x0200 0000, 0xfe000000);  // DG_WRAP_POWERUP_TIMER = 0x1
    REG_SET_BITS(RTC_CNTL_TIMER4_REG, 0x0001 0000, 0x01ff0000);  // DG_WRAP_WAIT_TIMER = 0x1
}

void rtc_dbias_cfg(p1, p2, p3, p4)
{
    REG_SET_BITS(RTC_CNTL_REG, p4 << 22, RTC_CNTL_DBIAS_SLP_M);      // RTC_DBIAS during sleep
    REG_SET_BITS(RTC_CNTL_REG, p1 << 11, RTC_CNTL_DIG_DBIAS_WAK_M);  // DIG_REG_DBIAS during wakeup
    REG_SET_BITS(RTC_CNTL_REG, p2 << 8, RTC_CNTL_DIG_DBIAS_SLP_M);   // DIG_REG_DBIAS during sleep
}

void rtc_digital_lp_mode()
{
    REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, 0x05550000);    // iram4 ~ iram0 and rom are force iso
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x0000aaa0);    // iram4 ~ iram0 and rom are force power down

    REG_WRITE(DPORT_PERIP_CLK_EN_REG, 0x0);
    REG_WRITE(DPORT_WIFI_CLK_EN_REG, 0x0);
    REG_CLR_BIT(DPORT_WIFI_CLK_EN_REG, 0x40);       // seems like to enable the MAC clk of wifi ??

    REG_SET_BIT(DPORT_WIFI_RST_EN_REG, DPORT_MAC_RST);           // wifi mac reset
    REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);  // wifi force iso
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);   // wifi power down
    REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, 0x10000000, RTC_CNTL_SOC_CLK_SEL_M);  // select the CK8K
    REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, 0x00001500, 0x00003f00);      // crystall, BB_PLL, BB_PLL_I2C force power down
    REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PD)  // bias core force power down
    REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);  // bias i2c force power down
}


[编辑] 5 rtc_deep_slp_conf

void rtc_deep_slp_conf()
{
  REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, 0x00003000);  // clear DG_PAD_FORCE_ISO and DG_PAD_FORCE_NOISO
  REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x80000000);  // enable power down digital core in sleep

  REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, 0x00180000);  // clear DG_WRAP_FORCE_PU and DG_WRAP_FORCE_PD

  REG_SET_BITS(RTC_CNTL_TIMER4_REG, 0x0200 0000, 0xfe000000);  // DG_WRAP_POWERUP_TIMER = 0x1
  REG_SET_BITS(RTC_CNTL_TIMER4_REG, 0x0001 0000, 0x01ff0000);  // DG_WRAP_WAIT_TIMER = 0x1
}
0x4008f054 <rtc_deep_slp_conf>:   entry	a1, 32
0x4008f057 <rtc_deep_slp_conf+3>: l32r	a8, 0x4008e598  /* a8 = 0x3ff48088, RTC_CNTL_DIG_ISO_REG */
0x4008f05a <rtc_deep_slp_conf+6>: l32r	a10, 0x4008c3c0  /* a10 = 0xffffcfff */
0x4008f05d <rtc_deep_slp_conf+9>: memw
0x4008f060 <rtc_deep_slp_conf+12>: l32i.n	a11, a8, 0
0x4008f062 <rtc_deep_slp_conf+14>: l32r	a9, 0x4008e2f0  /* a9 = 0x3ff48084, RTC_CNTL_DIG_PWC_REG */
0x4008f065 <rtc_deep_slp_conf+17>: and	a10, a11, a10  /* clear BIT[13:12] */
0x4008f068 <rtc_deep_slp_conf+20>: memw
0x4008f06b <rtc_deep_slp_conf+23>: s32i.n	a10, a8, 0
0x4008f06d <rtc_deep_slp_conf+25>: memw
/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0; digital pad force ISO*/
/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1; digital pad force no ISO*/

0x4008f070 <rtc_deep_slp_conf+28>: l32i.n	a10, a9, 0  /* read RTC_CNTL_DIG_PWC_REG */
0x4008f072 <rtc_deep_slp_conf+30>: l32r	a8, 0x400806ec  /* a8 = 0x80000000 */
0x4008f075 <rtc_deep_slp_conf+33>: or	a8, a10, a8  /* set BIT[31] */
0x4008f078 <rtc_deep_slp_conf+36>: memw
0x4008f07b <rtc_deep_slp_conf+39>: s32i.n	a8, a9, 0
0x4008f07d <rtc_deep_slp_conf+41>: memw
/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0; enable power down digital core in sleep*/

0x4008f080 <rtc_deep_slp_conf+44>: l32i.n	a11, a9, 0  /* read RTC_CNTL_DIG_PWC_REG */
0x4008f082 <rtc_deep_slp_conf+46>: l32r	a10, 0x4008f048  /* a10 = 0xffe7ffff */
0x4008f085 <rtc_deep_slp_conf+49>: l32r	a8, 0x4008f04c  /* a8 = 0x3ff48028, RTC_CNTL_TIMER4_REG */
0x4008f088 <rtc_deep_slp_conf+52>: and	a10, a11, a10  /* clear BIT[20:19] */
0x4008f08b <rtc_deep_slp_conf+55>: memw
0x4008f08e <rtc_deep_slp_conf+58>: s32i.n	a10, a9, 0
0x4008f090 <rtc_deep_slp_conf+60>: memw
/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1; digital core force power up*/
/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0; digital core force power down*/

0x4008f093 <rtc_deep_slp_conf+63>: l32i.n	a10, a8, 0  /* read RTC_CNTL_TIMER4_REG */
0x4008f095 <rtc_deep_slp_conf+65>: l32r	a9, 0x4008f050  /* a9 = 0x01ffffff */
0x4008f098 <rtc_deep_slp_conf+68>: and	a9, a10, a9  /* clear BIT[31:25] */
0x4008f09b <rtc_deep_slp_conf+71>: l32r	a10, 0x40084c00  /* a10 = 0x0200 0000 */
0x4008f09e <rtc_deep_slp_conf+74>: or	a9, a9, a10  /* set BIT[31:25] = 0x1 */
0x4008f0a1 <rtc_deep_slp_conf+77>: memw
0x4008f0a4 <rtc_deep_slp_conf+80>: s32i.n	a9, a8, 0
0x4008f0a6 <rtc_deep_slp_conf+82>: memw
/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */

0x4008f0a9 <rtc_deep_slp_conf+85>: l32i.n	a10, a8, 0  /* read RTC_CNTL_TIMER4_REG */
0x4008f0ab <rtc_deep_slp_conf+87>: l32r	a9, 0x4008ba60  /* a9 = 0xfe00ffff */
0x4008f0ae <rtc_deep_slp_conf+90>: and	a9, a10, a9  /* clear BIT[24:16] */
0x4008f0b1 <rtc_deep_slp_conf+93>: l32r	a10, 0x40088a98  /* a10 = 0x00010000 */
0x4008f0b4 <rtc_deep_slp_conf+96>: or	a9, a9, a10  /* set BIT[24:16] = 0x1 */
0x4008f0b7 <rtc_deep_slp_conf+99>: memw
0x4008f0ba <rtc_deep_slp_conf+102>: s32i.n	a9, a8, 0
/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */

0x4008f0bc <rtc_deep_slp_conf+104>: retw.n


[编辑] 6 rtc_dbias_cfg

void rtc_dbias_cfg(p1, p2, p3, p4)
{
    REG_SET_BITS(RTC_CNTL_REG, p4 << 22, RTC_CNTL_DBIAS_SLP_M);      // RTC_DBIAS during sleep
    REG_SET_BITS(RTC_CNTL_REG, p1 << 11, RTC_CNTL_DIG_DBIAS_WAK_M);  // DIG_REG_DBIAS during wakeup
    REG_SET_BITS(RTC_CNTL_REG, p2 << 8, RTC_CNTL_DIG_DBIAS_SLP_M);   // DIG_REG_DBIAS during sleep
}
   0x4008fe30 <rtc_dbias_cfg>:	entry	a1, 32
   0x4008fe33 <rtc_dbias_cfg+3>:	l32r	a8, 0x4008e58c  /* a8 = 0x3ff4807c, RTC_CNTL_REG */
   0x4008fe36 <rtc_dbias_cfg+6>:	l32r	a11, 0x4008e824  /* a11 = 0xfe3fffff */
   0x4008fe39 <rtc_dbias_cfg+9>:	memw
   0x4008fe3c <rtc_dbias_cfg+12>:	l32i.n	a9, a8, 0
   0x4008fe3e <rtc_dbias_cfg+14>:	extui	a5, a5, 0, 3  /* p4[2:0] */
   0x4008fe41 <rtc_dbias_cfg+17>:	slli	a10, a5, 22  /* a10 = p4[2:0] << 22 */
   0x4008fe44 <rtc_dbias_cfg+20>:	and	a9, a9, a11
   0x4008fe47 <rtc_dbias_cfg+23>:	or	a9, a10, a9
   0x4008fe4a <rtc_dbias_cfg+26>:	memw
   0x4008fe4d <rtc_dbias_cfg+29>:	s32i.n	a9, a8, 0
   0x4008fe4f <rtc_dbias_cfg+31>:	memw
   /* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4; RTC_DBIAS during sleep*/

   0x4008fe52 <rtc_dbias_cfg+34>:	l32i.n	a9, a8, 0  /* read RTC_CNTL_REG */
   0x4008fe54 <rtc_dbias_cfg+36>:	l32r	a11, 0x4008e82c  /* a11 = 0xffffc7ff */
   0x4008fe57 <rtc_dbias_cfg+39>:	extui	a2, a2, 0, 3  /* p1[2:0] */
   0x4008fe5a <rtc_dbias_cfg+42>:	slli	a10, a2, 11  /* a10 = p1[2:0] << 11 */
   0x4008fe5d <rtc_dbias_cfg+45>:	and	a9, a9, a11
   0x4008fe60 <rtc_dbias_cfg+48>:	or	a9, a10, a9
   0x4008fe63 <rtc_dbias_cfg+51>:	memw
   0x4008fe66 <rtc_dbias_cfg+54>:	s32i.n	a9, a8, 0
   0x4008fe68 <rtc_dbias_cfg+56>:	memw
   /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4; DIG_REG_DBIAS during wakeup*/

   0x4008fe6b <rtc_dbias_cfg+59>:	l32i.n	a9, a8, 0  /* read RTC_CNTL_REG */
   0x4008fe6d <rtc_dbias_cfg+61>:	extui	a3, a3, 0, 3  /* p2[2:0] */
   0x4008fe70 <rtc_dbias_cfg+64>:	movi	a11, 0xfffff8ff
   0x4008fe73 <rtc_dbias_cfg+67>:	slli	a10, a3, 8  /* a10 = p2[2:0] << 8 */
   0x4008fe76 <rtc_dbias_cfg+70>:	and	a9, a9, a11
   0x4008fe79 <rtc_dbias_cfg+73>:	or	a9, a10, a9
   0x4008fe7c <rtc_dbias_cfg+76>:	memw
   0x4008fe7f <rtc_dbias_cfg+79>:	s32i.n	a9, a8, 0
   /* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4; DIG_REG_DBIAS during sleep*/

   0x4008fe81 <rtc_dbias_cfg+81>:	retw.n


[编辑] 7 rtc_digital_lp_mode

void rtc_digital_lp_mode()
{
    REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, 0x05550000);    // iram4 ~ iram0 and rom are force iso
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, 0x0000aaa0);    // iram4 ~ iram0 and rom are force power down

    REG_WRITE(DPORT_PERIP_CLK_EN_REG, 0x0);
    REG_WRITE(DPORT_WIFI_CLK_EN_REG, 0x0);
    REG_CLR_BIT(DPORT_WIFI_CLK_EN_REG, 0x40);       // seems like to enable the MAC clk of wifi ??

    REG_SET_BIT(DPORT_WIFI_RST_EN_REG, DPORT_MAC_RST);           // wifi mac reset
    REG_SET_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);  // wifi force iso
    REG_SET_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);   // wifi power down
    REG_SET_BITS(RTC_CNTL_CLK_CONF_REG, 0x10000000, RTC_CNTL_SOC_CLK_SEL_M);  // select the CK8K
    REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, 0x00001500, 0x00003f00);      // crystall, BB_PLL, BB_PLL_I2C force power down
    REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PD)  // bias core force power down
    REG_SET_BITS(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);  // bias i2c force power down
}
0x4008f0cc <rtc_digital_lp_mode>: entry	a1, 32
0x4008f0cf <rtc_digital_lp_mode+3>: l32r	a9, 0x4008e598  /* a9 = 0x3ff48088, RTC_CNTL_DIG_ISO_REG */
0x4008f0d2 <rtc_digital_lp_mode+6>: l32r	a10, 0x4008f0c0  /* a10 = 0x05550000 */
0x4008f0d5 <rtc_digital_lp_mode+9>: memw
0x4008f0d8 <rtc_digital_lp_mode+12>: l32i.n	a11, a9, 0
0x4008f0da <rtc_digital_lp_mode+14>: l32r	a8, 0x4008e2f0  /* a8 = 0x3ff48084, RTC_CNTL_DIG_PWC_REG */
0x4008f0dd <rtc_digital_lp_mode+17>: or	a10, a11, a10  /* set BIT[26], 24, 22, 20, 18, 16 */
0x4008f0e0 <rtc_digital_lp_mode+20>: memw
0x4008f0e3 <rtc_digital_lp_mode+23>: s32i.n	a10, a9, 0
0x4008f0e5 <rtc_digital_lp_mode+25>: memw
/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0; internal SRAM 4 force ISO*/
/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0; internal SRAM 3 force ISO*/
/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0; internal SRAM 2 force ISO*/
/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0; internal SRAM 1 force ISO*/

0x4008f0e8 <rtc_digital_lp_mode+28>: l32i.n	a11, a8, 0
0x4008f0ea <rtc_digital_lp_mode+30>: l32r	a10, 0x4008f0c4  /* a10 = 0x0000aaa0 */
0x4008f0ed <rtc_digital_lp_mode+33>: l32r	a12, 0x4008f0c8  /* a12 = 0x3ff000c0 */
0x4008f0f0 <rtc_digital_lp_mode+36>: or	a10, a11, a10  /* set BIT[15], 13, 11, 9, 7, 5 */
0x4008f0f3 <rtc_digital_lp_mode+39>: memw
0x4008f0f6 <rtc_digital_lp_mode+42>: s32i.n	a10, a8, 0
/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0; internal SRAM 4 force power down*/
/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0; internal SRAM 3 force power down*/
/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0; internal SRAM 2 force power down*/
/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0; internal SRAM 1 force power down*/
/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0; internal SRAM 0 force power down*/
/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0; ROM force power down*/

0x4008f0f8 <rtc_digital_lp_mode+44>: movi.n	a11, 0
0x4008f0fa <rtc_digital_lp_mode+46>: l32r	a10, 0x4008efb4  /* a10 = 0x3ff000cc */
0x4008f0fd <rtc_digital_lp_mode+49>: memw
0x4008f100 <rtc_digital_lp_mode+52>: s32i.n	a11, a12, 0  /* set DPORT_PERIP_CLK_EN_REG to 0 */
#define DR_REG_DPORT_BASE                       0x3ff00000
#define DPORT_PERIP_CLK_EN_REG          (DR_REG_DPORT_BASE + 0x0C0)
#define DPORT_WIFI_CLK_EN_REG          (DR_REG_DPORT_BASE + 0x0CC)

0x4008f102 <rtc_digital_lp_mode+54>: memw
0x4008f105 <rtc_digital_lp_mode+57>: s32i.n	a11, a10, 0  /* set DPORT_WIFI_CLK_EN_REG to 0 */
0x4008f107 <rtc_digital_lp_mode+59>: memw

0x4008f10a <rtc_digital_lp_mode+62>: l32i.n	a13, a10, 0  /* read DPORT_WIFI_CLK_EN_REG */
0x4008f10c <rtc_digital_lp_mode+64>: movi	a12, -65  /* a12 = 0xffff ffbf */
0x4008f10f <rtc_digital_lp_mode+67>: l32r	a11, 0x4008efb8  /* a11 = 0x3ff000d0 */
0x4008f112 <rtc_digital_lp_mode+70>: and	a12, a13, a12  /* clear BIT[6] */
0x4008f115 <rtc_digital_lp_mode+73>: memw
0x4008f118 <rtc_digital_lp_mode+76>: s32i.n	a12, a10, 0
0x4008f11a <rtc_digital_lp_mode+78>: memw
/* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */

0x4008f11d <rtc_digital_lp_mode+81>: l32i.n	a12, a11, 0  /* read DPORT_WIFI_RST_EN_REG */
0x4008f11f <rtc_digital_lp_mode+83>: movi.n	a10, 4
0x4008f121 <rtc_digital_lp_mode+85>: or	a10, a12, a10  /* set BIT[2], DPORT_MAC_RST */
0x4008f124 <rtc_digital_lp_mode+88>: memw
0x4008f127 <rtc_digital_lp_mode+91>: s32i.n	a10, a11, 0
0x4008f129 <rtc_digital_lp_mode+93>: memw

0x4008f12c <rtc_digital_lp_mode+96>: l32i.n	a11, a9, 0  /* read RTC_CNTL_DIG_ISO_REG */
0x4008f12e <rtc_digital_lp_mode+98>: l32r	a10, 0x400865e0  /* a10 = 0x10000000 */
0x4008f131 <rtc_digital_lp_mode+101>: or	a11, a11, a10  /* set BIT[28] */
0x4008f134 <rtc_digital_lp_mode+104>: memw
0x4008f137 <rtc_digital_lp_mode+107>: s32i.n	a11, a9, 0
0x4008f139 <rtc_digital_lp_mode+109>: memw
/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0; wifi force ISO*/

0x4008f13c <rtc_digital_lp_mode+112>: l32i.n	a12, a8, 0  /* read RTC_CNTL_DIG_PWC_REG */
0x4008f13e <rtc_digital_lp_mode+114>: l32r	a11, 0x40087268  /* a11 = 0x00020000 */
0x4008f141 <rtc_digital_lp_mode+117>: l32r	a9, 0x4008e53c  /* a9 = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */
0x4008f144 <rtc_digital_lp_mode+120>: or	a11, a12, a11  /* set BIT[17] */
0x4008f147 <rtc_digital_lp_mode+123>: memw
0x4008f14a <rtc_digital_lp_mode+126>: s32i.n	a11, a8, 0
0x4008f14c <rtc_digital_lp_mode+128>: memw
/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0; wifi force power down*/

0x4008f14f <rtc_digital_lp_mode+131>: l32i.n	a12, a9, 0  /* read RTC_CNTL_CLK_CONF_REG */
0x4008f151 <rtc_digital_lp_mode+133>: l32r	a11, 0x400865dc  /* a11 = 0xe7ffffff */
0x4008f154 <rtc_digital_lp_mode+136>: l32r	a8, 0x400804e0  /* a8 = 0x3ff48000, RTC_CNTL_OPTIONS0_REG */
0x4008f157 <rtc_digital_lp_mode+139>: and	a11, a12, a11
0x4008f15a <rtc_digital_lp_mode+142>: or	a10, a11, a10  /* clear BIT[28:27] and set to 0x2 */
0x4008f15d <rtc_digital_lp_mode+145>: memw
0x4008f160 <rtc_digital_lp_mode+148>: s32i.n	a10, a9, 0
0x4008f162 <rtc_digital_lp_mode+150>: memw
/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0; SOC clock sel. 0: XTAL  1: PLL  2: CK8M  3: APLL*/

0x4008f165 <rtc_digital_lp_mode+153>: l32i.n	a10, a8, 0  /* read RTC_CNTL_OPTIONS0_REG */
0x4008f167 <rtc_digital_lp_mode+155>: l32r	a9, 0x4008ba54  /* a9 = 0xffffc0ff */
0x4008f16a <rtc_digital_lp_mode+158>: and	a9, a10, a9
0x4008f16d <rtc_digital_lp_mode+161>: l32r	a10, 0x4008e540  /* a10 = 0x00001500 */
0x4008f170 <rtc_digital_lp_mode+164>: or	a9, a9, a10  /* clear BIT[13:8] and set to 0x15 */
0x4008f173 <rtc_digital_lp_mode+167>: memw
0x4008f176 <rtc_digital_lp_mode+170>: s32i.n	a9, a8, 0
0x4008f178 <rtc_digital_lp_mode+172>: memw
/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1; crystall force power up*/
/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0; crystall force power down*/
/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0; BB_PLL force power up*/
/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0; BB_PLL force power down*/
/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0; BB_PLL_I2C force power up*/
/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0; BB_PLL _I2C force power down*/

0x4008f17b <rtc_digital_lp_mode+175>: l32i.n	a10, a8, 0  /* read RTC_CNTL_OPTIONS0_REG */
0x4008f17d <rtc_digital_lp_mode+177>: l32r	a9, 0x40087764  /* a9 = 0x00200000 */
0x4008f180 <rtc_digital_lp_mode+180>: or	a9, a10, a9  /* set BIT[21] */
0x4008f183 <rtc_digital_lp_mode+183>: memw
0x4008f186 <rtc_digital_lp_mode+186>: s32i.n	a9, a8, 0
0x4008f188 <rtc_digital_lp_mode+188>: memw
/* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0; BIAS_CORE force power down*/

0x4008f18b <rtc_digital_lp_mode+191>: l32i.n	a10, a8, 0  /* read RTC_CNTL_OPTIONS0_REG */
0x4008f18d <rtc_digital_lp_mode+193>: l32r	a9, 0x4008a52c  /* a9 = 0x00040000 */
0x4008f190 <rtc_digital_lp_mode+196>: or	a9, a10, a9  /* set BIT[18] */
0x4008f193 <rtc_digital_lp_mode+199>: memw
0x4008f196 <rtc_digital_lp_mode+202>: s32i.n	a9, a8, 0
/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0; BIAS_I2C force power down*/

0x4008f198 <rtc_digital_lp_mode+204>: retw.n














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