ESP32 RTC Sleep Prepare
来自Jack's Lab
1 rtc_get_xtal
RTC_CNTL_STORE5_REG is the External Xtal Frequency Register
0x4008fa70 <rtc_get_xtal>: entry a1, 32 0x4008fa73 <rtc_get_xtal+3>: l32r a11, 0x4008fa44 /* a11 = *(0x4008fa44) = 0x3ff480b0, RTC_CNTL_STORE4_REG */ 0x4008fa76 <rtc_get_xtal+6>: l32r a9, 0x4008fa68 /* a9 = *(0x4008fa68) = 0x3ff480b4, RTC_CNTL_STORE5_REG */ 0x4008fa79 <rtc_get_xtal+9>: memw 0x4008fa7c <rtc_get_xtal+12>: l32i.n a8, a11, 0 /* a8 = *(0x3ff480b0) = 0x00280028, read RTC_CNTL_STORE4_REG */ 0x4008fa7e <rtc_get_xtal+14>: memw 0x4008fa81 <rtc_get_xtal+17>: l32i.n a9, a9, 0 /* a9 = *(0x3ff480b4) = 0x4c4b4c4b, read RTC_CNTL_STORE5_REG */ 0x4008fa83 <rtc_get_xtal+19>: extui a10, a8, 0, 16 /* a10 = RTC_CNTL_STORE4_REG[15:0] */ 0x4008fa86 <rtc_get_xtal+22>: extui a12, a8, 16, 16 /* a12 = RTC_CNTL_STORE4_REG[31:16] */ 0x4008fa89 <rtc_get_xtal+25>: bne a10, a12, 0x4008fa95 /* branch; if (a10 != a12) */ 0x4008fa8c <rtc_get_xtal+28>: mov.n a2, a10 /* a2 = a10 = 0x28, a2 hold the return value */ 0x4008fa8e <rtc_get_xtal+30>: addi.n a8, a8, -1 /* a8 = RTC_CNTL_STORE4_REG - 1 */ 0x4008fa90 <rtc_get_xtal+32>: movi.n a10, -3 /* a10 = 0xFFFF FFFD */ 0x4008fa92 <rtc_get_xtal+34>: bgeu a10, a8, 0x4008fac2 /* branch to return; if (0xFFFF FFFD >= a8) */ 0x4008fa95 <rtc_get_xtal+37>: extui a8, a9, 0, 16 /* a8 = RTC_CNTL_STORE5_REG[15:0] */ 0x4008fa98 <rtc_get_xtal+40>: extui a10, a9, 16, 16 /* a10 = RTC_CNTL_STORE5_REG[31:16] */ 0x4008fa9b <rtc_get_xtal+43>: bne a8, a10, 0x4008fac2 /* branch; if (a8 != a10) */ 0x4008fa9e <rtc_get_xtal+46>: addi.n a9, a9, -1 /* a9 = RTC_CNTL_STORE5_REG - 1 */ 0x4008faa0 <rtc_get_xtal+48>: movi.n a10, -3 /* a10 = 0xFFFF FFFD */ 0x4008faa2 <rtc_get_xtal+50>: bltu a10, a9, 0x4008fac2 /* branch; if (0xFFFF FFFD < a9) */ 0x4008faa5 <rtc_get_xtal+53>: l32r a2, 0x4008fa6c /* a2 = *(0x4008fa6c) = 0x01c9c37f */ 0x4008faa8 <rtc_get_xtal+56>: slli a8, a8, 12 /* a8 = RTC_CNTL_STORE5_REG[15:0] << 12 */ 0x4008faab <rtc_get_xtal+59>: bgeu a2, a8, 0x4008fab8 /* branch; if (a2 >= a8) */ 0x4008faae <rtc_get_xtal+62>: l32r a8, 0x4008fa60 /* a8 = *(0x4008fa60) = 0x00280028 */ 0x4008fab1 <rtc_get_xtal+65>: movi.n a2, 40 0x4008fab3 <rtc_get_xtal+67>: j 0x4008fabd 0x4008fab6 <rtc_get_xtal+70>: 0x0000 <<--- Seems like this the gdb/openocd-esp32 bug 0x4008fab8 <rtc_get_xtal+72>: l32r a8, 0x4008fa64 /* a8 = *(0x4008fa64) = 0x001a001a */ 0x4008fabb <rtc_get_xtal+75>: movi.n a2, 26 0x4008fabd <rtc_get_xtal+77>: memw 0x4008fac0 <rtc_get_xtal+80>: s32i.n a8, a11, 0 0x4008fac2 <rtc_get_xtal+82>: retw.n
So:
uint32_t rtc_get_xtal();
2 rtc_slp_prep_lite
#define DEEP_SLEEP_PD_NORMAL BIT(0) /* Base deep sleep mode */ #define DEEP_SLEEP_PD_RTC_PERIPH BIT(1) /* Power down RTC peripherals */ #define DEEP_SLEEP_PD_RTC_SLOW_MEM BIT(2) /* Power down RTC SLOW memory */ #define DEEP_SLEEP_PD_RTC_FAST_MEM BIT(3) /* Power down RTC FAST memory */ /* * @brief Prepare for entering sleep mode * @param deep_slp DEEP_SLEEP_PD_ flags combined with OR (DEEP_SLEEP_PD_NORMAL must be included) * @param cpu_lp_mode for deep sleep, should be 0 */ void rtc_slp_prep_lite(uint32_t deep_slp, uint32_t cpu_lp_mode);
0x4008f5f8 <rtc_slp_prep_lite>: entry a1, 80 0x4008f5fb <rtc_slp_prep_lite+3>: movi.n a9, 4 /* a9 = 4 */ 0x4008f5fd <rtc_slp_prep_lite+5>: movi.n a13, 0 /* a13 = 0 */ 0x4008f5ff <rtc_slp_prep_lite+7>: mov.n a10, a9 /* a10 = 4 */ 0x4008f601 <rtc_slp_prep_lite+9>: movnez a10, a13, a3 /* a10 = a13 = 0, if (a3 != 0) */ 0x4008f604 <rtc_slp_prep_lite+12>: movi.n a8, 2 /* a8 = 2 */ 0x4008f606 <rtc_slp_prep_lite+14>: mov.n a11, a13 /* a11 = a13 = 0 */ 0x4008f608 <rtc_slp_prep_lite+16>: extui a12, a2, 0, 1 /* a12 = a2[0] */ 0x4008f60b <rtc_slp_prep_lite+19>: movnez a11, a8, a3 /* a11 = a8 = 2, if (a3 != 0) */ 0x4008f60e <rtc_slp_prep_lite+22>: and a9, a2, a9 /* a9 = a2 & a9, a2 is the 1st param deep_slp */ 0x4008f611 <rtc_slp_prep_lite+25>: and a8, a2, a8 /* a8 = a2 & a8 */ 0x4008f614 <rtc_slp_prep_lite+28>: s32i.n a10, a1, 28 0x4008f616 <rtc_slp_prep_lite+30>: movi.n a14, 16 0x4008f618 <rtc_slp_prep_lite+32>: l32r a10, 0x4008f5f4 /* a10 = *(0x4008f5f4 ) = 0xdd000000 */ 0x4008f61b <rtc_slp_prep_lite+35>: movi.n a15, 8 0x4008f61d <rtc_slp_prep_lite+37>: s32i.n a12, a1, 16 0x4008f61f <rtc_slp_prep_lite+39>: s32i.n a9, a1, 0 0x4008f621 <rtc_slp_prep_lite+41>: s32i.n a8, a1, 4 0x4008f623 <rtc_slp_prep_lite+43>: s32i.n a13, a1, 8 0x4008f625 <rtc_slp_prep_lite+45>: s32i.n a13, a1, 12 0x4008f627 <rtc_slp_prep_lite+47>: s32i.n a13, a1, 20 0x4008f629 <rtc_slp_prep_lite+49>: s32i.n a3, a1, 24 0x4008f62b <rtc_slp_prep_lite+51>: s32i.n a13, a1, 32 0x4008f62d <rtc_slp_prep_lite+53>: s32i.n a13, a1, 36 0x4008f62f <rtc_slp_prep_lite+55>: s32i.n a13, a1, 40 0x4008f631 <rtc_slp_prep_lite+57>: mov.n a12, a13 0x4008f633 <rtc_slp_prep_lite+59>: and a14, a2, a14 0x4008f636 <rtc_slp_prep_lite+62>: and a15, a2, a15 0x4008f639 <rtc_slp_prep_lite+65>: call8 0x4008f248 <rtc_slp_prep> 0x4008f63c <rtc_slp_prep_lite+68>: retw.n
- cpu_lp_mode == 0 (deep sleep), the parameters of rtc_slp_prep()
- 1st param, a10 = 0xdd000000
- 2nd param, a11 = 0 /* SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL */
- 3rd param, a12 = 0
- a13 = 0
- a14 = deep_slp & 0x10
- a15 = deep_slp & 0x8
- cpu_lp_mode != 0, the parameters of rtc_slp_prep()
- 1st param, a10 = 0xdd000000
- 2nd param, a11 = 2
- 3rd param, a12 = 0
- a13 = 0
- a14 = deep_slp & 0x10
- a15 = deep_slp & 0x8
3 rtc_slp_prep
(gdb) x /345i rtc_slp_prep 0x4008f1c4 <rtc_slp_prep>: entry a1, 48 0x4008f1c7 <rtc_slp_prep+3>: call8 0x4008f9ec <rtc_get_xtal> 0x4008f1ca <rtc_slp_prep+6>: l32r a8, 0x4008e53c /* a8 = *(0x4008e5c0) = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */ 0x4008f1cd <rtc_slp_prep+9>: l32r a9, 0x400865dc /* a9 = *(0x40086674) = 0xe7ffffff */ 0x4008f1d0 <rtc_slp_prep+12>: memw 0x4008f1d3 <rtc_slp_prep+15>: l32i a12, a8, 0 /* a12 = read RTC_CNTL_CLK_CONF_REG = 0x2d580210 */ 0x4008f1d6 <rtc_slp_prep+18>: extui a11, a3, 0, 2 /* a11 = p2[1:0], 2nd_param of rtc_slp_prep */ 0x4008f1d9 <rtc_slp_prep+21>: slli a11, a11, 27 0x4008f1dc <rtc_slp_prep+24>: and a9, a12, a9 0x4008f1df <rtc_slp_prep+27>: or a9, a11, a9 /* set BIT[28:27] of RTC_CNTL_CLK_CONF_REG */ 0x4008f1e2 <rtc_slp_prep+30>: memw 0x4008f1e5 <rtc_slp_prep+33>: s32i a9, a8, 0 /* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0; SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL */ 0x4008f1e8 <rtc_slp_prep+36>: or a13, a10, a10 /* a10 is the return value of rtc_get_xtal() */ 0x4008f1eb <rtc_slp_prep+39>: bnei a3, 1, 0x4008f238 <rtc_slp_prep+116> ------> If (a3 != 1), not the PLL clock, jump 0x4008f1ee <rtc_slp_prep+42>: l32r a3, 0x4008e57c /* a3 = 0x3ff4801c, RTC_CNTL_TIMER1_REG */ 0x4008f1f1 <rtc_slp_prep+45>: l32r a8, 0x40084ce0 /* a8 = 0x00ffffff, BIT[31:24] */ 0x4008f1f4 <rtc_slp_prep+48>: memw 0x4008f1f7 <rtc_slp_prep+51>: l32i.n a9, a3, 0 0x4008f1f9 <rtc_slp_prep+53>: and a8, a9, a8 0x4008f1fc <rtc_slp_prep+56>: l32r a9, 0x4008f19c /* a9 = 0x14000000 */ 0x4008f1ff <rtc_slp_prep+59>: or a8, a8, a9 /* set BIT[31:24] = 0x14 */ 0x4008f202 <rtc_slp_prep+62>: memw 0x4008f205 <rtc_slp_prep+65>: s32i.n a8, a3, 0 /* Write back to RTC_CNTL_TIMER1_REG */ 0x4008f207 <rtc_slp_prep+67>: memw /* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; PLL wait cycles in slow_clk_rtc */ 0x4008f20a <rtc_slp_prep+70>: l32i.n a9, a3, 0 0x4008f20c <rtc_slp_prep+72>: l32r a8, 0x4008e580 /* a8 = 0xff003fff, BIT[23:14] */ 0x4008f20f <rtc_slp_prep+75>: and a8, a9, a8 0x4008f212 <rtc_slp_prep+78>: l32r a9, 0x4008f1a0 /* a9 = 0x00050000 */ 0x4008f215 <rtc_slp_prep+81>: or a8, a8, a9 /* set BIT[23:14] = 0x14 */ 0x4008f218 <rtc_slp_prep+84>: memw 0x4008f21b <rtc_slp_prep+87>: s32i.n a8, a3, 0 0x4008f21d <rtc_slp_prep+89>: memw /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; XTAL wait cycles in slow_clk_rtc */ 0x4008f220 <rtc_slp_prep+92>: l32i.n a9, a3, 0 0x4008f222 <rtc_slp_prep+94>: l32r a8, 0x4008e584 /* a8 = 0xffffc03f, BIT[13:6] */ 0x4008f225 <rtc_slp_prep+97>: and a8, a9, a8 0x4008f228 <rtc_slp_prep+100>: movi a9, 0x500 0x4008f22b <rtc_slp_prep+103>: or a8, a8, a9 /* set BIT[13:6] = 0x14 */ 0x4008f22e <rtc_slp_prep+106>: memw 0x4008f231 <rtc_slp_prep+109>: s32i.n a8, a3, 0 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; CK8M wait cycles in slow_clk_rtc */ 0x4008f233 <rtc_slp_prep+111>: j 0x4008f34e <rtc_slp_prep+394> /* jump to process the PLL continously */ 0x4008f235 <rtc_slp_prep+113>: ill (0x0000) <------------- openocd/gdb bug 0x4008f238 <rtc_slp_prep+116>: bnez a3, 0x4008f298 <rtc_slp_prep+212> /* if (a3 != 0), not the XTAL clock, jump */ ---------> /* Following should be related to the XTAL clock */ 0x4008f23b <rtc_slp_prep+119>: l32r a3, 0x4008e57c /* a3 = 0x3ff4801c, RTC_CNTL_TIMER1_REG */ 0x4008f23e <rtc_slp_prep+122>: l32r a8, 0x40084ce0 /* a8 = 0x00ffffff, BIT[31:24] */ 0x4008f241 <rtc_slp_prep+125>: memw 0x4008f244 <rtc_slp_prep+128>: l32i.n a9, a3, 0 0x4008f246 <rtc_slp_prep+130>: and a8, a9, a8 0x4008f249 <rtc_slp_prep+133>: l32r a9, 0x40084c80 /* a9 = 0x01000000 */ 0x4008f24c <rtc_slp_prep+136>: or a8, a8, a9 /* set BIT[31:24] = 0x1 */ 0x4008f24f <rtc_slp_prep+139>: memw 0x4008f252 <rtc_slp_prep+142>: s32i.n a8, a3, 0 0x4008f254 <rtc_slp_prep+144>: memw /* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; PLL wait cycles in slow_clk_rtc */ 0x4008f257 <rtc_slp_prep+147>: l32i.n a9, a3, 0 0x4008f259 <rtc_slp_prep+149>: l32r a8, 0x4008e580 /* a8 = 0xff003fff, BIT[23:14] */ 0x4008f25c <rtc_slp_prep+152>: and a8, a9, a8 0x4008f25f <rtc_slp_prep+155>: l32r a9, 0x4008f1a0 /* a9 = 0x00050000 */ 0x4008f262 <rtc_slp_prep+158>: or a8, a8, a9 /* set BIT[23:14] = 0x14 */ 0x4008f265 <rtc_slp_prep+161>: memw 0x4008f268 <rtc_slp_prep+164>: s32i.n a8, a3, 0 0x4008f26a <rtc_slp_prep+166>: memw /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; XTAL wait cycles in slow_clk_rtc */ 0x4008f26d <rtc_slp_prep+169>: l32i.n a9, a3, 0 0x4008f26f <rtc_slp_prep+171>: l32r a8, 0x4008e584 /* a8 = 0xffffc03f, BIT[13:6] */ 0x4008f272 <rtc_slp_prep+174>: and a8, a9, a8 0x4008f275 <rtc_slp_prep+177>: movi a9, 0x500 0x4008f278 <rtc_slp_prep+180>: or a8, a8, a9 /* set BIT[13:6] = 0x14 */ 0x4008f27b <rtc_slp_prep+183>: memw 0x4008f27e <rtc_slp_prep+186>: s32i.n a8, a3, 0 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; CK8M wait cycles in slow_clk_rtc */ 0x4008f280 <rtc_slp_prep+188>: s32i a13, a1, 0 /* store the a13 into stack */ 0x4008f283 <rtc_slp_prep+191>: l32r a8, 0x4008f1c0 /* a8 = 0x40008550, ets_update_cpu_frequency */ 0x4008f286 <rtc_slp_prep+194>: callx8 a8 /* ets_update_cpu_frequency(uint32_t ticks_per_us) */ /* a10 is the ticks_per_us, get from call rtc_get_xtal() */ 0x4008f289 <rtc_slp_prep+197>: l32i.n a13, a1, 0 /* restore a13 */ 0x4008f28b <rtc_slp_prep+199>: l32r a10, 0x40080574 /* a10 = 0x000f4240 */ 0x4008f28e <rtc_slp_prep+202>: mull a10, a13, a10 /* a10 = rtc_get_xtal() * 1000000 */ 0x4008f291 <rtc_slp_prep+205>: call8 0x4008fa40 <rtc_apb_freq_up> 0x4008f294 <rtc_slp_prep+208>: j 0x4008f34e <rtc_slp_prep+394> -----------------------> jump 394 0x4008f296 <rtc_slp_prep+210>: 0x0000 <-------------- openocd/gdb bug 0x4008f298 <rtc_slp_prep+212>: beqi a3, 2, 0x4008f29e <rtc_slp_prep+218> /* if (a3 == 2); CK8M clock, jump */ 0x4008f29b <rtc_slp_prep+215>: j 0x4008f34e <rtc_slp_prep+394> -------------------------> jump 394 /* Following is related to CK8M clock */ 0x4008f29e <rtc_slp_prep+218>: l32r a3, 0x4008f1a4 0x4008f2a1 <rtc_slp_prep+221>: l32r a8, 0x4008f050 0x4008f2a4 <rtc_slp_prep+224>: memw 0x4008f2a7 <rtc_slp_prep+227>: l32i a9, a3, 0 0x4008f2aa <rtc_slp_prep+230>: movi a10, 1 0x4008f2ad <rtc_slp_prep+233>: and a8, a9, a8 0x4008f2b0 <rtc_slp_prep+236>: l32r a9, 0x40084c00 0x4008f2b3 <rtc_slp_prep+239>: or a8, a8, a9 0x4008f2b6 <rtc_slp_prep+242>: memw 0x4008f2b9 <rtc_slp_prep+245>: s32i a8, a3, 0 0x4008f2bc <rtc_slp_prep+248>: memw 0x4008f2bf <rtc_slp_prep+251>: l32i.n a9, a3, 0 0x4008f2c1 <rtc_slp_prep+253>: l32r a8, 0x4008ba60 0x4008f2c4 <rtc_slp_prep+256>: and a8, a9, a8 0x4008f2c7 <rtc_slp_prep+259>: l32r a9, 0x40088a98 0x4008f2ca <rtc_slp_prep+262>: or a8, a8, a9 0x4008f2cd <rtc_slp_prep+265>: memw 0x4008f2d0 <rtc_slp_prep+268>: s32i.n a8, a3, 0 0x4008f2d2 <rtc_slp_prep+270>: memw 0x4008f2d5 <rtc_slp_prep+273>: l32i.n a9, a3, 0 0x4008f2d7 <rtc_slp_prep+275>: l32r a8, 0x4008f1a8 0x4008f2da <rtc_slp_prep+278>: and a8, a9, a8 0x4008f2dd <rtc_slp_prep+281>: movi a9, 0x200 0x4008f2e0 <rtc_slp_prep+284>: or a8, a8, a9 0x4008f2e3 <rtc_slp_prep+287>: memw 0x4008f2e6 <rtc_slp_prep+290>: s32i.n a8, a3, 0 0x4008f2e8 <rtc_slp_prep+292>: memw 0x4008f2eb <rtc_slp_prep+295>: l32i.n a9, a3, 0 0x4008f2ed <rtc_slp_prep+297>: movi a8, 0xfffffe00 0x4008f2f0 <rtc_slp_prep+300>: and a9, a9, a8 0x4008f2f3 <rtc_slp_prep+303>: or a9, a9, a10 0x4008f2f6 <rtc_slp_prep+306>: l32r a8, 0x4008e57c 0x4008f2f9 <rtc_slp_prep+309>: memw 0x4008f2fc <rtc_slp_prep+312>: s32i.n a9, a3, 0 0x4008f2fe <rtc_slp_prep+314>: memw 0x4008f301 <rtc_slp_prep+317>: l32i.n a9, a8, 0 0x4008f303 <rtc_slp_prep+319>: l32r a3, 0x40084ce0 0x4008f306 <rtc_slp_prep+322>: movi.n a10, 8 0x4008f308 <rtc_slp_prep+324>: and a3, a9, a3 0x4008f30b <rtc_slp_prep+327>: l32r a9, 0x40084c80 0x4008f30e <rtc_slp_prep+330>: or a3, a3, a9 0x4008f311 <rtc_slp_prep+333>: memw 0x4008f314 <rtc_slp_prep+336>: s32i.n a3, a8, 0 0x4008f316 <rtc_slp_prep+338>: memw 0x4008f319 <rtc_slp_prep+341>: l32i.n a9, a8, 0 0x4008f31b <rtc_slp_prep+343>: l32r a3, 0x4008e580 0x4008f31e <rtc_slp_prep+346>: and a3, a9, a3 0x4008f321 <rtc_slp_prep+349>: l32r a9, 0x4008f1ac 0x4008f324 <rtc_slp_prep+352>: or a3, a3, a9 0x4008f327 <rtc_slp_prep+355>: memw 0x4008f32a <rtc_slp_prep+358>: s32i.n a3, a8, 0 0x4008f32c <rtc_slp_prep+360>: memw 0x4008f32f <rtc_slp_prep+363>: l32i.n a9, a8, 0 0x4008f331 <rtc_slp_prep+365>: l32r a3, 0x4008e584 0x4008f334 <rtc_slp_prep+368>: and a3, a9, a3 0x4008f337 <rtc_slp_prep+371>: movi a9, 0x500 0x4008f33a <rtc_slp_prep+374>: or a3, a3, a9 0x4008f33d <rtc_slp_prep+377>: memw 0x4008f340 <rtc_slp_prep+380>: s32i.n a3, a8, 0 0x4008f342 <rtc_slp_prep+382>: l32r a8, 0x4008f1c0 0x4008f345 <rtc_slp_prep+385>: callx8 a8 0x4008f348 <rtc_slp_prep+388>: l32r a10, 0x4008f1b0 0x4008f34b <rtc_slp_prep+391>: call8 0x4008fa40 <rtc_apb_freq_up> >>>>>>>>>>>>>>>>>>>>>>>> 0x4008f34e <rtc_slp_prep+394>: movi a10, 0 0x4008f351 <rtc_slp_prep+397>: call8 0x4008fa5c <rtc_uart_div_modify> 0x4008f354 <rtc_slp_prep+400>: l32r a8, 0x4008e4d4 0x4008f357 <rtc_slp_prep+403>: movi a3, -1 0x4008f35a <rtc_slp_prep+406>: memw 0x4008f35d <rtc_slp_prep+409>: l32i a9, a8, 0 0x4008f360 <rtc_slp_prep+412>: xor a2, a3, a2 0x4008f363 <rtc_slp_prep+415>: and a2, a2, a9 0x4008f366 <rtc_slp_prep+418>: l32r a3, 0x4008bff8 0x4008f369 <rtc_slp_prep+421>: memw 0x4008f36c <rtc_slp_prep+424>: s32i.n a2, a8, 0 0x4008f36e <rtc_slp_prep+426>: memw 0x4008f371 <rtc_slp_prep+429>: l32i.n a8, a3, 0 0x4008f373 <rtc_slp_prep+431>: l32r a2, 0x4008af28 0x4008f376 <rtc_slp_prep+434>: and a2, a8, a2 0x4008f379 <rtc_slp_prep+437>: memw 0x4008f37c <rtc_slp_prep+440>: s32i.n a2, a3, 0 0x4008f37e <rtc_slp_prep+442>: l32r a2, 0x4008e2f0 0x4008f381 <rtc_slp_prep+445>: beqz.n a4, 0x4008f395 <rtc_slp_prep+465> 0x4008f383 <rtc_slp_prep+447>: memw 0x4008f386 <rtc_slp_prep+450>: l32i.n a4, a2, 0 0x4008f388 <rtc_slp_prep+452>: movi.n a3, 16 0x4008f38a <rtc_slp_prep+454>: or a3, a4, a3 0x4008f38d <rtc_slp_prep+457>: memw 0x4008f390 <rtc_slp_prep+460>: s32i.n a3, a2, 0 0x4008f392 <rtc_slp_prep+462>: j 0x4008f3a4 <rtc_slp_prep+480> 0x4008f395 <rtc_slp_prep+465>: memw 0x4008f398 <rtc_slp_prep+468>: l32i.n a4, a2, 0 0x4008f39a <rtc_slp_prep+470>: movi.n a3, -17 0x4008f39c <rtc_slp_prep+472>: and a3, a4, a3 0x4008f39f <rtc_slp_prep+475>: memw 0x4008f3a2 <rtc_slp_prep+478>: s32i.n a3, a2, 0 0x4008f3a4 <rtc_slp_prep+480>: l32r a8, 0x4008e2f4 0x4008f3a7 <rtc_slp_prep+483>: memw 0x4008f3aa <rtc_slp_prep+486>: l32i.n a4, a8, 0 0x4008f3ac <rtc_slp_prep+488>: beqz.n a5, 0x4008f3bc <rtc_slp_prep+504> 0x4008f3ae <rtc_slp_prep+490>: l32r a3, 0x4008f1b4 0x4008f3b1 <rtc_slp_prep+493>: or a3, a4, a3 0x4008f3b4 <rtc_slp_prep+496>: memw 0x4008f3b7 <rtc_slp_prep+499>: s32i.n a3, a8, 0 0x4008f3b9 <rtc_slp_prep+501>: j 0x4008f3c7 <rtc_slp_prep+515> 0x4008f3bc <rtc_slp_prep+504>: l32r a3, 0x4008e594 0x4008f3bf <rtc_slp_prep+507>: and a3, a4, a3 0x4008f3c2 <rtc_slp_prep+510>: memw 0x4008f3c5 <rtc_slp_prep+513>: s32i.n a3, a8, 0 0x4008f3c7 <rtc_slp_prep+515>: memw 0x4008f3ca <rtc_slp_prep+518>: l32i.n a4, a8, 0 0x4008f3cc <rtc_slp_prep+520>: beqz.n a6, 0x4008f3dc <rtc_slp_prep+536> 0x4008f3ce <rtc_slp_prep+522>: movi a3, 0x240 0x4008f3d1 <rtc_slp_prep+525>: or a3, a4, a3 0x4008f3d4 <rtc_slp_prep+528>: memw 0x4008f3d7 <rtc_slp_prep+531>: s32i.n a3, a8, 0 0x4008f3d9 <rtc_slp_prep+533>: j 0x4008f3e7 <rtc_slp_prep+547> 0x4008f3dc <rtc_slp_prep+536>: movi a3, 0xfffffdbf 0x4008f3df <rtc_slp_prep+539>: and a3, a4, a3 0x4008f3e2 <rtc_slp_prep+542>: memw 0x4008f3e5 <rtc_slp_prep+545>: s32i.n a3, a8, 0 0x4008f3e7 <rtc_slp_prep+547>: memw 0x4008f3ea <rtc_slp_prep+550>: l32i.n a4, a8, 0 0x4008f3ec <rtc_slp_prep+552>: beqz.n a7, 0x4008f41c <rtc_slp_prep+600> 0x4008f3ee <rtc_slp_prep+554>: l32r a3, 0x400878b8 0x4008f3f1 <rtc_slp_prep+557>: or a3, a4, a3 0x4008f3f4 <rtc_slp_prep+560>: memw 0x4008f3f7 <rtc_slp_prep+563>: s32i.n a3, a8, 0 0x4008f3f9 <rtc_slp_prep+565>: memw 0x4008f3fc <rtc_slp_prep+568>: l32i.n a4, a8, 0 0x4008f3fe <rtc_slp_prep+570>: l32r a3, 0x4008db64 0x4008f401 <rtc_slp_prep+573>: and a3, a4, a3 0x4008f404 <rtc_slp_prep+576>: memw 0x4008f407 <rtc_slp_prep+579>: s32i.n a3, a8, 0 0x4008f409 <rtc_slp_prep+581>: memw 0x4008f40c <rtc_slp_prep+584>: l32i.n a4, a8, 0 0x4008f40e <rtc_slp_prep+586>: movi.n a3, -2 0x4008f410 <rtc_slp_prep+588>: and a3, a4, a3 0x4008f413 <rtc_slp_prep+591>: memw 0x4008f416 <rtc_slp_prep+594>: s32i.n a3, a8, 0 0x4008f418 <rtc_slp_prep+596>: j 0x4008f446 <rtc_slp_prep+642> 0x4008f41b <rtc_slp_prep+599>: lsi f0, a1, 24 0x4008f41e <rtc_slp_prep+602>: lsi f12, a0, 208 0x4008f421 <rtc_slp_prep+605>: or a12, a0, a1 0x4008f424 <rtc_slp_prep+608>: lsx f3, a9, a0 0x4008f427 <rtc_slp_prep+611>: memw 0x4008f42a <rtc_slp_prep+614>: l32i.n a4, a8, 0 0x4008f42c <rtc_slp_prep+616>: l32r a3, 0x4008063c 0x4008f42f <rtc_slp_prep+619>: or a3, a4, a3 0x4008f432 <rtc_slp_prep+622>: memw 0x4008f435 <rtc_slp_prep+625>: s32i.n a3, a8, 0 0x4008f437 <rtc_slp_prep+627>: memw 0x4008f43a <rtc_slp_prep+630>: l32i.n a4, a8, 0 0x4008f43c <rtc_slp_prep+632>: movi.n a3, 1 0x4008f43e <rtc_slp_prep+634>: or a3, a4, a3 0x4008f441 <rtc_slp_prep+637>: memw 0x4008f444 <rtc_slp_prep+640>: s32i.n a3, a8, 0 0x4008f446 <rtc_slp_prep+642>: l32i.n a3, a1, 48 0x4008f448 <rtc_slp_prep+644>: memw 0x4008f44b <rtc_slp_prep+647>: l32i.n a4, a8, 0 0x4008f44d <rtc_slp_prep+649>: beqz.n a3, 0x4008f47c <rtc_slp_prep+696> 0x4008f44f <rtc_slp_prep+651>: l32r a3, 0x40087268 0x4008f452 <rtc_slp_prep+654>: or a3, a4, a3 0x4008f455 <rtc_slp_prep+657>: memw 0x4008f458 <rtc_slp_prep+660>: s32i.n a3, a8, 0 0x4008f45a <rtc_slp_prep+662>: memw 0x4008f45d <rtc_slp_prep+665>: l32i.n a4, a8, 0 0x4008f45f <rtc_slp_prep+667>: l32r a3, 0x4008c0e4 0x4008f462 <rtc_slp_prep+670>: and a3, a4, a3 0x4008f465 <rtc_slp_prep+673>: memw 0x4008f468 <rtc_slp_prep+676>: s32i.n a3, a8, 0 0x4008f46a <rtc_slp_prep+678>: memw 0x4008f46d <rtc_slp_prep+681>: l32i.n a4, a8, 0 0x4008f46f <rtc_slp_prep+683>: movi.n a3, -5 0x4008f471 <rtc_slp_prep+685>: and a3, a4, a3 0x4008f474 <rtc_slp_prep+688>: memw 0x4008f477 <rtc_slp_prep+691>: s32i.n a3, a8, 0 0x4008f479 <rtc_slp_prep+693>: j 0x4008f4a6 <rtc_slp_prep+738> 0x4008f47c <rtc_slp_prep+696>: l32r a3, 0x400855e0 0x4008f47f <rtc_slp_prep+699>: and a3, a4, a3 0x4008f482 <rtc_slp_prep+702>: memw 0x4008f485 <rtc_slp_prep+705>: s32i.n a3, a8, 0 0x4008f487 <rtc_slp_prep+707>: memw 0x4008f48a <rtc_slp_prep+710>: l32i.n a4, a8, 0 0x4008f48c <rtc_slp_prep+712>: l32r a3, 0x40088a98 0x4008f48f <rtc_slp_prep+715>: or a3, a4, a3 0x4008f492 <rtc_slp_prep+718>: memw 0x4008f495 <rtc_slp_prep+721>: s32i.n a3, a8, 0 0x4008f497 <rtc_slp_prep+723>: memw 0x4008f49a <rtc_slp_prep+726>: l32i.n a4, a8, 0 0x4008f49c <rtc_slp_prep+728>: movi.n a3, 4 0x4008f49e <rtc_slp_prep+730>: or a3, a4, a3 0x4008f4a1 <rtc_slp_prep+733>: memw 0x4008f4a4 <rtc_slp_prep+736>: s32i.n a3, a8, 0 0x4008f4a6 <rtc_slp_prep+738>: l32i.n a3, a1, 52 0x4008f4a8 <rtc_slp_prep+740>: memw 0x4008f4ab <rtc_slp_prep+743>: l32i.n a4, a8, 0 0x4008f4ad <rtc_slp_prep+745>: beqz.n a3, 0x4008f4bd <rtc_slp_prep+761> 0x4008f4af <rtc_slp_prep+747>: l32r a3, 0x4008ada0 0x4008f4b2 <rtc_slp_prep+750>: or a3, a4, a3 0x4008f4b5 <rtc_slp_prep+753>: memw 0x4008f4b8 <rtc_slp_prep+756>: s32i.n a3, a8, 0 0x4008f4ba <rtc_slp_prep+758>: j 0x4008f4c8 <rtc_slp_prep+772> 0x4008f4bd <rtc_slp_prep+761>: l32r a3, 0x400855d8 0x4008f4c0 <rtc_slp_prep+764>: and a3, a4, a3 0x4008f4c3 <rtc_slp_prep+767>: memw 0x4008f4c6 <rtc_slp_prep+770>: s32i.n a3, a8, 0 0x4008f4c8 <rtc_slp_prep+772>: l32i.n a3, a1, 56 0x4008f4ca <rtc_slp_prep+774>: memw 0x4008f4cd <rtc_slp_prep+777>: l32i.n a4, a2, 0 0x4008f4cf <rtc_slp_prep+779>: beqz.n a3, 0x4008f4e0 <rtc_slp_prep+796> 0x4008f4d1 <rtc_slp_prep+781>: l32r a3, 0x400805fc 0x4008f4d4 <rtc_slp_prep+784>: or a3, a4, a3 0x4008f4d7 <rtc_slp_prep+787>: memw 0x4008f4da <rtc_slp_prep+790>: s32i.n a3, a2, 0 0x4008f4dc <rtc_slp_prep+792>: j 0x4008f4eb <rtc_slp_prep+807> 0x4008f4df <rtc_slp_prep+795>: movltz.s f3, f1, a0 0x4008f4e2 <rtc_slp_prep+798>: lsi f14, a0, 208 0x4008f4e5 <rtc_slp_prep+801>: or a12, a0, a1 0x4008f4e8 <rtc_slp_prep+804>: andb b3, b9, b0 0x4008f4eb <rtc_slp_prep+807>: l32i.n a3, a1, 60 0x4008f4ed <rtc_slp_prep+809>: memw 0x4008f4f0 <rtc_slp_prep+812>: l32i.n a4, a2, 0 0x4008f4f2 <rtc_slp_prep+814>: beqz.n a3, 0x4008f505 <rtc_slp_prep+833> 0x4008f4f4 <rtc_slp_prep+816>: l32r a3, 0x4008f1b8 0x4008f4f7 <rtc_slp_prep+819>: or a3, a4, a3 0x4008f4fa <rtc_slp_prep+822>: memw 0x4008f4fd <rtc_slp_prep+825>: s32i.n a3, a2, 0 0x4008f4ff <rtc_slp_prep+827>: j 0x4008f510 <rtc_slp_prep+844> 0x4008f502 <rtc_slp_prep+830>: ill 0x4008f505 <rtc_slp_prep+833>: l32r a3, 0x4008f1bc 0x4008f508 <rtc_slp_prep+836>: and a3, a4, a3 0x4008f50b <rtc_slp_prep+839>: memw 0x4008f50e <rtc_slp_prep+842>: s32i.n a3, a2, 0 0x4008f510 <rtc_slp_prep+844>: l32i a3, a1, 64 0x4008f513 <rtc_slp_prep+847>: beqz.n a3, 0x4008f530 <rtc_slp_prep+876> 0x4008f515 <rtc_slp_prep+849>: call8 0x4008f054 <rtc_deep_slp_conf> 0x4008f518 <rtc_slp_prep+852>: l32r a2, 0x400804e0 0x4008f51b <rtc_slp_prep+855>: l32r a3, 0x4008c0e4 0x4008f51e <rtc_slp_prep+858>: memw 0x4008f521 <rtc_slp_prep+861>: l32i.n a4, a2, 0 0x4008f523 <rtc_slp_prep+863>: and a3, a4, a3 0x4008f526 <rtc_slp_prep+866>: memw 0x4008f529 <rtc_slp_prep+869>: s32i.n a3, a2, 0 0x4008f52b <rtc_slp_prep+871>: j 0x4008f556 <rtc_slp_prep+914> 0x4008f52e <rtc_slp_prep+874>: sub a0, a0, a0 0x4008f531 <rtc_slp_prep+877>: lsi f2, a0, 0x148 0x4008f534 <rtc_slp_prep+880>: l8ui a2, a0, 65 0x4008f537 <rtc_slp_prep+883>: addi a14, a3, 49 0x4008f53a <rtc_slp_prep+886>: s32i.n a14, a3, 48 0x4008f53c <rtc_slp_prep+888>: and a4, a5, a4 0x4008f53f <rtc_slp_prep+891>: memw 0x4008f542 <rtc_slp_prep+894>: s32i a4, a2, 0 0x4008f545 <rtc_slp_prep+897>: memw 0x4008f548 <rtc_slp_prep+900>: l32i a4, a3, 0 0x4008f54b <rtc_slp_prep+903>: l32r a2, 0x40088a98 0x4008f54e <rtc_slp_prep+906>: or a2, a4, a2 0x4008f551 <rtc_slp_prep+909>: memw 0x4008f554 <rtc_slp_prep+912>: s32i.n a2, a3, 0 0x4008f556 <rtc_slp_prep+914>: l32i a10, a1, 76 0x4008f559 <rtc_slp_prep+917>: l32i a11, a1, 80 0x4008f55c <rtc_slp_prep+920>: l32i a12, a1, 84 0x4008f55f <rtc_slp_prep+923>: l32i a13, a1, 88 0x4008f562 <rtc_slp_prep+926>: call8 0x4008fe30 <rtc_dbias_cfg> 0x4008f565 <rtc_slp_prep+929>: l32i a2, a1, 72 0x4008f568 <rtc_slp_prep+932>: beqz.n a2, 0x4008f56d <rtc_slp_prep+937> 0x4008f56a <rtc_slp_prep+934>: call8 0x4008f0cc <rtc_digital_lp_mode> 0x4008f56d <rtc_slp_prep+937>: retw.n
