2016年12月4日 (日) 18:53的版本

1 Overview

0x40090da0 <rtc_smoke_detector_demo>:   entry   a1, 48
0x40090da3 <rtc_smoke_detector_demo+3>: mov.n   a10, a1
0x40090da5 <rtc_smoke_detector_demo+5>: call8   0x40090790

0x40090da8 <rtc_smoke_detector_demo+8>: movi.n  a10, 0
0x40090daa <rtc_smoke_detector_demo+10>: l32i.n  a4, a1, 0
0x40090dac <rtc_smoke_detector_demo+12>: call8   0x4008eb70 <rtc_init_lite>
0x40090daf <rtc_smoke_detector_demo+15>: call8   0x4008f010 <rtc_sdreg_off>

0x40090db2 <rtc_smoke_detector_demo+18>: l32r    a2, 0x40087268  /* a2 = *(0x40087268) = 0x00020000 */
0x40090db5 <rtc_smoke_detector_demo+21>: mov.n   a10, a2
0x40090db7 <rtc_smoke_detector_demo+23>: call8   0x400dcef8 <slp_pad_ctrl>  /* slp_pad_ctrl(1<<17) */

0x40090dba <rtc_smoke_detector_demo+26>: mov.n   a10, a2
0x40090dbc <rtc_smoke_detector_demo+28>: movi.n  a11, 17
0x40090dbe <rtc_smoke_detector_demo+30>: call8   0x4008ef2c <rtc_cmd_ext_wakeup>  /* rtc_cmd_ext_wakeup(1<<17, 17) */

0x40090dc1 <rtc_smoke_detector_demo+33>: movi.n  a11, 5
0x40090dc3 <rtc_smoke_detector_demo+35>: movi.n  a10, 1
0x40090dc5 <rtc_smoke_detector_demo+37>: call8   0x400dcf00 <rtc_smoke_detector_in_sleep> /* rtc_smoke_detector_in_sleep(1, 5) */

0x40090dc8 <rtc_smoke_detector_demo+40>: l32r    a8, 0x40090d90  /* a8 = *(0x40090d90) = 0x3ff61774, in RTCMEM0 */
0x40090dcb <rtc_smoke_detector_demo+43>: l32r    a2, 0x40090c14  /* a2 = *(0x40090c14) = 0x00001388 = 5000 */
0x40090dce <rtc_smoke_detector_demo+46>: l32r    a3, 0x40090d94  /* a3 = *(0x40090d94) = 0x3f403de4 */
0x40090dd1 <rtc_smoke_detector_demo+49>: memw
0x40090dd4 <rtc_smoke_detector_demo+52>: s32i.n  a2, a8, 0  /* write 0x00001388 to *(0x3ff61774) */

/* a3 = 0x3f403de4, *a3 = "\n", '=' <repeats 41 times>, "\n" */
0x40090dd6 <rtc_smoke_detector_demo+54>: mov.n   a10, a3
0x40090dd8 <rtc_smoke_detector_demo+56>: call8   0x400d8b7c <rtc_printf>

/* a10 = *(40090d98) = 0x3f403e10, *a10 = " Smoke Detector Demo during deep sleep... " */
0x40090ddb <rtc_smoke_detector_demo+59>: l32r    a10, 0x40090d98
0x40090dde <rtc_smoke_detector_demo+62>: call8   0x400d8b7c <rtc_printf>

/* a3 = 0x3f403de4, *a3 = "\n", '=' <repeats 41 times>, "\n" */
0x40090de1 <rtc_smoke_detector_demo+65>: mov.n   a10, a3
0x40090de3 <rtc_smoke_detector_demo+67>: call8   0x400d8b7c <rtc_printf>

0x40090de6 <rtc_smoke_detector_demo+70>: l32r    a10, 0x40090d9c  /* a10 = *(0x40090d9c) = 0x00004e20 = 20000 */
0x40090de9 <rtc_smoke_detector_demo+73>: l32r    a8, 0x40080850   /* a8 = *(0x40080850)  = 0x40008534, ets_delay_us() */
0x40090dec <rtc_smoke_detector_demo+76>: callx8  a8  /* ets_delay_us(20000) */

0x40090def <rtc_smoke_detector_demo+79>: mov.n   a10, a2  /* a10 = 0x00001388 = 5000 */
0x40090df1 <rtc_smoke_detector_demo+81>: call8   0x40090234 <rtc_sar_sleep_timer_start>  /* rtc_sar_sleep_timer_start(5000) */
0x40090df4 <rtc_smoke_detector_demo+84>: l32r    a3, 0x4008f9c0  /* a3 = *(0x4008f9c0) = 0x3ff480b0, RTC_CNTL_STORE4_REG */
0x40090df7 <rtc_smoke_detector_demo+87>: l32r    a2, 0x4008f9e4  /* a2 = *(0x4008f9e4) = 0x3ff480b4, RTC_CNTL_STORE5_REG */
0x40090dfa <rtc_smoke_detector_demo+90>: memw
0x40090dfd <rtc_smoke_detector_demo+93>: s32i.n  a4, a3, 0  /* write a4 into RTC_CNTL_STORE4_REG */
0x40090dff <rtc_smoke_detector_demo+95>: memw
0x40090e02 <rtc_smoke_detector_demo+98>: l32i.n  a4, a2, 0  /* a4 = read RTC_CNTL_STORE5_REG */
0x40090e04 <rtc_smoke_detector_demo+100>: movi.n  a3, 32
0x40090e06 <rtc_smoke_detector_demo+102>: or  a3, a4, a3  /* a3 = RTC_CNTL_STORE5_REG | 0x20 */
0x40090e09 <rtc_smoke_detector_demo+105>: movi.n  a10, 1
0x40090e0b <rtc_smoke_detector_demo+107>: or  a11, a10, a10  /* a11 = 1 */
0x40090e0e <rtc_smoke_detector_demo+110>: memw
0x40090e11 <rtc_smoke_detector_demo+113>: s32i    a3, a2, 0  /* write (RTC_CNTL_STORE5_REG | 0x20) into RTC_CNTL_STORE5_REG */

0x40090e14 <rtc_smoke_detector_demo+116>: call8   0x4008f574 <rtc_slp_prep_lite>  /* rtc_slp_prep_lite(1, 1) */

0x40090e17 <rtc_smoke_detector_demo+119>: l32r    a8, 0x4008e53c  /* a8 = *(0x4008e53c) = 0x3ff48070, RTC_CNTL_CLK_CONF_REG */
0x40090e1a <rtc_smoke_detector_demo+122>: l32r    a2, 0x40087f7c  /* a2 = *(0x40087f7c) = 0x00000800 */
0x40090e1d <rtc_smoke_detector_demo+125>: memw
0x40090e20 <rtc_smoke_detector_demo+128>: l32i.n  a3, a8, 0

/* a3 = read RTC_CNTL_CLK_CONF_REG = 0x25580210, DFREQ = 1010 1100 = 172 */

0x40090e22 <rtc_smoke_detector_demo+130>: l32r    a11, 0x40090c28  /* a11 = *(40090c28) = 0x00061a80 = 400000 */
0x40090e25 <rtc_smoke_detector_demo+133>: or  a2, a3, a2  /* a2 = RTC_CNTL_CLK_CONF_REG | 0x800 */
0x40090e28 <rtc_smoke_detector_demo+136>: memw
0x40090e2b <rtc_smoke_detector_demo+139>: s32i.n  a2, a8, 0  /* set BIT(11), CK8M_DFREQ_FORCE */

0x40090e2d <rtc_smoke_detector_demo+141>: memw
0x40090e30 <rtc_smoke_detector_demo+144>: l32i.n  a3, a8, 0  /* a3 = read RTC_CNTL_CLK_CONF_REG */
0x40090e32 <rtc_smoke_detector_demo+146>: l32r    a2, 0x4008fd10  /* a2 = *(0x4008fd10) = 0xfe01ffff */
0x40090e35 <rtc_smoke_detector_demo+149>: movi.n  a10, 0
0x40090e37 <rtc_smoke_detector_demo+151>: and a2, a3, a2  /* a2 = RTC_CNTL_CLK_CONF_REG & 0xfe01ffff, bit[24:17] = DFREQ */
0x40090e3a <rtc_smoke_detector_demo+154>: l32r    a3, 0x40090c24  /* a3 = *(0x40090c24) = 0x01900000 */
0x40090e3d <rtc_smoke_detector_demo+157>: movi.n  a12, 1
0x40090e3f <rtc_smoke_detector_demo+159>: or  a2, a2, a3  /* a2 = RTC_CNTL_CLK_CONF_REG & 0xfe01ffff | 0x01900000 */
0x40090e42 <rtc_smoke_detector_demo+162>: memw

/* set bit[24:17] to 1 1001 000, 0xc8, 200 */
0x40090e45 <rtc_smoke_detector_demo+165>: s32i.n  a2, a8, 0  /* set DFREQ to 200 */

0x40090e47 <rtc_smoke_detector_demo+167>: memw
0x40090e4a <rtc_smoke_detector_demo+170>: l32i.n  a3, a8, 0  /* a3 = read RTC_CNTL_CLK_CONF_REG */
0x40090e4c <rtc_smoke_detector_demo+172>: l32r    a2, 0x4008fd14  /* a2 = *(0x4008fd14) = 0xffff8fff */
0x40090e4f <rtc_smoke_detector_demo+175>: mov.n   a13, a10
0x40090e51 <rtc_smoke_detector_demo+177>: and a2, a3, a2  /* a2 = RTC_CNTL_CLK_CONF_REG & 0xffff8fff, bit[14:12], CK8M_DIV_SEL */
0x40090e54 <rtc_smoke_detector_demo+180>: l32r    a3, 0x4008063c  /* a3 = *(0x4008063c) = 0x00002000 */
0x40090e57 <rtc_smoke_detector_demo+183>: or  a2, a2, a3  /* a2 = RTC_CNTL_CLK_CONF_REG & 0xffff8fff | 0x00002000 */
0x40090e5a <rtc_smoke_detector_demo+186>: memw
0x40090e5d <rtc_smoke_detector_demo+189>: s32i.n  a2, a8, 0  /* write to RTC_CNTL_CLK_CONF_REG */
/* divider = reg_ck8m_div_sel + 1 */

0x40090e5f <rtc_smoke_detector_demo+191>: call8   0x40090098 <rtc_sleep> /* rtc_sleep(0, 400000, 1, 0) */
0x40090e62 <rtc_smoke_detector_demo+194>: retw.n

2 Process

rtc_init_lite();
rtc_sdreg_off();

slp_pad_ctrl(1<<17);
rtc_cmd_ext_wakeup(1<<17, 17);
rtc_smoke_detector_in_sleep(1, 5);

rtc_printf();
ets_delay_us(20000);

rtc_sar_sleep_timer_start(5000);

update_RTC_CNTL_STORE4_REG;
update_RTC_CNTL_STORE5_REG;

rtc_slp_prep_lite(1, 1);

setup_RTC_CNTL_CLK_CONF_REG;

rtc_sleep(0, 400000, 1, 0)

3 rtc_sdreg_off

0x4008f010 <rtc_sdreg_off>: entry   a1, 32
0x4008f013 <rtc_sdreg_off+3>: l32r    a8, 0x4008f00c  /* a8 = 0x3ff48074, RTC_CNTL_SDIO_CONF_REG */
0x4008f016 <rtc_sdreg_off+6>: l32r    a9, 0x40080604  /* a9 = 0x00400000, BIT[22] */
/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos: [22] ;default: 1'd0 */
/* 1: use SW option to control SDIO_REG  0: use state machine*/
 
0x4008f019 <rtc_sdreg_off+9>: memw
0x4008f01c <rtc_sdreg_off+12>: l32i.n  a10, a8, 0  /* a10 = read RTC_CNTL_SDIO_CONF_REG */
0x4008f01e <rtc_sdreg_off+14>: or  a9, a10, a9
0x4008f021 <rtc_sdreg_off+17>: memw
0x4008f024 <rtc_sdreg_off+20>: s32i.n  a9, a8, 0  /* set the BIT[22] of RTC_CNTL_SDIO_CONF_REG */
0x4008f026 <rtc_sdreg_off+22>: memw
 
0x4008f029 <rtc_sdreg_off+25>: l32i.n  a10, a8, 0  /* a10 = read RTC_CNTL_SDIO_CONF_REG */
0x4008f02b <rtc_sdreg_off+27>: l32r    a9, 0x40084ce8  /* a9 = 0x00800000, BIT[23] */
/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos: [23] ;default: 1'd1 ; */
/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
 
0x4008f02e <rtc_sdreg_off+30>: or  a9, a10, a9
0x4008f031 <rtc_sdreg_off+33>: memw
0x4008f034 <rtc_sdreg_off+36>: s32i.n  a9, a8, 0  /* set the BIT[23] of RTC_CNTL_SDIO_CONF_REG */
0x4008f036 <rtc_sdreg_off+38>: memw
 
0x4008f039 <rtc_sdreg_off+41>: l32i.n  a10, a8, 0  /* a10 = read RTC_CNTL_SDIO_CONF_REG */
0x4008f03b <rtc_sdreg_off+43>: l32r    a9, 0x400804c0  /* a9 = 0x7fffffff, BIT[31] */
/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos: [31] ;default: 1'd0 ; */
/*description: SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/
 
0x4008f03e <rtc_sdreg_off+46>: and a9, a10, a9  /* clear BIT[31] */
0x4008f041 <rtc_sdreg_off+49>: memw
0x4008f044 <rtc_sdreg_off+52>: s32i.n  a9, a8, 0
0x4008f046 <rtc_sdreg_off+54>: retw.n