ESP32 ULP
来自Jack's Lab
1 ULP CP Inst
1.1 ulp_cp_wr_reg
(gdb) x /16i ulp_cp_wr_reg 0x4008f690 <ulp_cp_wr_reg>: entry a1, 32 0x4008f693 <ulp_cp_wr_reg+3>: l32r a8, 0x40085078 0x4008f696 <ulp_cp_wr_reg+6>: slli a5, a5, 10 0x4008f699 <ulp_cp_wr_reg+9>: or a2, a2, a8 0x4008f69c <ulp_cp_wr_reg+12>: or a5, a2, a5 0x4008f69f <ulp_cp_wr_reg+15>: slli a4, a4, 18 0x4008f6a2 <ulp_cp_wr_reg+18>: or a5, a5, a4 0x4008f6a5 <ulp_cp_wr_reg+21>: slli a2, a3, 23 0x4008f6a8 <ulp_cp_wr_reg+24>: or a2, a5, a2 0x4008f6ab <ulp_cp_wr_reg+27>: retw.n 0x4008f6ad: ill (gdb) x /4x 0x40085078 0x40085078: 0x10000000 0xb100a136 0x5c0cfff1 0x8118c1a2
1.2 ulp_cp_rd_reg
0x4008f6b0 <ulp_cp_rd_reg>: entry a1, 32 0x4008f6b3 <ulp_cp_rd_reg+3>: l32r a8, 0x4008043c 0x4008f6b6 <ulp_cp_rd_reg+6>: slli a4, a4, 18 0x4008f6b9 <ulp_cp_rd_reg+9>: or a2, a2, a8 0x4008f6bc <ulp_cp_rd_reg+12>: or a4, a2, a4 0x4008f6bf <ulp_cp_rd_reg+15>: slli a2, a3, 23 0x4008f6c2 <ulp_cp_rd_reg+18>: or a2, a4, a2 0x4008f6c5 <ulp_cp_rd_reg+21>: retw.n (gdb) x /4x 0x4008043c 0x4008043c: 0x20000000 0x40080000 0x3ffb29d0 0x3ffb0000
1.3 ulp_cp_wr_i2c
0x4008f6c8 <ulp_cp_wr_i2c>: entry a1, 32 0x4008f6cb <ulp_cp_wr_i2c+3>: l32r a8, 0x4008f3c4 0x4008f6ce <ulp_cp_wr_i2c+6>: slli a7, a7, 8 0x4008f6d1 <ulp_cp_wr_i2c+9>: or a4, a4, a8 0x4008f6d4 <ulp_cp_wr_i2c+12>: or a7, a4, a7 0x4008f6d7 <ulp_cp_wr_i2c+15>: slli a6, a6, 16 0x4008f6da <ulp_cp_wr_i2c+18>: or a7, a7, a6 0x4008f6dd <ulp_cp_wr_i2c+21>: slli a5, a5, 19 0x4008f6e0 <ulp_cp_wr_i2c+24>: or a7, a7, a5 0x4008f6e3 <ulp_cp_wr_i2c+27>: slli a3, a3, 22 0x4008f6e6 <ulp_cp_wr_i2c+30>: or a7, a7, a3 0x4008f6e9 <ulp_cp_wr_i2c+33>: slli a2, a2, 27 0x4008f6ec <ulp_cp_wr_i2c+36>: or a2, a7, a2 0x4008f6ef <ulp_cp_wr_i2c+39>: retw.n 0x4008f6f1: ill (gdb) x /4x 0x4008f3c4 0x4008f3c4: 0x30000000 0x81004136 0x7780fffe 0x20448011
1.4 ulp_cp_wait_delay
0x4008f6f4 <ulp_cp_wait_delay>: entry a1, 32 0x4008f6f7 <ulp_cp_wait_delay+3>: l32r a8, 0x400805a0 0x4008f6fa <ulp_cp_wait_delay+6>: or a2, a2, a8 0x4008f6fd <ulp_cp_wait_delay+9>: retw.n (gdb) x /4x 0x400805a0 0x400805a0: 0x40000000 0x3ff42008 0x00400000 0x3ffae270
1.5 ulp_cp_meas_tsens
(gdb) x /32i ulp_cp_meas_tsens 0x4008f700 <ulp_cp_meas_tsens>: entry a1, 32 0x4008f703 <ulp_cp_meas_tsens+3>: l32r a8, 0x4008f404 0x4008f706 <ulp_cp_meas_tsens+6>: slli a2, a2, 2 0x4008f709 <ulp_cp_meas_tsens+9>: or a3, a3, a8 0x4008f70c <ulp_cp_meas_tsens+12>: or a2, a3, a2 0x4008f70f <ulp_cp_meas_tsens+15>: retw.n 0x4008f711: ill (gdb) x /4x 0x4008f404 0x4008f404: 0xa0000000 0x81004136 0x2200fffe 0x20338011
1.6 ulp_cp_meas_tsens_new
0x4008f714 <ulp_cp_meas_tsens_new>: entry a1, 32 0x4008f717 <ulp_cp_meas_tsens_new+3>: l32r a8, 0x4008f404 0x4008f71a <ulp_cp_meas_tsens_new+6>: slli a3, a3, 2 0x4008f71d <ulp_cp_meas_tsens_new+9>: or a4, a4, a8 0x4008f720 <ulp_cp_meas_tsens_new+12>: or a3, a4, a3 0x4008f723 <ulp_cp_meas_tsens_new+15>: slli a2, a2, 16 0x4008f726 <ulp_cp_meas_tsens_new+18>: or a2, a3, a2 0x4008f729 <ulp_cp_meas_tsens_new+21>: retw.n (gdb) x /4x 0x4008f404 0x4008f404: 0xa0000000 0x81004136 0x2200fffe 0x20338011
1.7 ulp_cp_meas_sar
0x4008f72c <ulp_cp_meas_sar>: entry a1, 32 0x4008f72f <ulp_cp_meas_sar+3>: l32r a8, 0x4008f41c 0x4008f732 <ulp_cp_meas_sar+6>: slli a4, a4, 2 0x4008f735 <ulp_cp_meas_sar+9>: or a5, a5, a8 0x4008f738 <ulp_cp_meas_sar+12>: or a4, a5, a4 0x4008f73b <ulp_cp_meas_sar+15>: slli a3, a3, 6 0x4008f73e <ulp_cp_meas_sar+18>: or a4, a4, a3 0x4008f741 <ulp_cp_meas_sar+21>: slli a2, a2, 8 0x4008f744 <ulp_cp_meas_sar+24>: or a2, a4, a2 0x4008f747 <ulp_cp_meas_sar+27>: retw.n 0x4008f749: ill (gdb) x /4x 0x4008f41c 0x4008f41c: 0x50000000 0x81004136 0x4040fffe 0x14505034
1.8 ulp_cp_sar_wr_mem
0x4008f74c <ulp_cp_sar_wr_mem>: entry a1, 32 0x4008f74f <ulp_cp_sar_wr_mem+3>: l32r a8, 0x400804d8 0x4008f752 <ulp_cp_sar_wr_mem+6>: slli a3, a3, 2 0x4008f755 <ulp_cp_sar_wr_mem+9>: or a4, a4, a8 0x4008f758 <ulp_cp_sar_wr_mem+12>: or a3, a4, a3 0x4008f75b <ulp_cp_sar_wr_mem+15>: slli a2, a2, 7 0x4008f75e <ulp_cp_sar_wr_mem+18>: or a2, a3, a2 0x4008f761 <ulp_cp_sar_wr_mem+21>: retw.n 0x4008f763: ill (gdb) x /4x 0x400804d8 0x400804d8: 0x60000000 0x00040023 0xc0000000 0x3ffb2b48
1.9 ulp_cp_sar_wr_mem_set_offset
0x4008f768 <ulp_cp_sar_wr_mem_set_offset>: entry a1, 32 0x4008f76b <ulp_cp_sar_wr_mem_set_offset+3>: l32r a8, 0x4008f764 0x4008f76e <ulp_cp_sar_wr_mem_set_offset+6>: slli a2, a2, 10 0x4008f771 <ulp_cp_sar_wr_mem_set_offset+9>: or a2, a2, a8 0x4008f774 <ulp_cp_sar_wr_mem_set_offset+12>: retw.n (gdb) x /1x 0x4008f764 0x4008f764: 0x64000000
1.10 ulp_cp_sar_wr_mem_man2
0x4008f790 <ulp_cp_sar_wr_mem_man2>: entry a1, 32 0x4008f793 <ulp_cp_sar_wr_mem_man2+3>: l32r a8, 0x4008f778 0x4008f796 <ulp_cp_sar_wr_mem_man2+6>: slli a3, a3, 2 0x4008f799 <ulp_cp_sar_wr_mem_man2+9>: or a4, a4, a8 0x4008f79c <ulp_cp_sar_wr_mem_man2+12>: or a3, a4, a3 0x4008f79f <ulp_cp_sar_wr_mem_man2+15>: slli a2, a2, 10 0x4008f7a2 <ulp_cp_sar_wr_mem_man2+18>: or a2, a3, a2 0x4008f7a5 <ulp_cp_sar_wr_mem_man2+21>: retw.n (gdb) x /1x 0x4008f778 0x4008f778: 0x68000000
1.11 ulp_cp_rd_mem
0x4008f7ac <ulp_cp_rd_mem>: entry a1, 32 0x4008f7af <ulp_cp_rd_mem+3>: l32r a8, 0x4008f7a8 0x4008f7b2 <ulp_cp_rd_mem+6>: slli a2, a2, 10 0x4008f7b5 <ulp_cp_rd_mem+9>: or a3, a3, a8 0x4008f7b8 <ulp_cp_rd_mem+12>: or a2, a3, a2 0x4008f7bb <ulp_cp_rd_mem+15>: retw.n 0x4008f7bd: ill 0x4008f7c0 <ulp_cp_rd_mem2>: entry a1, 32 0x4008f7c3 <ulp_cp_rd_mem2+3>: l32r a8, 0x4008f7a8 0x4008f7c6 <ulp_cp_rd_mem2+6>: slli a3, a3, 2 0x4008f7c9 <ulp_cp_rd_mem2+9>: or a4, a4, a8 0x4008f7cc <ulp_cp_rd_mem2+12>: or a3, a4, a3 0x4008f7cf <ulp_cp_rd_mem2+15>: slli a2, a2, 10 0x4008f7d2 <ulp_cp_rd_mem2+18>: or a2, a3, a2 0x4008f7d5 <ulp_cp_rd_mem2+21>: retw.n (gdb) x /1x 0x4008f7a8 0x4008f7a8: 0xd0000000
1.12 ulp_cp_alu_reg
(gdb) x /12i ulp_cp_alu_reg 0x4008f7d8 <ulp_cp_alu_reg>: entry a1, 32 0x4008f7db <ulp_cp_alu_reg+3>: l32r a8, 0x4008f46c 0x4008f7de <ulp_cp_alu_reg+6>: slli a4, a4, 2 0x4008f7e1 <ulp_cp_alu_reg+9>: or a5, a5, a8 0x4008f7e4 <ulp_cp_alu_reg+12>: or a4, a5, a4 0x4008f7e7 <ulp_cp_alu_reg+15>: slli a3, a3, 4 0x4008f7ea <ulp_cp_alu_reg+18>: or a4, a4, a3 0x4008f7ed <ulp_cp_alu_reg+21>: slli a2, a2, 21 0x4008f7f0 <ulp_cp_alu_reg+24>: or a2, a4, a2 0x4008f7f3 <ulp_cp_alu_reg+27>: retw.n 0x4008f7f5: ill (gdb) x /1x 0x4008f46c 0x4008f46c: 0x70000000
1.13 ulp_cp_alu_im
0x4008f7f8 <ulp_cp_alu_im>: entry a1, 32 0x4008f7fb <ulp_cp_alu_im+3>: l32r a8, 0x4008f490 0x4008f7fe <ulp_cp_alu_im+6>: slli a4, a4, 2 0x4008f801 <ulp_cp_alu_im+9>: or a5, a5, a8 0x4008f804 <ulp_cp_alu_im+12>: slli a2, a2, 4 0x4008f807 <ulp_cp_alu_im+15>: or a8, a5, a4 0x4008f80a <ulp_cp_alu_im+18>: or a8, a8, a2 0x4008f80d <ulp_cp_alu_im+21>: slli a2, a3, 21 0x4008f810 <ulp_cp_alu_im+24>: or a2, a8, a2 0x4008f813 <ulp_cp_alu_im+27>: retw.n 0x4008f815: ill 0x4008f818: ill (gdb) x /1x 0x4008f490 0x4008f490: 0x72000000
1.14 ulp_cp_alu_im
0x4008f7f8 <ulp_cp_alu_im>: entry a1, 32 0x4008f7fb <ulp_cp_alu_im+3>: l32r a8, 0x4008f490 0x4008f7fe <ulp_cp_alu_im+6>: slli a4, a4, 2 0x4008f801 <ulp_cp_alu_im+9>: or a5, a5, a8 0x4008f804 <ulp_cp_alu_im+12>: slli a2, a2, 4 0x4008f807 <ulp_cp_alu_im+15>: or a8, a5, a4 0x4008f80a <ulp_cp_alu_im+18>: or a8, a8, a2 0x4008f80d <ulp_cp_alu_im+21>: slli a2, a3, 21 0x4008f810 <ulp_cp_alu_im+24>: or a2, a8, a2 0x4008f813 <ulp_cp_alu_im+27>: retw.n 0x4008f815: ill 0x4008f818: ill
1.15 ulp_cp_stage_cnt_alu
0x4008f81c <ulp_cp_stage_cnt_alu>: entry a1, 32 0x4008f81f <ulp_cp_stage_cnt_alu+3>: l32r a8, 0x4008f818 0x4008f822 <ulp_cp_stage_cnt_alu+6>: slli a2, a2, 4 0x4008f825 <ulp_cp_stage_cnt_alu+9>: or a8, a2, a8 0x4008f828 <ulp_cp_stage_cnt_alu+12>: slli a2, a3, 21 0x4008f82b <ulp_cp_stage_cnt_alu+15>: or a2, a8, a2 0x4008f82e <ulp_cp_stage_cnt_alu+18>: retw.n (gdb) x /1x 0x4008f818 0x4008f818: 0x74000000
1.16 ulp_cp_force_branch
0x4008f830 <ulp_cp_force_branch>: entry a1, 32 0x4008f833 <ulp_cp_force_branch+3>: l32r a8, 0x40080690 0x4008f836 <ulp_cp_force_branch+6>: slli a2, a2, 17 0x4008f839 <ulp_cp_force_branch+9>: or a2, a2, a8 0x4008f83c <ulp_cp_force_branch+12>: retw.n (gdb) x /1x 0x40080690 0x40080690: 0x80000000
1.17 ulp_cp_jump
0x4008f840 <ulp_cp_jump>: entry a1, 32 0x4008f843 <ulp_cp_jump+3>: l32r a8, 0x40080690 0x4008f846 <ulp_cp_jump+6>: slli a4, a4, 2 0x4008f849 <ulp_cp_jump+9>: or a5, a5, a8 0x4008f84c <ulp_cp_jump+12>: or a4, a5, a4 0x4008f84f <ulp_cp_jump+15>: slli a2, a2, 22 0x4008f852 <ulp_cp_jump+18>: or a2, a4, a2 0x4008f855 <ulp_cp_jump+21>: retw.n
1.18 ulp_cp_reg0_branch
0x4008f858 <ulp_cp_reg0_branch>: entry a1, 32 0x4008f85b <ulp_cp_reg0_branch+3>: l32r a8, 0x4008f4c0 0x4008f85e <ulp_cp_reg0_branch+6>: slli a3, a3, 16 0x4008f861 <ulp_cp_reg0_branch+9>: or a4, a4, a8 0x4008f864 <ulp_cp_reg0_branch+12>: or a3, a4, a3 0x4008f867 <ulp_cp_reg0_branch+15>: slli a2, a2, 17 0x4008f86a <ulp_cp_reg0_branch+18>: or a2, a3, a2 0x4008f86d <ulp_cp_reg0_branch+21>: retw.n (gdb) x /1x 0x4008f4c0 0x4008f4c0: 0x82000000
1.19 ulp_cp_stage_cnt_br
0x4008f870 <ulp_cp_stage_cnt_br>: entry a1, 32 0x4008f873 <ulp_cp_stage_cnt_br+3>: l32r a8, 0x400807d0 0x4008f876 <ulp_cp_stage_cnt_br+6>: slli a3, a3, 15 0x4008f879 <ulp_cp_stage_cnt_br+9>: or a4, a4, a8 0x4008f87c <ulp_cp_stage_cnt_br+12>: or a3, a4, a3 0x4008f87f <ulp_cp_stage_cnt_br+15>: slli a2, a2, 17 0x4008f882 <ulp_cp_stage_cnt_br+18>: or a2, a3, a2 0x4008f885 <ulp_cp_stage_cnt_br+21>: retw.n (gdb) x /1x 0x400807d0 0x400807d0: 0x84000000
1.20 ulp_cp_cpu_wakeup
0x4008f888 <ulp_cp_cpu_wakeup>: entry a1, 32 0x4008f88b <ulp_cp_cpu_wakeup+3>: l32r a8, 0x4008f4fc 0x4008f88e <ulp_cp_cpu_wakeup+6>: or a2, a2, a8 0x4008f891 <ulp_cp_cpu_wakeup+9>: retw.n (gdb) x /1x 0x4008f4fc 0x4008f4fc: 0x90000000
1.21 ulp_cp_sleep_cyc_sel
0x4008f894 <ulp_cp_sleep_cyc_sel>: entry a1, 32 0x4008f897 <ulp_cp_sleep_cyc_sel+3>: l32r a8, 0x4008f50c 0x4008f89a <ulp_cp_sleep_cyc_sel+6>: or a2, a2, a8 0x4008f89d <ulp_cp_sleep_cyc_sel+9>: retw.n (gdb) x /1x 0x4008f50c 0x4008f50c: 0x92000000
1.22 ulp_cp_meas_end
0x4008f8a0 <ulp_cp_meas_end>: entry a1, 32 0x4008f8a3 <ulp_cp_meas_end+3>: l32r a2, 0x4008f51c 0x4008f8a6 <ulp_cp_meas_end+6>: retw.n (gdb) x /1x 0x4008f51c 0x4008f51c: 0xb0000000
