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== Interrupts == <pre> #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ #define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ #define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels (not including level zero) */ #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ /* Masks of interrupts at each interrupt level: */ #define XCHAL_INTLEVEL1_MASK 0x000637FF #define XCHAL_INTLEVEL2_MASK 0x00380000 #define XCHAL_INTLEVEL3_MASK 0x28C08800 #define XCHAL_INTLEVEL4_MASK 0x53000000 #define XCHAL_INTLEVEL5_MASK 0x84010000 #define XCHAL_INTLEVEL6_MASK 0x00000000 #define XCHAL_INTLEVEL7_MASK 0x00004000 /* Masks of interrupts at each range 1..n of interrupt levels: */ #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF /* Level of each interrupt: */ #define XCHAL_INT0_LEVEL 1 #define XCHAL_INT1_LEVEL 1 #define XCHAL_INT2_LEVEL 1 #define XCHAL_INT3_LEVEL 1 #define XCHAL_INT4_LEVEL 1 #define XCHAL_INT5_LEVEL 1 #define XCHAL_INT6_LEVEL 1 #define XCHAL_INT7_LEVEL 1 #define XCHAL_INT8_LEVEL 1 #define XCHAL_INT9_LEVEL 1 #define XCHAL_INT10_LEVEL 1 #define XCHAL_INT11_LEVEL 3 #define XCHAL_INT12_LEVEL 1 #define XCHAL_INT13_LEVEL 1 #define XCHAL_INT14_LEVEL 7 #define XCHAL_INT15_LEVEL 3 #define XCHAL_INT16_LEVEL 5 #define XCHAL_INT17_LEVEL 1 #define XCHAL_INT18_LEVEL 1 #define XCHAL_INT19_LEVEL 2 #define XCHAL_INT20_LEVEL 2 #define XCHAL_INT21_LEVEL 2 #define XCHAL_INT22_LEVEL 3 #define XCHAL_INT23_LEVEL 3 #define XCHAL_INT24_LEVEL 4 #define XCHAL_INT25_LEVEL 4 #define XCHAL_INT26_LEVEL 5 #define XCHAL_INT27_LEVEL 3 #define XCHAL_INT28_LEVEL 4 #define XCHAL_INT29_LEVEL 3 #define XCHAL_INT30_LEVEL 4 #define XCHAL_INT31_LEVEL 5 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with EXCSAVE/EPS/EPC_n, RFI n) */ /* Type of each interrupt: */ #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE #define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI #define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER #define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE #define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL #define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE #define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE #define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE #define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL /* Masks of interrupts for each type of interrupt: */ #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F #define XCHAL_INTTYPE_MASK_TIMER 0x00018040 #define XCHAL_INTTYPE_MASK_NMI 0x00004000 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 #define XCHAL_INTTYPE_MASK_PROFILING 0x00000800 /* Interrupt numbers assigned to specific interrupt sources: */ #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ #define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ #define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ #define XCHAL_PROFILING_INTERRUPT 11 /* profiling interrupt */ /* Interrupt numbers for levels at which only one interrupt is configured: */ #define XCHAL_INTLEVEL7_NUM 14 /* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ /* * External interrupt mapping. * These macros describe how Xtensa processor interrupt numbers * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) * map to external BInterrupt<n> pins, for those interrupts * configured as external (level-triggered, edge-triggered, or NMI). * See the Xtensa processor databook for more details. */ /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ #define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */ #define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */ #define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */ #define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */ #define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */ #define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */ #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ #define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */ #define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */ #define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */ #define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */ #define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */ #define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */ #define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */ #define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */ #define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */ #define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */ #define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */ #define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */ /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ #define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ #define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ #define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ #define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ #define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ #define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ #define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */ #define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */ #define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */ #define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */ #define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */ #define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */ #define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ #define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ #define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */ #define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ #define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */ #define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */ #define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */ #define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */ #define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */ #define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */ #define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */ #define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */ #define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */ #define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */ </pre> <br><br>
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