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ESP32 core isa
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== Cache == <pre> #define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ #define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ #define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ #define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ #define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ #define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ #define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ #define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ #define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ #define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ #define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ #define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ #define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ #define XCHAL_HAVE_AXI 0 /* AXI bus */ #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ #define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ /* Number of cache sets in log2(lines per way): */ #define XCHAL_ICACHE_SETWIDTH 0 #define XCHAL_DCACHE_SETWIDTH 0 /* Cache set associativity (number of ways): */ #define XCHAL_ICACHE_WAYS 1 #define XCHAL_DCACHE_WAYS 1 /* Cache features: */ #define XCHAL_ICACHE_LINE_LOCKABLE 0 #define XCHAL_DCACHE_LINE_LOCKABLE 0 #define XCHAL_ICACHE_ECC_PARITY 0 #define XCHAL_DCACHE_ECC_PARITY 0 /* Cache access size in bytes (affects operation of SICW instruction): */ #define XCHAL_ICACHE_ACCESS_SIZE 1 #define XCHAL_DCACHE_ACCESS_SIZE 1 #define XCHAL_DCACHE_BANKS 0 /* number of banks */ /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ #define XCHAL_CA_BITS 4 </pre> <br><br>
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