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ESP32 core isa
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== ROM/RAM == <pre> #define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */ #define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ #define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */ #define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ #define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ /* Instruction ROM 0: */ #define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */ #define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */ #define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */ #define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ /* Instruction RAM 0: */ #define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ #define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ #define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */ #define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ /* Instruction RAM 1: */ #define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */ #define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */ #define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */ #define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ /* Data ROM 0: */ #define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */ #define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */ #define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */ #define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ #define XCHAL_DATAROM0_BANKS 1 /* number of banks */ /* Data RAM 0: */ #define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */ #define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */ #define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */ #define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ /* Data RAM 1: */ #define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */ #define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */ #define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */ #define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ #define XCHAL_DATARAM1_BANKS 1 /* number of banks */ /* XLMI Port 0: */ #define XCHAL_XLMI0_VADDR 0x3FF00000 /* virtual address */ #define XCHAL_XLMI0_PADDR 0x3FF00000 /* physical address */ #define XCHAL_XLMI0_SIZE 524288 /* size in bytes */ #define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ </pre> <br><br>
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