2016年11月22日 (二) 00:17的版本

1 ISA

#define XCHAL_HAVE_BE           0   /* big-endian byte ordering */
#define XCHAL_HAVE_WINDOWED     1   /* windowed registers option */
#define XCHAL_NUM_AREGS         64  /* num of physical addr regs */
#define XCHAL_NUM_AREGS_LOG2        6   /* log2(XCHAL_NUM_AREGS) */
#define XCHAL_MAX_INSTRUCTION_SIZE  3   /* max instr bytes (3..8) */
#define XCHAL_HAVE_DEBUG        1   /* debug option */
#define XCHAL_HAVE_DENSITY      1   /* 16-bit instructions */
#define XCHAL_HAVE_LOOPS        1   /* zero-overhead loops */
#define XCHAL_LOOP_BUFFER_SIZE      256 /* zero-ov. loop instr buffer size */
#define XCHAL_HAVE_NSA          1   /* NSA/NSAU instructions */
#define XCHAL_HAVE_MINMAX       1   /* MIN/MAX instructions */
#define XCHAL_HAVE_SEXT         1   /* SEXT instruction */
#define XCHAL_HAVE_DEPBITS      0   /* DEPBITS instruction */
#define XCHAL_HAVE_CLAMPS       1   /* CLAMPS instruction */
#define XCHAL_HAVE_MUL16        1   /* MUL16S/MUL16U instructions */
#define XCHAL_HAVE_MUL32        1   /* MULL instruction */
#define XCHAL_HAVE_MUL32_HIGH       1   /* MULUH/MULSH instructions */
#define XCHAL_HAVE_DIV32        1   /* QUOS/QUOU/REMS/REMU instructions */
#define XCHAL_HAVE_L32R         1   /* L32R instruction */
#define XCHAL_HAVE_ABSOLUTE_LITERALS    0   /* non-PC-rel (extended) L32R */
#define XCHAL_HAVE_CONST16      0   /* CONST16 instruction */
#define XCHAL_HAVE_ADDX         1   /* ADDX#/SUBX# instructions */
#define XCHAL_HAVE_WIDE_BRANCHES    0   /* B*.W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES   0   /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12       1   /* (obsolete option) */
#define XCHAL_HAVE_ABS          1   /* ABS instruction */
/*#define XCHAL_HAVE_POPC       0*/ /* POPC instruction */
/*#define XCHAL_HAVE_CRC        0*/ /* CRC instruction */
#define XCHAL_HAVE_RELEASE_SYNC     1   /* L32AI/S32RI instructions */
#define XCHAL_HAVE_S32C1I       1   /* S32C1I instruction */
#define XCHAL_HAVE_SPECULATION      0   /* speculation */
#define XCHAL_HAVE_FULL_RESET       1   /* all regs/state reset */
#define XCHAL_NUM_CONTEXTS      1   /* */
#define XCHAL_NUM_MISC_REGS     4   /* num of scratch regs (0..4) */
#define XCHAL_HAVE_TAP_MASTER       0   /* JTAG TAP control instr's */
#define XCHAL_HAVE_PRID         1   /* processor ID register */
#define XCHAL_HAVE_EXTERN_REGS      1   /* WER/RER instructions */
#define XCHAL_HAVE_MX           0   /* MX core (Tensilica internal) */
#define XCHAL_HAVE_MP_INTERRUPTS    0   /* interrupt distributor port */

#define XCHAL_HAVE_MP_RUNSTALL      0   /* core RunStall control port */
#define XCHAL_HAVE_PSO          0   /* Power Shut-Off */
#define XCHAL_HAVE_PSO_CDM      0   /* core/debug/mem pwr domains */
#define XCHAL_HAVE_PSO_FULL_RETENTION   0   /* all regs preserved on PSO */
#define XCHAL_HAVE_THREADPTR        1   /* THREADPTR register */
#define XCHAL_HAVE_BOOLEANS     1   /* boolean registers */
#define XCHAL_HAVE_CP           1   /* CPENABLE reg (coprocessor) */
#define XCHAL_CP_MAXCFG         8   /* max allowed cp id plus one */
#define XCHAL_HAVE_MAC16        1   /* MAC16 package */

#define XCHAL_HAVE_FUSION        0  /* Fusion*/
#define XCHAL_HAVE_FUSION_FP     0          /* Fusion FP option */
#define XCHAL_HAVE_FUSION_LOW_POWER 0   /* Fusion Low Power option */
#define XCHAL_HAVE_FUSION_AES    0          /* Fusion BLE/Wifi AES-128 CCM option */
#define XCHAL_HAVE_FUSION_CONVENC    0       /* Fusion Conv Encode option */
#define XCHAL_HAVE_FUSION_LFSR_CRC   0  /* Fusion LFSR-CRC option */
#define XCHAL_HAVE_FUSION_BITOPS     0  /* Fusion Bit Operations Support option */
#define XCHAL_HAVE_FUSION_AVS    0  /* Fusion AVS option */
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND     0  /* Fusion 16-bit Baseband option */
#define XCHAL_HAVE_FUSION_VITERBI        0     /* Fusion Viterbi option */
#define XCHAL_HAVE_FUSION_SOFTDEMAP      0   /* Fusion Soft Bit Demap option */
#define XCHAL_HAVE_HIFIPRO      0   /* HiFiPro Audio Engine pkg */
#define XCHAL_HAVE_HIFI4        0   /* HiFi4 Audio Engine pkg */
#define XCHAL_HAVE_HIFI4_VFPU       0   /* HiFi4 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI3        0   /* HiFi3 Audio Engine pkg */
#define XCHAL_HAVE_HIFI3_VFPU       0   /* HiFi3 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI2        0   /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_HIFI2EP      0   /* HiFi2EP */
#define XCHAL_HAVE_HIFI_MINI        0   


#define XCHAL_HAVE_VECTORFPU2005    0   /* vector or user floating-point pkg */
#define XCHAL_HAVE_USER_DPFPU         0       /* user DP floating-point pkg */
#define XCHAL_HAVE_USER_SPFPU         0       /* user DP floating-point pkg */
#define XCHAL_HAVE_FP                 1      /* single prec floating point */
#define XCHAL_HAVE_FP_DIV             1  /* FP with DIV instructions */
#define XCHAL_HAVE_FP_RECIP           1        /* FP with RECIP instructions */
#define XCHAL_HAVE_FP_SQRT            1 /* FP with SQRT instructions */
#define XCHAL_HAVE_FP_RSQRT           1        /* FP with RSQRT instructions */
#define XCHAL_HAVE_DFP                        0     /* double precision FP pkg */
#define XCHAL_HAVE_DFP_DIV            0 /* DFP with DIV instructions */
#define XCHAL_HAVE_DFP_RECIP          0       /* DFP with RECIP instructions*/
#define XCHAL_HAVE_DFP_SQRT           0        /* DFP with SQRT instructions */
#define XCHAL_HAVE_DFP_RSQRT          0       /* DFP with RSQRT instructions*/
#define XCHAL_HAVE_DFP_ACCEL        1   /* double precision FP acceleration pkg */
#define XCHAL_HAVE_DFP_accel        XCHAL_HAVE_DFP_ACCEL                /* for backward compatibility */

#define XCHAL_HAVE_DFPU_SINGLE_ONLY    1                    /* DFPU Coprocessor, single precision only */
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE  0                /* DFPU Coprocessor, single and double precision */
#define XCHAL_HAVE_VECTRA1      0   /* Vectra I  pkg */
#define XCHAL_HAVE_VECTRALX     0   /* Vectra LX pkg */
#define XCHAL_HAVE_PDX4             0   /* PDX4 */
#define XCHAL_HAVE_CONNXD2      0   /* ConnX D2 pkg */
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0   /* ConnX D2 & Dual LoadStore Flix */
#define XCHAL_HAVE_BBE16        0   /* ConnX BBE16 pkg */
#define XCHAL_HAVE_BBE16_RSQRT      0   /* BBE16 & vector recip sqrt */
#define XCHAL_HAVE_BBE16_VECDIV     0   /* BBE16 & vector divide */
#define XCHAL_HAVE_BBE16_DESPREAD   0   /* BBE16 & despread */
#define XCHAL_HAVE_BBENEP       0   /* ConnX BBENEP pkgs */
#define XCHAL_HAVE_BSP3         0   /* ConnX BSP3 pkg */
#define XCHAL_HAVE_BSP3_TRANSPOSE   0   /* BSP3 & transpose32x32 */
#define XCHAL_HAVE_SSP16        0   /* ConnX SSP16 pkg */
#define XCHAL_HAVE_SSP16_VITERBI    0   /* SSP16 & viterbi */
#define XCHAL_HAVE_TURBO16      0   /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16        0   /* ConnX BBP16 pkg */
#define XCHAL_HAVE_FLIX3        0   /* basic 3-way FLIX option */
#define XCHAL_HAVE_GRIVPEP              0   /*  GRIVPEP is General Release of IVPEP */
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0   /* Histogram option on GRIVPEP */

2 Exceptions

3 Interrupts

4 CACHE

#define XCHAL_ICACHE_LINESIZE       4   /* I-cache line size in bytes */
#define XCHAL_DCACHE_LINESIZE       4   /* D-cache line size in bytes */
#define XCHAL_ICACHE_LINEWIDTH      2   /* log2(I line size in bytes) */
#define XCHAL_DCACHE_LINEWIDTH      2   /* log2(D line size in bytes) */

#define XCHAL_ICACHE_SIZE       0   /* I-cache size in bytes or 0 */
#define XCHAL_DCACHE_SIZE       0   /* D-cache size in bytes or 0 */

#define XCHAL_DCACHE_IS_WRITEBACK   0   /* writeback feature */
#define XCHAL_DCACHE_IS_COHERENT    0   /* MP coherence feature */

#define XCHAL_HAVE_PREFETCH     0   /* PREFCTL register */
#define XCHAL_HAVE_PREFETCH_L1      0   /* prefetch to L1 dcache */
#define XCHAL_PREFETCH_CASTOUT_LINES    0   /* dcache pref. castout bufsz */
#define XCHAL_PREFETCH_ENTRIES      0   /* cache prefetch entries */
#define XCHAL_PREFETCH_BLOCK_ENTRIES    0   /* prefetch block streams */
#define XCHAL_HAVE_CACHE_BLOCKOPS   0   /* block prefetch for caches */
#define XCHAL_HAVE_ICACHE_TEST      0   /* Icache test instructions */
#define XCHAL_HAVE_DCACHE_TEST      0   /* Dcache test instructions */
#define XCHAL_HAVE_ICACHE_DYN_WAYS  0   /* Icache dynamic way support */
#define XCHAL_HAVE_DCACHE_DYN_WAYS  0   /* Dcache dynamic way support */