GD32
来自Jack's Lab
（版本间的差异）
(→OpenOCD) |
(→Toolchain) |
||
| 第28行： | 第28行： | ||
* QFN32 | * QFN32 | ||
* [http://gd32mcu.com/data/documents/shujushouce/GD32E230xx_Datasheet_Rev1.4.pdf GD32E230xx datasheet] | * [http://gd32mcu.com/data/documents/shujushouce/GD32E230xx_Datasheet_Rev1.4.pdf GD32E230xx datasheet] | ||
| + | |||
| + | <br> | ||
| + | |||
| + | == Boot modes == | ||
| + | |||
| + | At startup, boot pins are used to select one of three boot options: | ||
| + | |||
| + | * Boot from main Flash memory (default) | ||
| + | * Boot from system memory | ||
| + | * Boot from on-chip SRAM | ||
| + | |||
| + | In default condition, boot from main Flash memory is selected. The boot loader is located in | ||
| + | the internal boot ROM memory (system memory). It is used to reprogram the Flash memory | ||
| + | by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15 or PA2 and PA3) | ||
<br> | <br> | ||
2021年10月8日 (五) 18:44的版本
目录 |
1 Overview
http://gd32mcu.com/cn/product/m23
1.1 GD32E230G8U6
- 32 bit Cortex®-M23 Core, up to 72MHz
- 64KB Flash, 8KB RAM; G6U6 (32KB/6KB)
- I2C x2; SPI x2; USART x2
- RTC x1
- GPIO x23
- ADC x1
- 1.8V ~ 3.6V, 5V 容忍I/O
- QFN28
- GD32E230xx datasheet
1.2 GD32E230K8U6
- 32 bit Cortex®-M23 Core, up to 72MHz
- 64KB Flash, 8KB RAM; G6U6 (32KB/6KB)
- I2C x2; SPI x2; USART x2
- RTC x1
- GPIO x23
- ADC x1
- 1.8V ~ 3.6V, 5V 容忍I/O
- QFN32
- GD32E230xx datasheet
2 Boot modes
At startup, boot pins are used to select one of three boot options:
- Boot from main Flash memory (default)
- Boot from system memory
- Boot from on-chip SRAM
In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15 or PA2 and PA3)
3 Toolchain
3.1 OpenOCD
