GD32
来自Jack's Lab
（版本间的差异）
(→Boot modes) |
(→Overview) |
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http://gd32mcu.com/cn/product/m23 | http://gd32mcu.com/cn/product/m23 | ||
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| + | <br> | ||
| + | |||
| + | == ARM == | ||
=== GD32E230G8U6 === | === GD32E230G8U6 === | ||
| 第28行： | 第32行： | ||
* QFN32 | * QFN32 | ||
* [http://gd32mcu.com/data/documents/shujushouce/GD32E230xx_Datasheet_Rev1.4.pdf GD32E230xx datasheet] | * [http://gd32mcu.com/data/documents/shujushouce/GD32E230xx_Datasheet_Rev1.4.pdf GD32E230xx datasheet] | ||
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| + | <br> | ||
| + | |||
| + | == RISC-V == | ||
| + | |||
| + | === GD32VF103T8U6 === | ||
| + | |||
| + | * RISC-V 108MHz | ||
| + | * 64KB Flash/20KB RAM | ||
| + | * up to 26 I/O | ||
| + | * SysTick 24bit Timer x1 | ||
| + | * WDG x2, RTC x1 | ||
| + | * I2C x1; SPI x1; USART x2; CAN2.0 x2; | ||
| + | * USB OTG | ||
| + | * 12bit ADC x2(10 ch) | ||
| + | * 12bit DAC x2 | ||
| + | * QFN36 | ||
| + | |||
| + | <br> | ||
| + | |||
| + | === GD32VF103TBU6 === | ||
| + | |||
| + | * RISC-V 108MHz | ||
| + | * 128KB Flash/32KB RAM | ||
| + | * up to 26 I/O | ||
| + | * SysTick 24bit Timer x1 | ||
| + | * WDG x2, RTC x1 | ||
| + | * I2C x1; SPI x1; USART x2; CAN2.0 x2; | ||
| + | * USB OTG | ||
| + | * 12bit ADC x2(10 ch) | ||
| + | * 12bit DAC x2 | ||
| + | * QFN36 | ||
<br> | <br> | ||
2021年10月9日 (六) 11:34的版本
目录 |
1 Overview
http://gd32mcu.com/cn/product/m23
2 ARM
2.1 GD32E230G8U6
- 32 bit Cortex®-M23 Core, up to 72MHz
- 64KB Flash, 8KB RAM; G6U6 (32KB/6KB)
- I2C x2; SPI x2; USART x2
- RTC x1
- GPIO x23
- ADC x1
- 1.8V ~ 3.6V, 5V 容忍I/O
- QFN28
- GD32E230xx datasheet
2.2 GD32E230K8U6
- 32 bit Cortex®-M23 Core, up to 72MHz
- 64KB Flash, 8KB RAM; G6U6 (32KB/6KB)
- I2C x2; SPI x2; USART x2
- RTC x1
- GPIO x23
- ADC x1
- 1.8V ~ 3.6V, 5V 容忍I/O
- QFN32
- GD32E230xx datasheet
3 RISC-V
3.1 GD32VF103T8U6
- RISC-V 108MHz
- 64KB Flash/20KB RAM
- up to 26 I/O
- SysTick 24bit Timer x1
- WDG x2, RTC x1
- I2C x1; SPI x1; USART x2; CAN2.0 x2;
- USB OTG
- 12bit ADC x2(10 ch)
- 12bit DAC x2
- QFN36
3.2 GD32VF103TBU6
- RISC-V 108MHz
- 128KB Flash/32KB RAM
- up to 26 I/O
- SysTick 24bit Timer x1
- WDG x2, RTC x1
- I2C x1; SPI x1; USART x2; CAN2.0 x2;
- USB OTG
- 12bit ADC x2(10 ch)
- 12bit DAC x2
- QFN36
4 Boot modes
At startup, boot pins are used to select one of three boot options:
- Boot from main Flash memory (default)
- Boot from system memory
- Boot from on-chip SRAM
In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory).
It is used to reprogram the Flash memory by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15 or PA2 and PA3)
5 Toolchain
5.1 OpenOCD
