查看Noduino Quantum的源代码
←
Noduino Quantum
跳转到:
导航
,
搜索
因为以下原因,你没有权限编辑本页:
您刚才请求的操作只有这个用户组中的用户才能使用:
用户
您可以查看并复制此页面的源代码:
== ESP32 Arch == ESP32 block diagram: [[文件:Esp32-block-diagram.jpg | 600px]] ESP32 use two LX6 core which ISA is xtensa. * Xtensa LX6 Core: http://ip.cadence.com/uploads/533/Cadence_Tensillica_Xtensa_LX6_ds-pdf * Xtensa Instruction Set Architecture: http://0x04.net/~mwk/doc/xtensa.pdf We plan to write the document of the xtensa architecture like the [http://wiki.jackslab.org/MIPS_%E4%BD%93%E7%B3%BB%E7%BB%93%E6%9E%84%E7%9B%B8%E5%85%B3%E6%96%87%E9%9B%86%E6%B1%87%E7%BC%96 MIPS] or [http://www.jackslab.org/?skill-type=%E4%BD%93%E7%B3%BB%E7%BB%93%E6%9E%84 SPARC] The Xtensa instruction set is designed to meet the diverse requirements of dataplane processing. This 32-bit architecture features a compact 16- and 24-bit instruction set with modeless switching for maximum power efficiency and performance. The base instruction set has 80 RISC instructions and includes a 32-bit ALU, up to 64 general-purpose 32-bit registers, and six special-purpose registers. Using this instruction set, you can expect significant code size reductions that result in higher code density and better power dissipation. * [[Xtensa GPR and ABI]] * [[Xtensa Instruction Set]] * [[Xtensa Exception]] * [[Xtensa Memory]] * [[ESP32 SPR]] * [[ESP32 core isa]] <br><br>
返回到
Noduino Quantum
。
个人工具
登录
名字空间
页面
讨论
变换
查看
阅读
查看源代码
查看历史
操作
搜索
导航
首页
社区专页
新闻动态
最近更改
随机页面
帮助
工具箱
链入页面
相关更改
特殊页面