V3S
来自Jack's Lab
(版本间的差异)
(以“== Overview == <br><br> == Block diagram == <br><br> == Reference == <br><br> <br><br><br><br><br><br> <br><br><br><br><br><br>”为内容创建页面) |
(→Overview) |
||
第1行: | 第1行: | ||
== Overview == | == Overview == | ||
+ | |||
+ | * ARM Cortex-A7 MPI | ||
+ | * Thumb-2, NEON | ||
+ | * VFPv4 Floating Point Unit | ||
+ | * 32 KB I-Cache, 32KB D-Cache, 128KB L2 Cache | ||
+ | |||
+ | * Integrated 64MB SiP DDR2, up to 400MHz, Support Memory Dynamic Frequency Scale (MDFS) | ||
+ | |||
+ | * 32 KB Boot ROM | ||
+ | * SPI Nor/Nand flash | ||
+ | * SD/TF card | ||
+ | * eMMC | ||
+ | |||
+ | * USB OTG | ||
+ | |||
+ | * PWM x2 | ||
+ | * RTC | ||
+ | * LRADC, 6-bit resolution, suport hold key and continuous key | ||
+ | * Crypto Engine, AES 128/192/256, DES/TDES, SHA1, MD5 | ||
+ | |||
+ | * Display engine 2.0, output size up to 1024x1024 | ||
<br><br> | <br><br> |
2018年10月24日 (三) 16:37的版本
1 Overview
- ARM Cortex-A7 MPI
- Thumb-2, NEON
- VFPv4 Floating Point Unit
- 32 KB I-Cache, 32KB D-Cache, 128KB L2 Cache
- Integrated 64MB SiP DDR2, up to 400MHz, Support Memory Dynamic Frequency Scale (MDFS)
- 32 KB Boot ROM
- SPI Nor/Nand flash
- SD/TF card
- eMMC
- USB OTG
- PWM x2
- RTC
- LRADC, 6-bit resolution, suport hold key and continuous key
- Crypto Engine, AES 128/192/256, DES/TDES, SHA1, MD5
- Display engine 2.0, output size up to 1024x1024
2 Block diagram
3 Reference