Xtensa Exception
来自Jack's Lab
1 Vector
1.1 ESP32
Exception Vector of ESP32:
Level2Vector = 0x40000180 Level3Vector = 0x400001c0 Level4Vector = 0x40000200 Level5Vector = 0x40000240 DebugExceptionVector = 0x40000280 NMIExceptionVector = 0x400002c0 KernelExceptionVector = 0x40000300 UserExceptionVector = 0x40000340 DoubleExceptionVector = 0x400003c0 ResetVector = 0x40000400 SyscallException = 0x400007cf GeneralException = 0x40000e14 Level2FromVector = 0x40000954 Level3FromVector = 0x40000a28 Level4FromVector = 0x40000af8 Level5FromVector = 0x40000c68 /* include/xtensa/config/core-isa.h */ #define XCHAL_RESET_VECTOR0_VADDR 0x50000000 #define XCHAL_RESET_VECTOR0_PADDR 0x50000000 #define XCHAL_RESET_VECTOR1_VADDR 0x40000400 #define XCHAL_RESET_VECTOR1_PADDR 0x40000400 #define XCHAL_RESET_VECTOR_VADDR 0x40000400 #define XCHAL_RESET_VECTOR_PADDR 0x40000400 #define XCHAL_USER_VECOFS 0x00000340 #define XCHAL_USER_VECTOR_VADDR 0x40000340 #define XCHAL_USER_VECTOR_PADDR 0x40000340 #define XCHAL_KERNEL_VECOFS 0x00000300 #define XCHAL_KERNEL_VECTOR_VADDR 0x40000300 #define XCHAL_KERNEL_VECTOR_PADDR 0x40000300 #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 #define XCHAL_WINDOW_VECTORS_VADDR 0x40000000 #define XCHAL_WINDOW_VECTORS_PADDR 0x40000000 #define XCHAL_INTLEVEL2_VECOFS 0x00000180 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180 #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0 #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0 #define XCHAL_INTLEVEL4_VECOFS 0x00000200 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 #define XCHAL_INTLEVEL5_VECOFS 0x00000240 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240 #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240 #define XCHAL_INTLEVEL6_VECOFS 0x00000280 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR #define XCHAL_NMI_VECOFS 0x000002C0 #define XCHAL_NMI_VECTOR_VADDR 0x400002C0 #define XCHAL_NMI_VECTOR_PADDR 0x400002C0 #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
1.1.1 Reset Exception
0x40000400: j 0x40000450 0x40000403: movltz.s f10, f11, a0 0x40000406: lsi f0, a0, 224 0x40000409: f64cmph a15, a0, a0, 3 0x4000040c: .byte 0xff 0x4000040d: .byte 0xff 0x4000040e: .byte 0xff 0x4000040f: .byte 0x7f 0x40000410: ill 0x40000413: ill 0x40000416: f64cmph a4, a0, a0, 1 0x40000419: l32r a2, 0x3ffc8ca4 0x4000041c: ill 0x4000041f: extui a12, a14, 3, 1 0x40000422: lsi f0, a0, 0x3e0 0x40000425: lsi f13, a0, 0x100 0x40000428: l32i.n a12, a5, 52 0x4000042a: extui a4, a0, 0, 6 0x4000042d: s32i.n a0, a0, 0 0x4000042f: add.s f2, f8, f4 0x40000432: lsi f0, a0, 0x3e0 0x40000435: add.n a0, a0, a0 0x40000437: lsi f4, a8, 24 0x4000043a: .byte 0xfe 0x4000043b: .byte 0x3f 0x4000043c: l32i.n a6, a12, 0 0x4000043e: lsi f0, a0, 0x130 0x40000441: j 0x4001043d 0x40000444: ill 0x40000447: ill ...... ...... 0x40000450: movi a0, 0 0x40000453: wsr.intenable a0 0x40000456: rsr.prid a2 0x40000459: l32r a3, 0x40000404 0x4000045c: bne a2, a3, 0x40000471 0x4000045f: l32r a3, 0x40000408 0x40000462: l32i a3, a3, 0 0x40000465: bbci a3, 31, 0x40000471 0x40000468: l32r a2, 0x4000040c 0x4000046b: and a3, a3, a2 0x4000046e: callx0 a3 0x40000471: l32r a2, 0x40000410 0x40000474: rsr.prid a3 0x40000477: extui a3, a3, 0, 8 0x4000047a: beqz.n a2, 0x40000480 0x4000047c: bnez.n a3, 0x40000480 0x4000047e: s32i.n a0, a2, 0 0x40000480: l32r a2, 0x40000414 0x40000483: wsr.vecbase a2 0x40000486: movi.n a3, 21 0x40000488: wsr.atomctl a3 0x4000048b: rsil a2, 1 0x4000048e: l32r a2, 0x40000418 0x40000491: l32r a5, 0x4000041c 0x40000494: l32r a6, 0x40000420 0x40000497: movi.n a3, 0 0x40000499: mov.n a7, a2 0x4000049b: and a6, a6, a5 0x4000049e: j 0x400004c3 0x400004a1: ill 0x400004a4: ill 0x400004a7: ill ...... ......