Xtensa L106 Architecture
来自Jack's Lab
1 Overview
- Small, low power 32-bit RISC controller core, Xtensa ISA
- Cache-less processor with memory protection unit
- 5-stage pipeline
- Dhrystone 2.1: 1.22 DMIPS/MHz
- 24/16-bit ISA with modeless switching
- Iterative 32x32 multiplier
- Separate instruction and data memory interfaces
- Integrated interrupt controller with 15 interrupts at 2 priority levels
- 32-bit ALU
- 16 GPRs
2 See also
- Xtensa Instruction Set Architecture: http://0x04.net/~mwk/doc/xtensa.pdf
